63 int mt8192_set_audio_int_bus_parent(struct mtk_base_afe *afe,  in mt8192_set_audio_int_bus_parent()  argument
66 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in mt8192_set_audio_int_bus_parent()
72 		dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in mt8192_set_audio_int_bus_parent()
80 static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)  in apll1_mux_setting()  argument
82 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in apll1_mux_setting()
88 			dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in apll1_mux_setting()
95 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll1_mux_setting()
104 			dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in apll1_mux_setting()
111 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll1_mux_setting()
120 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll1_mux_setting()
130 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll1_mux_setting()
142 static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)  in apll2_mux_setting()  argument
144 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in apll2_mux_setting()
150 			dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in apll2_mux_setting()
157 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll2_mux_setting()
166 			dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in apll2_mux_setting()
173 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll2_mux_setting()
182 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll2_mux_setting()
192 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll2_mux_setting()
204 int mt8192_afe_enable_clock(struct mtk_base_afe *afe)  in mt8192_afe_enable_clock()  argument
206 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in mt8192_afe_enable_clock()
211 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8192_afe_enable_clock()
218 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8192_afe_enable_clock()
225 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8192_afe_enable_clock()
232 		dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in mt8192_afe_enable_clock()
240 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8192_afe_enable_clock()
245 	ret = mt8192_set_audio_int_bus_parent(afe, CLK_CLK26M);  in mt8192_afe_enable_clock()
247 		dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in mt8192_afe_enable_clock()
256 		dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in mt8192_afe_enable_clock()
264 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8192_afe_enable_clock()
273 void mt8192_afe_disable_clock(struct mtk_base_afe *afe)  in mt8192_afe_disable_clock()  argument
275 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in mt8192_afe_disable_clock()
278 	mt8192_set_audio_int_bus_parent(afe, CLK_CLK26M);  in mt8192_afe_disable_clock()
285 int mt8192_apll1_enable(struct mtk_base_afe *afe)  in mt8192_apll1_enable()  argument
287 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in mt8192_apll1_enable()
291 	apll1_mux_setting(afe, true);  in mt8192_apll1_enable()
295 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8192_apll1_enable()
302 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8192_apll1_enable()
307 	regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,  in mt8192_apll1_enable()
309 	regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x1);  in mt8192_apll1_enable()
311 	regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,  in mt8192_apll1_enable()
319 void mt8192_apll1_disable(struct mtk_base_afe *afe)  in mt8192_apll1_disable()  argument
321 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in mt8192_apll1_disable()
323 	regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,  in mt8192_apll1_disable()
327 	regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x0);  in mt8192_apll1_disable()
332 	apll1_mux_setting(afe, false);  in mt8192_apll1_disable()
335 int mt8192_apll2_enable(struct mtk_base_afe *afe)  in mt8192_apll2_enable()  argument
337 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in mt8192_apll2_enable()
341 	apll2_mux_setting(afe, true);  in mt8192_apll2_enable()
345 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8192_apll2_enable()
352 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8192_apll2_enable()
357 	regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,  in mt8192_apll2_enable()
359 	regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x1);  in mt8192_apll2_enable()
361 	regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,  in mt8192_apll2_enable()
369 void mt8192_apll2_disable(struct mtk_base_afe *afe)  in mt8192_apll2_disable()  argument
371 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in mt8192_apll2_disable()
373 	regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,  in mt8192_apll2_disable()
377 	regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x0);  in mt8192_apll2_disable()
382 	apll2_mux_setting(afe, false);  in mt8192_apll2_disable()
385 int mt8192_get_apll_rate(struct mtk_base_afe *afe, int apll)  in mt8192_get_apll_rate()  argument
390 int mt8192_get_apll_by_rate(struct mtk_base_afe *afe, int rate)  in mt8192_get_apll_by_rate()  argument
395 int mt8192_get_apll_by_name(struct mtk_base_afe *afe, const char *name)  in mt8192_get_apll_by_name()  argument
562 int mt8192_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)  in mt8192_mck_enable()  argument
564 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in mt8192_mck_enable()
565 	int apll = mt8192_get_apll_by_rate(afe, rate);  in mt8192_mck_enable()
576 			dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",  in mt8192_mck_enable()
583 			dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",  in mt8192_mck_enable()
593 		dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",  in mt8192_mck_enable()
599 		dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n",  in mt8192_mck_enable()
608 void mt8192_mck_disable(struct mtk_base_afe *afe, int mck_id)  in mt8192_mck_disable()  argument
610 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in mt8192_mck_disable()
619 int mt8192_init_clock(struct mtk_base_afe *afe)  in mt8192_init_clock()  argument
621 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in mt8192_init_clock()
622 	struct device_node *of_node = afe->dev->of_node;  in mt8192_init_clock()
625 	afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),  in mt8192_init_clock()
631 		afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);  in mt8192_init_clock()
633 			dev_warn(afe->dev, "%s devm_clk_get %s fail, ret %ld\n",  in mt8192_init_clock()
643 		dev_err(afe->dev, "%s() Cannot find apmixedsys controller: %ld\n",  in mt8192_init_clock()
651 		dev_err(afe->dev, "%s() Cannot find topckgen controller: %ld\n",  in mt8192_init_clock()
659 		dev_err(afe->dev, "%s() Cannot find infracfg: %ld\n",  in mt8192_init_clock()