Lines Matching refs:afe_priv
94 struct mt8183_afe_private *afe_priv = afe->platform_priv; in mt8183_init_clock() local
97 afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk), in mt8183_init_clock()
99 if (!afe_priv->clk) in mt8183_init_clock()
103 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]); in mt8183_init_clock()
104 if (IS_ERR(afe_priv->clk[i])) { in mt8183_init_clock()
107 PTR_ERR(afe_priv->clk[i])); in mt8183_init_clock()
108 return PTR_ERR(afe_priv->clk[i]); in mt8183_init_clock()
117 struct mt8183_afe_private *afe_priv = afe->platform_priv; in mt8183_afe_enable_clock() local
120 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]); in mt8183_afe_enable_clock()
127 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]); in mt8183_afe_enable_clock()
134 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO], in mt8183_afe_enable_clock()
135 afe_priv->clk[CLK_CLK26M]); in mt8183_afe_enable_clock()
143 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); in mt8183_afe_enable_clock()
150 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], in mt8183_afe_enable_clock()
151 afe_priv->clk[CLK_TOP_SYSPLL_D2_D4]); in mt8183_afe_enable_clock()
159 ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]); in mt8183_afe_enable_clock()
166 ret = clk_prepare_enable(afe_priv->clk[CLK_I2S1_BCLK_SW]); in mt8183_afe_enable_clock()
173 ret = clk_prepare_enable(afe_priv->clk[CLK_I2S2_BCLK_SW]); in mt8183_afe_enable_clock()
180 ret = clk_prepare_enable(afe_priv->clk[CLK_I2S3_BCLK_SW]); in mt8183_afe_enable_clock()
187 ret = clk_prepare_enable(afe_priv->clk[CLK_I2S4_BCLK_SW]); in mt8183_afe_enable_clock()
197 clk_disable_unprepare(afe_priv->clk[CLK_I2S3_BCLK_SW]); in mt8183_afe_enable_clock()
199 clk_disable_unprepare(afe_priv->clk[CLK_I2S2_BCLK_SW]); in mt8183_afe_enable_clock()
201 clk_disable_unprepare(afe_priv->clk[CLK_I2S1_BCLK_SW]); in mt8183_afe_enable_clock()
203 clk_disable_unprepare(afe_priv->clk[CLK_AFE]); in mt8183_afe_enable_clock()
205 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); in mt8183_afe_enable_clock()
207 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]); in mt8183_afe_enable_clock()
209 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]); in mt8183_afe_enable_clock()
216 struct mt8183_afe_private *afe_priv = afe->platform_priv; in mt8183_afe_disable_clock() local
218 clk_disable_unprepare(afe_priv->clk[CLK_I2S4_BCLK_SW]); in mt8183_afe_disable_clock()
219 clk_disable_unprepare(afe_priv->clk[CLK_I2S3_BCLK_SW]); in mt8183_afe_disable_clock()
220 clk_disable_unprepare(afe_priv->clk[CLK_I2S2_BCLK_SW]); in mt8183_afe_disable_clock()
221 clk_disable_unprepare(afe_priv->clk[CLK_I2S1_BCLK_SW]); in mt8183_afe_disable_clock()
222 clk_disable_unprepare(afe_priv->clk[CLK_AFE]); in mt8183_afe_disable_clock()
223 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); in mt8183_afe_disable_clock()
224 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]); in mt8183_afe_disable_clock()
225 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]); in mt8183_afe_disable_clock()
233 struct mt8183_afe_private *afe_priv = afe->platform_priv; in apll1_mux_setting() local
237 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]); in apll1_mux_setting()
243 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
244 afe_priv->clk[CLK_TOP_APLL1_CK]); in apll1_mux_setting()
253 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]); in apll1_mux_setting()
259 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
260 afe_priv->clk[CLK_TOP_APLL1_D8]); in apll1_mux_setting()
268 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
269 afe_priv->clk[CLK_CLK26M]); in apll1_mux_setting()
276 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]); in apll1_mux_setting()
278 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
279 afe_priv->clk[CLK_CLK26M]); in apll1_mux_setting()
286 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]); in apll1_mux_setting()
292 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
293 afe_priv->clk[CLK_CLK26M]); in apll1_mux_setting()
294 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]); in apll1_mux_setting()
297 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
298 afe_priv->clk[CLK_CLK26M]); in apll1_mux_setting()
299 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]); in apll1_mux_setting()
307 struct mt8183_afe_private *afe_priv = afe->platform_priv; in apll2_mux_setting() local
311 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]); in apll2_mux_setting()
317 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
318 afe_priv->clk[CLK_TOP_APLL2_CK]); in apll2_mux_setting()
327 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]); in apll2_mux_setting()
333 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], in apll2_mux_setting()
334 afe_priv->clk[CLK_TOP_APLL2_D8]); in apll2_mux_setting()
342 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], in apll2_mux_setting()
343 afe_priv->clk[CLK_CLK26M]); in apll2_mux_setting()
350 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]); in apll2_mux_setting()
352 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
353 afe_priv->clk[CLK_CLK26M]); in apll2_mux_setting()
360 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]); in apll2_mux_setting()
366 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], in apll2_mux_setting()
367 afe_priv->clk[CLK_CLK26M]); in apll2_mux_setting()
368 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]); in apll2_mux_setting()
371 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
372 afe_priv->clk[CLK_CLK26M]); in apll2_mux_setting()
373 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]); in apll2_mux_setting()
381 struct mt8183_afe_private *afe_priv = afe->platform_priv; in mt8183_apll1_enable() local
387 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]); in mt8183_apll1_enable()
394 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]); in mt8183_apll1_enable()
412 clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]); in mt8183_apll1_enable()
419 struct mt8183_afe_private *afe_priv = afe->platform_priv; in mt8183_apll1_disable() local
427 clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]); in mt8183_apll1_disable()
428 clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]); in mt8183_apll1_disable()
435 struct mt8183_afe_private *afe_priv = afe->platform_priv; in mt8183_apll2_enable() local
441 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]); in mt8183_apll2_enable()
448 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]); in mt8183_apll2_enable()
466 clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]); in mt8183_apll2_enable()
473 struct mt8183_afe_private *afe_priv = afe->platform_priv; in mt8183_apll2_disable() local
481 clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]); in mt8183_apll2_disable()
482 clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]); in mt8183_apll2_disable()
544 struct mt8183_afe_private *afe_priv = afe->platform_priv; in mt8183_mck_enable() local
558 ret = clk_prepare_enable(afe_priv->clk[m_sel_id]); in mt8183_mck_enable()
564 ret = clk_set_parent(afe_priv->clk[m_sel_id], in mt8183_mck_enable()
565 afe_priv->clk[apll_clk_id]); in mt8183_mck_enable()
575 ret = clk_prepare_enable(afe_priv->clk[div_clk_id]); in mt8183_mck_enable()
581 ret = clk_set_rate(afe_priv->clk[div_clk_id], rate); in mt8183_mck_enable()
592 clk_disable_unprepare(afe_priv->clk[div_clk_id]); in mt8183_mck_enable()
596 clk_disable_unprepare(afe_priv->clk[m_sel_id]); in mt8183_mck_enable()
603 struct mt8183_afe_private *afe_priv = afe->platform_priv; in mt8183_mck_disable() local
611 clk_disable_unprepare(afe_priv->clk[div_clk_id]); in mt8183_mck_disable()
613 clk_disable_unprepare(afe_priv->clk[m_sel_id]); in mt8183_mck_disable()