36 	via_write_reg_mask(VIACR, 0x11, 0x00, 0x80);  in via_set_primary_timing()
38 	via_write_reg(VIACR, 0x00, raw.hor_total & 0xFF);  in via_set_primary_timing()
39 	via_write_reg(VIACR, 0x01, raw.hor_addr & 0xFF);  in via_set_primary_timing()
40 	via_write_reg(VIACR, 0x02, raw.hor_blank_start & 0xFF);  in via_set_primary_timing()
41 	via_write_reg_mask(VIACR, 0x03, raw.hor_blank_end & 0x1F, 0x1F);  in via_set_primary_timing()
42 	via_write_reg(VIACR, 0x04, raw.hor_sync_start & 0xFF);  in via_set_primary_timing()
43 	via_write_reg_mask(VIACR, 0x05, (raw.hor_sync_end & 0x1F)  in via_set_primary_timing()
45 	via_write_reg(VIACR, 0x06, raw.ver_total & 0xFF);  in via_set_primary_timing()
46 	via_write_reg_mask(VIACR, 0x07, (raw.ver_total >> 8 & 0x01)  in via_set_primary_timing()
53 	via_write_reg_mask(VIACR, 0x09, raw.ver_blank_start >> (9 - 5) & 0x20,  in via_set_primary_timing()
55 	via_write_reg(VIACR, 0x10, raw.ver_sync_start & 0xFF);  in via_set_primary_timing()
56 	via_write_reg_mask(VIACR, 0x11, raw.ver_sync_end & 0x0F, 0x0F);  in via_set_primary_timing()
57 	via_write_reg(VIACR, 0x12, raw.ver_addr & 0xFF);  in via_set_primary_timing()
58 	via_write_reg(VIACR, 0x15, raw.ver_blank_start & 0xFF);  in via_set_primary_timing()
59 	via_write_reg(VIACR, 0x16, raw.ver_blank_end & 0xFF);  in via_set_primary_timing()
60 	via_write_reg_mask(VIACR, 0x33, (raw.hor_sync_start >> (8 - 4) & 0x10)  in via_set_primary_timing()
62 	via_write_reg_mask(VIACR, 0x35, (raw.ver_total >> 10 & 0x01)  in via_set_primary_timing()
66 	via_write_reg_mask(VIACR, 0x36, raw.hor_total >> (8 - 3) & 0x08, 0x08);  in via_set_primary_timing()
69 	via_write_reg_mask(VIACR, 0x11, 0x80, 0x80);  in via_set_primary_timing()
72 	via_write_reg_mask(VIACR, 0x17, 0x00, 0x80);  in via_set_primary_timing()
73 	via_write_reg_mask(VIACR, 0x17, 0x80, 0x80);  in via_set_primary_timing()
93 	via_write_reg(VIACR, 0x50, raw.hor_total & 0xFF);  in via_set_secondary_timing()
94 	via_write_reg(VIACR, 0x51, raw.hor_addr & 0xFF);  in via_set_secondary_timing()
95 	via_write_reg(VIACR, 0x52, raw.hor_blank_start & 0xFF);  in via_set_secondary_timing()
96 	via_write_reg(VIACR, 0x53, raw.hor_blank_end & 0xFF);  in via_set_secondary_timing()
97 	via_write_reg(VIACR, 0x54, (raw.hor_blank_start >> 8 & 0x07)  in via_set_secondary_timing()
100 	via_write_reg_mask(VIACR, 0x55, (raw.hor_total >> 8 & 0x0F)  in via_set_secondary_timing()
102 	via_write_reg(VIACR, 0x56, raw.hor_sync_start & 0xFF);  in via_set_secondary_timing()
103 	via_write_reg(VIACR, 0x57, raw.hor_sync_end & 0xFF);  in via_set_secondary_timing()
104 	via_write_reg(VIACR, 0x58, raw.ver_total & 0xFF);  in via_set_secondary_timing()
105 	via_write_reg(VIACR, 0x59, raw.ver_addr & 0xFF);  in via_set_secondary_timing()
106 	via_write_reg(VIACR, 0x5A, raw.ver_blank_start & 0xFF);  in via_set_secondary_timing()
107 	via_write_reg(VIACR, 0x5B, raw.ver_blank_end & 0xFF);  in via_set_secondary_timing()
108 	via_write_reg(VIACR, 0x5C, (raw.ver_blank_start >> 8 & 0x07)  in via_set_secondary_timing()
112 	via_write_reg(VIACR, 0x5D, (raw.ver_total >> 8 & 0x07)  in via_set_secondary_timing()
116 	via_write_reg(VIACR, 0x5E, raw.ver_sync_start & 0xFF);  in via_set_secondary_timing()
117 	via_write_reg(VIACR, 0x5F, (raw.ver_sync_end & 0x1F)  in via_set_secondary_timing()
124 	via_write_reg(VIACR, 0x0D, addr & 0xFF);  in via_set_primary_address()
125 	via_write_reg(VIACR, 0x0C, (addr >> 8) & 0xFF);  in via_set_primary_address()
126 	via_write_reg(VIACR, 0x34, (addr >> 16) & 0xFF);  in via_set_primary_address()
127 	via_write_reg_mask(VIACR, 0x48, (addr >> 24) & 0x1F, 0x1F);  in via_set_primary_address()
134 	via_write_reg_mask(VIACR, 0x62, (addr >> 2) & 0xFE, 0xFE);  in via_set_secondary_address()
135 	via_write_reg(VIACR, 0x63, (addr >> 10) & 0xFF);  in via_set_secondary_address()
136 	via_write_reg(VIACR, 0x64, (addr >> 18) & 0xFF);  in via_set_secondary_address()
137 	via_write_reg_mask(VIACR, 0xA3, (addr >> 26) & 0x07, 0x07);  in via_set_secondary_address()
147 	via_write_reg(VIACR, 0x13, pitch & 0xFF);  in via_set_primary_pitch()
148 	via_write_reg_mask(VIACR, 0x35, (pitch >> (8 - 5)) & 0xE0, 0xE0);  in via_set_primary_pitch()
155 	via_write_reg(VIACR, 0x66, pitch & 0xFF);  in via_set_secondary_pitch()
156 	via_write_reg_mask(VIACR, 0x67, (pitch >> 8) & 0x03, 0x03);  in via_set_secondary_pitch()
157 	via_write_reg_mask(VIACR, 0x71, (pitch >> (10 - 7)) & 0x80, 0x80);  in via_set_secondary_pitch()
214 	via_write_reg_mask(VIACR, 0x67, value, 0xC0);  in via_set_secondary_color_depth()