90 	{VIACR, CR7A, 0xFF, 0x01},	/* LCD Scaling Parameter 1 */
91 	{VIACR, CR7B, 0xFF, 0x02},	/* LCD Scaling Parameter 2 */
92 	{VIACR, CR7C, 0xFF, 0x03},	/* LCD Scaling Parameter 3 */
93 	{VIACR, CR7D, 0xFF, 0x04},	/* LCD Scaling Parameter 4 */
94 	{VIACR, CR7E, 0xFF, 0x07},	/* LCD Scaling Parameter 5 */
95 	{VIACR, CR7F, 0xFF, 0x0A},	/* LCD Scaling Parameter 6 */
96 	{VIACR, CR80, 0xFF, 0x0D},	/* LCD Scaling Parameter 7 */
97 	{VIACR, CR81, 0xFF, 0x13},	/* LCD Scaling Parameter 8 */
98 	{VIACR, CR82, 0xFF, 0x16},	/* LCD Scaling Parameter 9 */
99 	{VIACR, CR83, 0xFF, 0x19},	/* LCD Scaling Parameter 10 */
100 	{VIACR, CR84, 0xFF, 0x1C},	/* LCD Scaling Parameter 11 */
101 	{VIACR, CR85, 0xFF, 0x1D},	/* LCD Scaling Parameter 12 */
102 	{VIACR, CR86, 0xFF, 0x1E},	/* LCD Scaling Parameter 13 */
103 	{VIACR, CR87, 0xFF, 0x1F},	/* LCD Scaling Parameter 14 */
107 	{VIACR, CR07, 0x10, 0x10}, /* [0] vertical total (bit 8)
115 	{VIACR, CR08, 0xFF, 0x00}, /* [0-4] preset row scan
117 	{VIACR, CR09, 0xDF, 0x40}, /* [0-4] max scan line
121 	{VIACR, CR0A, 0xFF, 0x1E}, /* [0-4] cursor start
123 	{VIACR, CR0B, 0xFF, 0x00}, /* [0-4] cursor end
125 	{VIACR, CR0E, 0xFF, 0x00}, /* [0-7] cursor location (high) */
126 	{VIACR, CR0F, 0xFF, 0x00}, /* [0-7] cursor location (low) */
127 	{VIACR, CR11, 0xF0, 0x80}, /* [0-3] vertical retrace end
130 	{VIACR, CR14, 0xFF, 0x00}, /* [0-4] underline location
133 	{VIACR, CR17, 0xFF, 0x63}, /* [0-1] mapping of display address 13-14
139 	{VIACR, CR18, 0xFF, 0xFF}, /* [0-7] line compare */
466 	viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);  in viafb_lock_crt()
471 	viafb_write_reg_mask(CR11, VIACR, 0, BIT7);  in viafb_unlock_crt()
472 	viafb_write_reg_mask(CR47, VIACR, 0, BIT0);  in viafb_unlock_crt()
694 	via_write_reg_mask(VIACR, index, value, mask);  in set_source_common()
785 	via_write_reg_mask(VIACR, 0x36, value, 0x30);  in set_crt_state()
890 		via_write_reg_mask(VIACR, 0x9B, polarity << 5, 0x60);  in via_set_sync_polarity()
892 		via_write_reg_mask(VIACR, 0x99, polarity << 5, 0x60);  in via_set_sync_polarity()
894 		via_write_reg_mask(VIACR, 0x97, polarity << 5, 0x60);  in via_set_sync_polarity()
945 	viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);  in load_fix_bit_crtc_reg()
947 	viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);  in load_fix_bit_crtc_reg()
949 	viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);  in load_fix_bit_crtc_reg()
957 		viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);  in load_fix_bit_crtc_reg()
992 		if (io_type == VIACR)  in viafb_load_reg()
993 			viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);  in viafb_load_reg()
1031 		viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);  in viafb_load_fetch_count_reg()
1320 				viafb_load_reg_num, reg, VIACR);  in viafb_load_FIFO_reg()
1333 				viafb_load_reg_num, reg, VIACR);  in viafb_load_FIFO_reg()
1344 		viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);  in viafb_load_FIFO_reg()
1355 		viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);  in viafb_load_FIFO_reg()
1367 		viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);  in viafb_load_FIFO_reg()
1537 		tmp = viafb_read_reg(VIACR, CR4F);  in init_gfx_chip_info()
1538 		viafb_write_reg(CR4F, VIACR, 0x55);  in init_gfx_chip_info()
1539 		if (viafb_read_reg(VIACR, CR4F) != 0x55)  in init_gfx_chip_info()
1546 		viafb_write_reg(CR4F, VIACR, tmp);  in init_gfx_chip_info()
1678 		tmp = viafb_read_reg(VIACR, CR6A);  in viafb_init_dac()
1680 		viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);  in viafb_init_dac()
1689 		viafb_write_reg(CR6A, VIACR, tmp);  in viafb_init_dac()
1713 		viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);  in set_display_channel()
1717 		viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);  in set_display_channel()
1720 		viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);  in set_display_channel()
1725 			viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);  in set_display_channel()
1728 			viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);  in set_display_channel()
1786 	via_write_reg_mask(VIACR, 0x45, 0x00, 0x01);  in hw_init()
1789 	via_write_reg_mask(VIACR, 0xFD, 0, 0x80); /* VX900 hw scale on IGA2 */  in hw_init()
1890 			viafb_write_reg(CR02, VIACR,  in viafb_setmode()
1891 				viafb_read_reg(VIACR, CR02) - 1);  in viafb_setmode()
2033 	viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);  in enable_second_display_channel()
2034 	viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);  in enable_second_display_channel()
2035 	viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);  in enable_second_display_channel()
2041 	viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);  in disable_second_display_channel()
2042 	viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);  in disable_second_display_channel()
2043 	viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);  in disable_second_display_channel()
2053 			viafb_write_reg_mask(CR96, VIACR,  in viafb_set_dpa_gfx()
2072 			viafb_write_reg_mask(CR9B, VIACR,  in viafb_set_dpa_gfx()
2083 			viafb_write_reg_mask(CR97, VIACR,  in viafb_set_dpa_gfx()
2090 			viafb_write_reg_mask(CR99, VIACR,  in viafb_set_dpa_gfx()
2097 			viafb_write_reg_mask(CR97, VIACR,  in viafb_set_dpa_gfx()
2099 			viafb_write_reg_mask(CR99, VIACR,  in viafb_set_dpa_gfx()