Lines Matching refs:NO_VIRT
118 #define NO_VIRT 0 macro
674 p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE); in init_pci_cap_basic_perm()
675 p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE); in init_pci_cap_basic_perm()
676 p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE); in init_pci_cap_basic_perm()
864 p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE); in init_pci_cap_pcix_perm()
865 p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE); in init_pci_cap_pcix_perm()
949 p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI); in init_pci_cap_exp_perm()
1035 p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask); in init_pci_ext_cap_err_perm()
1036 p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask); in init_pci_ext_cap_err_perm()
1037 p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask); in init_pci_ext_cap_err_perm()
1047 p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask); in init_pci_ext_cap_err_perm()
1048 p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask); in init_pci_ext_cap_err_perm()
1052 p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask); in init_pci_ext_cap_err_perm()
1065 p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE); in init_pci_ext_cap_pwr_perm()
1216 p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE); in init_pci_cap_msi_perm()
1217 p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE); in init_pci_cap_msi_perm()
1222 p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE); in init_pci_cap_msi_perm()
1223 p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE); in init_pci_cap_msi_perm()