Lines Matching refs:temp
258 u16 temp; in xhci_common_hub_descriptor() local
263 temp = 0; in xhci_common_hub_descriptor()
266 temp |= HUB_CHAR_INDV_PORT_LPSM; in xhci_common_hub_descriptor()
268 temp |= HUB_CHAR_NO_LPSM; in xhci_common_hub_descriptor()
271 temp |= HUB_CHAR_INDV_PORT_OCPM; in xhci_common_hub_descriptor()
274 desc->wHubCharacteristics = cpu_to_le16(temp); in xhci_common_hub_descriptor()
282 u16 temp; in xhci_usb2_hub_descriptor() local
292 temp = 1 + (ports / 8); in xhci_usb2_hub_descriptor()
293 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; in xhci_usb2_hub_descriptor()
681 u32 temp; in xhci_set_port_power() local
684 temp = readl(port->addr); in xhci_set_port_power()
687 hcd->self.busnum, port->hcd_portnum + 1, on ? "ON" : "OFF", temp); in xhci_set_port_power()
689 temp = xhci_port_state_to_neutral(temp); in xhci_set_port_power()
693 writel(temp | PORT_POWER, port->addr); in xhci_set_port_power()
697 writel(temp & ~PORT_POWER, port->addr); in xhci_set_port_power()
701 temp = usb_acpi_power_manageable(hcd->self.root_hub, in xhci_set_port_power()
703 if (temp) in xhci_set_port_power()
712 u32 temp; in xhci_port_set_test_mode() local
717 temp = readl(port->addr + PORTPMSC); in xhci_port_set_test_mode()
718 temp |= test_mode << PORT_TEST_MODE_SHIFT; in xhci_port_set_test_mode()
719 writel(temp, port->addr + PORTPMSC); in xhci_port_set_test_mode()
790 u32 temp; in xhci_set_link_state() local
794 temp = xhci_port_state_to_neutral(portsc); in xhci_set_link_state()
795 temp &= ~PORT_PLS_MASK; in xhci_set_link_state()
796 temp |= PORT_LINK_STROBE | link_state; in xhci_set_link_state()
797 writel(temp, port->addr); in xhci_set_link_state()
801 portsc, temp); in xhci_set_link_state()
807 u32 temp; in xhci_set_remote_wake_mask() local
809 temp = readl(port->addr); in xhci_set_remote_wake_mask()
810 temp = xhci_port_state_to_neutral(temp); in xhci_set_remote_wake_mask()
813 temp |= PORT_WKCONN_E; in xhci_set_remote_wake_mask()
815 temp &= ~PORT_WKCONN_E; in xhci_set_remote_wake_mask()
818 temp |= PORT_WKDISC_E; in xhci_set_remote_wake_mask()
820 temp &= ~PORT_WKDISC_E; in xhci_set_remote_wake_mask()
823 temp |= PORT_WKOC_E; in xhci_set_remote_wake_mask()
825 temp &= ~PORT_WKOC_E; in xhci_set_remote_wake_mask()
827 writel(temp, port->addr); in xhci_set_remote_wake_mask()
834 u32 temp; in xhci_test_and_clear_bit() local
836 temp = readl(port->addr); in xhci_test_and_clear_bit()
837 if (temp & port_bit) { in xhci_test_and_clear_bit()
838 temp = xhci_port_state_to_neutral(temp); in xhci_test_and_clear_bit()
839 temp |= port_bit; in xhci_test_and_clear_bit()
840 writel(temp, port->addr); in xhci_test_and_clear_bit()
1203 u32 temp, status; in xhci_hub_control() local
1259 temp = readl(port->addr); in xhci_hub_control()
1260 if (temp == ~(u32)0) { in xhci_hub_control()
1265 trace_xhci_get_port_status(wIndex, temp); in xhci_hub_control()
1266 status = xhci_get_port_status(hcd, bus_state, wIndex, temp, in xhci_hub_control()
1272 hcd->self.busnum, portnum1, temp, status); in xhci_hub_control()
1285 status = xhci_get_ext_port_status(temp, port_li); in xhci_hub_control()
1305 temp = readl(port->addr); in xhci_hub_control()
1306 if (temp == ~(u32)0) { in xhci_hub_control()
1311 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1315 temp = readl(port->addr); in xhci_hub_control()
1316 if ((temp & PORT_PLS_MASK) != XDEV_U0) { in xhci_hub_control()
1327 temp = readl(port->addr); in xhci_hub_control()
1328 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) in xhci_hub_control()
1329 || (temp & PORT_PLS_MASK) >= XDEV_U3) { in xhci_hub_control()
1352 temp = readl(port->addr); in xhci_hub_control()
1356 temp = readl(port->addr); in xhci_hub_control()
1361 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1366 temp |= PORT_CSC | PORT_PEC | PORT_WRC | in xhci_hub_control()
1369 writel(temp | PORT_PE, port->addr); in xhci_hub_control()
1370 temp = readl(port->addr); in xhci_hub_control()
1379 temp = readl(port->addr); in xhci_hub_control()
1403 if ((temp & PORT_CONNECT)) { in xhci_hub_control()
1412 temp = readl(port->addr); in xhci_hub_control()
1416 if (!(temp & PORT_PE)) { in xhci_hub_control()
1435 u32 pls = temp & PORT_PLS_MASK; in xhci_hub_control()
1460 temp = readl(port->addr); in xhci_hub_control()
1480 temp = readl(port->addr); in xhci_hub_control()
1481 if ((temp & PORT_PLS_MASK) == XDEV_U3) in xhci_hub_control()
1485 temp = readl(port->addr); in xhci_hub_control()
1499 temp = (temp | PORT_RESET); in xhci_hub_control()
1500 writel(temp, port->addr); in xhci_hub_control()
1502 temp = readl(port->addr); in xhci_hub_control()
1504 hcd->self.busnum, portnum1, temp); in xhci_hub_control()
1508 temp = readl(port->addr); in xhci_hub_control()
1510 hcd->self.busnum, portnum1, temp); in xhci_hub_control()
1513 temp |= PORT_WR; in xhci_hub_control()
1514 writel(temp, port->addr); in xhci_hub_control()
1515 temp = readl(port->addr); in xhci_hub_control()
1520 temp = readl(port->addr + PORTPMSC); in xhci_hub_control()
1521 temp &= ~PORT_U1_TIMEOUT_MASK; in xhci_hub_control()
1522 temp |= PORT_U1_TIMEOUT(timeout); in xhci_hub_control()
1523 writel(temp, port->addr + PORTPMSC); in xhci_hub_control()
1528 temp = readl(port->addr + PORTPMSC); in xhci_hub_control()
1529 temp &= ~PORT_U2_TIMEOUT_MASK; in xhci_hub_control()
1530 temp |= PORT_U2_TIMEOUT(timeout); in xhci_hub_control()
1531 writel(temp, port->addr + PORTPMSC); in xhci_hub_control()
1547 temp = readl(port->addr); in xhci_hub_control()
1556 temp = readl(port->addr); in xhci_hub_control()
1557 if (temp == ~(u32)0) { in xhci_hub_control()
1563 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1566 temp = readl(port->addr); in xhci_hub_control()
1568 xhci_dbg(xhci, "PORTSC %04x\n", temp); in xhci_hub_control()
1569 if (temp & PORT_RESET) in xhci_hub_control()
1571 if ((temp & PORT_PLS_MASK) == XDEV_U3) { in xhci_hub_control()
1572 if ((temp & PORT_PE) == 0) in xhci_hub_control()
1606 port->addr, temp); in xhci_hub_control()
1642 u32 temp, status; in xhci_hub_status_data() local
1684 temp = readl(ports[i]->addr); in xhci_hub_status_data()
1685 if (temp == ~(u32)0) { in xhci_hub_status_data()
1690 trace_xhci_hub_status_data(i, temp); in xhci_hub_status_data()
1692 if ((temp & mask) != 0 || in xhci_hub_status_data()
1699 if ((temp & PORT_RC)) in xhci_hub_status_data()
1701 if (temp & PORT_OC) in xhci_hub_status_data()
1883 u32 temp, portsc; in xhci_bus_resume() local
1902 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1903 temp &= ~CMD_EIE; in xhci_bus_resume()
1904 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1981 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1982 temp |= CMD_EIE; in xhci_bus_resume()
1983 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1984 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()