119 	struct geni_se se;  member
196 	port->se.base = uport->membase;  in qcom_geni_serial_request_port()
493 		geni_se_cancel_m_cmd(&port->se);  in qcom_geni_serial_console_write()
496 			geni_se_abort_m_cmd(&port->se);  in qcom_geni_serial_console_write()
599 		geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr,  in qcom_geni_serial_stop_tx_dma()
605 	geni_se_cancel_m_cmd(&port->se);  in qcom_geni_serial_stop_tx_dma()
610 		geni_se_abort_m_cmd(&port->se);  in qcom_geni_serial_stop_tx_dma()
638 	ret = geni_se_tx_dma_prep(&port->se, &xmit->buf[xmit->tail],  in qcom_geni_serial_start_tx_dma()
677 	geni_se_cancel_m_cmd(&port->se);  in qcom_geni_serial_stop_tx_fifo()
680 		geni_se_abort_m_cmd(&port->se);  in qcom_geni_serial_stop_tx_fifo()
729 	geni_se_cancel_s_cmd(&port->se);  in qcom_geni_serial_stop_rx_fifo()
754 	geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);  in qcom_geni_serial_start_rx_fifo()
772 	geni_se_cancel_s_cmd(&port->se);  in qcom_geni_serial_stop_rx_dma()
780 		geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr,  in qcom_geni_serial_stop_rx_dma()
794 	geni_se_setup_s_cmd(&port->se, UART_START_READ, UART_PARAM_RFR_OPEN);  in qcom_geni_serial_start_rx_dma()
796 	ret = geni_se_rx_dma_prep(&port->se, port->rx_buf,  in qcom_geni_serial_start_rx_dma()
817 	geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, DMA_RX_BUF_SIZE);  in qcom_geni_serial_handle_rx_dma()
829 	ret = geni_se_rx_dma_prep(&port->se, port->rx_buf,  in qcom_geni_serial_handle_rx_dma()
945 	geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, port->tx_remaining);  in qcom_geni_serial_handle_tx_dma()
1046 	port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);  in setup_fifos()
1047 	port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);  in setup_fifos()
1048 	port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);  in setup_fifos()
1088 	proto = geni_se_read_proto(&port->se);  in qcom_geni_serial_port_setup()
1121 	geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,  in qcom_geni_serial_port_setup()
1123 	geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);  in qcom_geni_serial_port_setup()
1124 	geni_se_select_mode(&port->se, port->dev_data->mode);  in qcom_geni_serial_port_setup()
1232 	ver = geni_se_get_qup_hw_version(&port->se);  in qcom_geni_serial_set_termios()
1236 	clk_rate = get_clk_div_rate(port->se.clk, baud,  in qcom_geni_serial_set_termios()
1239 		dev_err(port->se.dev,  in qcom_geni_serial_set_termios()
1245 	dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n",  in qcom_geni_serial_set_termios()
1260 	port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;  in qcom_geni_serial_set_termios()
1261 	port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);  in qcom_geni_serial_set_termios()
1262 	geni_icc_set_bw(&port->se);  in qcom_geni_serial_set_termios()
1389 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se,  in qcom_geni_serial_enable_early_read()  argument
1392 	geni_se_setup_s_cmd(se, UART_START_READ, 0);  in qcom_geni_serial_enable_early_read()
1396 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,  in qcom_geni_serial_enable_early_read()  argument
1412 	struct geni_se se;  in qcom_geni_serial_earlycon_setup()  local
1419 	memset(&se, 0, sizeof(se));  in qcom_geni_serial_earlycon_setup()
1420 	se.base = uport->membase;  in qcom_geni_serial_earlycon_setup()
1421 	if (geni_se_read_proto(&se) != GENI_SE_UART)  in qcom_geni_serial_earlycon_setup()
1436 	geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,  in qcom_geni_serial_earlycon_setup()
1438 	geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);  in qcom_geni_serial_earlycon_setup()
1439 	geni_se_select_mode(&se, GENI_SE_FIFO);  in qcom_geni_serial_earlycon_setup()
1451 	qcom_geni_serial_enable_early_read(&se, dev->con);  in qcom_geni_serial_earlycon_setup()
1513 		geni_icc_enable(&port->se);  in qcom_geni_serial_pm()
1516 		geni_se_resources_on(&port->se);  in qcom_geni_serial_pm()
1519 		geni_se_resources_off(&port->se);  in qcom_geni_serial_pm()
1521 		geni_icc_disable(&port->se);  in qcom_geni_serial_pm()
1602 	port->se.dev = &pdev->dev;  in qcom_geni_serial_probe()
1603 	port->se.wrapper = dev_get_drvdata(pdev->dev.parent);  in qcom_geni_serial_probe()
1604 	port->se.clk = devm_clk_get(&pdev->dev, "se");  in qcom_geni_serial_probe()
1605 	if (IS_ERR(port->se.clk)) {  in qcom_geni_serial_probe()
1606 		ret = PTR_ERR(port->se.clk);  in qcom_geni_serial_probe()
1627 	ret = geni_icc_get(&port->se, NULL);  in qcom_geni_serial_probe()
1630 	port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;  in qcom_geni_serial_probe()
1631 	port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;  in qcom_geni_serial_probe()
1634 	ret = geni_icc_set_bw(&port->se);  in qcom_geni_serial_probe()
1722 		geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY);  in qcom_geni_serial_sys_suspend()
1723 		geni_icc_set_bw(&port->se);  in qcom_geni_serial_sys_suspend()
1737 		geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS);  in qcom_geni_serial_sys_resume()
1738 		geni_icc_set_bw(&port->se);  in qcom_geni_serial_sys_resume()
1754 		geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS);  in qcom_geni_serial_sys_hib_resume()
1755 		geni_icc_set_bw(&port->se);  in qcom_geni_serial_sys_hib_resume()