197 #define REG_GET_MASK(r, m)	(((r) & (m)) >> (ffs(m) - 1))  macro
430 	val = REG_GET_MASK(val, zone->sg->sensor_temp_mask);  in tegra_thermctl_get_temp()
1267 		state = REG_GET_MASK(r, SENSOR_CONFIG1_TEMP_ENABLE);  in regs_show()
1277 		state = REG_GET_MASK(r, SENSOR_CONFIG1_TIDDQ_EN_MASK);  in regs_show()
1279 		state = REG_GET_MASK(r, SENSOR_CONFIG1_TEN_COUNT_MASK);  in regs_show()
1281 		state = REG_GET_MASK(r, SENSOR_CONFIG1_TSAMPLE_MASK);  in regs_show()
1285 		state = REG_GET_MASK(r, SENSOR_STATUS1_TEMP_VALID_MASK);  in regs_show()
1287 		state = REG_GET_MASK(r, SENSOR_STATUS1_TEMP_MASK);  in regs_show()
1291 		state = REG_GET_MASK(r, SENSOR_STATUS0_VALID_MASK);  in regs_show()
1293 		state = REG_GET_MASK(r, SENSOR_STATUS0_CAPTURE_MASK);  in regs_show()
1297 		state = REG_GET_MASK(r, SENSOR_CONFIG0_STOP);  in regs_show()
1299 		state = REG_GET_MASK(r, SENSOR_CONFIG0_TALL_MASK);  in regs_show()
1301 		state = REG_GET_MASK(r, SENSOR_CONFIG0_TCALC_OVER);  in regs_show()
1303 		state = REG_GET_MASK(r, SENSOR_CONFIG0_OVER);  in regs_show()
1305 		state = REG_GET_MASK(r, SENSOR_CONFIG0_CPTR_OVER);  in regs_show()
1309 		state = REG_GET_MASK(r, SENSOR_CONFIG2_THERMA_MASK);  in regs_show()
1311 		state = REG_GET_MASK(r, SENSOR_CONFIG2_THERMB_MASK);  in regs_show()
1325 	state = REG_GET_MASK(r, SENSOR_TEMP1_CPU_TEMP_MASK);  in regs_show()
1327 	state = REG_GET_MASK(r, SENSOR_TEMP1_GPU_TEMP_MASK);  in regs_show()
1330 	state = REG_GET_MASK(r, SENSOR_TEMP2_PLLX_TEMP_MASK);  in regs_show()
1332 	state = REG_GET_MASK(r, SENSOR_TEMP2_MEM_TEMP_MASK);  in regs_show()
1345 			state = REG_GET_MASK(r, mask);  in regs_show()
1351 			state = REG_GET_MASK(r, mask);  in regs_show()
1357 			state = REG_GET_MASK(r, mask);  in regs_show()
1361 			state = REG_GET_MASK(r, mask);  in regs_show()
1373 			state = REG_GET_MASK(r, mask);  in regs_show()
1385 			state = REG_GET_MASK(r, mask);  in regs_show()
1411 	state = REG_GET_MASK(r, ttgs[0]->thermtrip_any_en_mask);  in regs_show()
1414 		state = REG_GET_MASK(r, ttgs[i]->thermtrip_enable_mask);  in regs_show()
1416 		state = REG_GET_MASK(r, ttgs[i]->thermtrip_threshold_mask);  in regs_show()
1427 	state = REG_GET_MASK(r, THROT_STATUS_BREACH_MASK);  in regs_show()
1429 	state = REG_GET_MASK(r, THROT_STATUS_STATE_MASK);  in regs_show()
1431 	state = REG_GET_MASK(r, THROT_STATUS_ENABLED_MASK);  in regs_show()
1436 		state = REG_GET_MASK(r, XPU_PSKIP_STATUS_ENABLED_MASK);  in regs_show()
1439 		state = REG_GET_MASK(r, XPU_PSKIP_STATUS_M_MASK);  in regs_show()
1441 		state = REG_GET_MASK(r, XPU_PSKIP_STATUS_N_MASK);  in regs_show()
1443 		state = REG_GET_MASK(r, XPU_PSKIP_STATUS_ENABLED_MASK);  in regs_show()
1514 	if (REG_GET_MASK(r, THROT_STATUS_STATE_MASK))  in throt_get_cdev_cur_state()
1926 	r = REG_GET_MASK(r, THROT_PRIORITY_LOCK_PRIORITY_MASK);  in soctherm_throttle_program()