79 	struct geni_se se;  member
108 	struct geni_se *se = &mas->se;  in spi_slv_setup()  local
110 	writel(SPI_SLAVE_EN, se->base + SE_SPI_SLAVE_EN);  in spi_slv_setup()
111 	writel(GENI_IO_MUX_0_EN, se->base + GENI_OUTPUT_CTRL);  in spi_slv_setup()
112 	writel(START_TRIGGER, se->base + SE_GENI_CFG_SEQ_START);  in spi_slv_setup()
125 	ret = geni_se_clk_freq_match(&mas->se,  in get_spi_clk_cfg()
153 	struct geni_se *se = &mas->se;  in handle_se_timeout()  local
158 		writel(0, se->base + SE_GENI_TX_WATERMARK_REG);  in handle_se_timeout()
173 	geni_se_cancel_m_cmd(se);  in handle_se_timeout()
182 	geni_se_abort_m_cmd(se);  in handle_se_timeout()
202 				writel(1, se->base + SE_DMA_TX_FSM_RST);  in handle_se_timeout()
211 				writel(1, se->base + SE_DMA_RX_FSM_RST);  in handle_se_timeout()
255 	struct geni_se *se = &mas->se;  in spi_geni_is_abort_still_pending()  local
268 	m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);  in spi_geni_is_abort_still_pending()
269 	m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN);  in spi_geni_is_abort_still_pending()
291 	struct geni_se *se = &mas->se;  in spi_geni_set_cs()  local
317 	geni_se_select_mode(se, mas->cur_xfer_mode);  in spi_geni_set_cs()
321 		geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0);  in spi_geni_set_cs()
323 		geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0);  in spi_geni_set_cs()
341 	struct geni_se *se = &mas->se;  in spi_setup_word_len()  local
352 	geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first,  in spi_setup_word_len()
355 	writel(word_len, se->base + SE_SPI_WORD_LEN);  in spi_setup_word_len()
362 	struct geni_se *se = &mas->se;  in geni_spi_set_clock_and_bw()  local
385 	writel(clk_sel, se->base + SE_GENI_CLK_SEL);  in geni_spi_set_clock_and_bw()
386 	writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);  in geni_spi_set_clock_and_bw()
389 	se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);  in geni_spi_set_clock_and_bw()
390 	ret = geni_icc_set_bw(se);  in geni_spi_set_clock_and_bw()
401 	struct geni_se *se = &mas->se;  in setup_fifo_params()  local
422 		writel(loopback_cfg, se->base + SE_SPI_LOOPBACK);  in setup_fifo_params()
423 		writel(demux_sel, se->base + SE_SPI_DEMUX_SEL);  in setup_fifo_params()
424 		writel(cpha, se->base + SE_SPI_CPHA);  in setup_fifo_params()
425 		writel(cpol, se->base + SE_SPI_CPOL);  in setup_fifo_params()
426 		writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV);  in setup_fifo_params()
651 	struct geni_se *se = &mas->se;  in spi_geni_init()  local
658 	proto = geni_se_read_proto(se);  in spi_geni_init()
670 	mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);  in spi_geni_init()
673 	mas->fifo_width_bits = geni_se_get_tx_fifo_width(se);  in spi_geni_init()
679 	geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2);  in spi_geni_init()
682 	ver = geni_se_get_qup_hw_version(se);  in spi_geni_init()
691 	fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE;  in spi_geni_init()
697 			geni_se_select_mode(se, GENI_GPI_DMA);  in spi_geni_init()
712 		geni_se_select_mode(se, GENI_SE_FIFO);  in spi_geni_init()
719 		spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);  in spi_geni_init()
721 		writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);  in spi_geni_init()
745 	struct geni_se *se = &mas->se;  in geni_spi_handle_tx()  local
753 		writel(0, se->base + SE_GENI_TX_WATERMARK_REG);  in geni_spi_handle_tx()
771 		iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1);  in geni_spi_handle_tx()
775 		writel(0, se->base + SE_GENI_TX_WATERMARK_REG);  in geni_spi_handle_tx()
783 	struct geni_se *se = &mas->se;  in geni_spi_handle_rx()  local
791 	rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS);  in geni_spi_handle_rx()
803 			readl(se->base + SE_GENI_RX_FIFOn);  in geni_spi_handle_rx()
818 		ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1);  in geni_spi_handle_rx()
831 	struct geni_se *se = &mas->se;  in setup_se_xfer()  local
868 		writel(len, se->base + SE_SPI_TX_TRANS_LEN);  in setup_se_xfer()
873 		writel(len, se->base + SE_SPI_RX_TRANS_LEN);  in setup_se_xfer()
891 	geni_se_select_mode(se, mas->cur_xfer_mode);  in setup_se_xfer()
898 	geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION);  in setup_se_xfer()
902 			geni_se_rx_init_dma(se, sg_dma_address(xfer->rx_sg.sgl),  in setup_se_xfer()
905 			geni_se_tx_init_dma(se, sg_dma_address(xfer->tx_sg.sgl),  in setup_se_xfer()
909 			writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG);  in setup_se_xfer()
944 	struct geni_se *se = &mas->se;  in geni_spi_isr()  local
947 	m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);  in geni_spi_isr()
983 					writel(0, se->base + SE_GENI_TX_WATERMARK_REG);  in geni_spi_isr()
996 		u32 dma_tx_status = readl_relaxed(se->base + SE_DMA_TX_IRQ_STAT);  in geni_spi_isr()
997 		u32 dma_rx_status = readl_relaxed(se->base + SE_DMA_RX_IRQ_STAT);  in geni_spi_isr()
1000 			writel(dma_tx_status, se->base + SE_DMA_TX_IRQ_CLR);  in geni_spi_isr()
1002 			writel(dma_rx_status, se->base + SE_DMA_RX_IRQ_CLR);  in geni_spi_isr()
1035 	writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR);  in geni_spi_isr()
1075 	mas->se.dev = dev;  in spi_geni_probe()
1076 	mas->se.wrapper = dev_get_drvdata(dev->parent);  in spi_geni_probe()
1077 	mas->se.base = base;  in spi_geni_probe()
1078 	mas->se.clk = clk;  in spi_geni_probe()
1118 	ret = geni_icc_get(&mas->se, NULL);  in spi_geni_probe()
1122 	mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ);  in spi_geni_probe()
1123 	mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;  in spi_geni_probe()
1125 	ret = geni_icc_set_bw(&mas->se);  in spi_geni_probe()
1188 	ret = geni_se_resources_off(&mas->se);  in spi_geni_runtime_suspend()
1192 	return geni_icc_disable(&mas->se);  in spi_geni_runtime_suspend()
1201 	ret = geni_icc_enable(&mas->se);  in spi_geni_runtime_resume()
1205 	ret = geni_se_resources_on(&mas->se);  in spi_geni_runtime_resume()