19 static unsigned int sh_clk_read(struct clk *clk)  in sh_clk_read()  argument
21 	if (clk->flags & CLK_ENABLE_REG_8BIT)  in sh_clk_read()
22 		return ioread8(clk->mapped_reg);  in sh_clk_read()
23 	else if (clk->flags & CLK_ENABLE_REG_16BIT)  in sh_clk_read()
24 		return ioread16(clk->mapped_reg);  in sh_clk_read()
26 	return ioread32(clk->mapped_reg);  in sh_clk_read()
29 static void sh_clk_write(int value, struct clk *clk)  in sh_clk_write()  argument
31 	if (clk->flags & CLK_ENABLE_REG_8BIT)  in sh_clk_write()
32 		iowrite8(value, clk->mapped_reg);  in sh_clk_write()
33 	else if (clk->flags & CLK_ENABLE_REG_16BIT)  in sh_clk_write()
34 		iowrite16(value, clk->mapped_reg);  in sh_clk_write()
36 		iowrite32(value, clk->mapped_reg);  in sh_clk_write()
39 static int sh_clk_mstp_enable(struct clk *clk)  in sh_clk_mstp_enable()  argument
41 	sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk);  in sh_clk_mstp_enable()
42 	if (clk->status_reg) {  in sh_clk_mstp_enable()
45 		void __iomem *mapped_status = (phys_addr_t)clk->status_reg -  in sh_clk_mstp_enable()
46 			(phys_addr_t)clk->enable_reg + clk->mapped_reg;  in sh_clk_mstp_enable()
48 		if (clk->flags & CLK_ENABLE_REG_8BIT)  in sh_clk_mstp_enable()
50 		else if (clk->flags & CLK_ENABLE_REG_16BIT)  in sh_clk_mstp_enable()
56 		     (read(mapped_status) & (1 << clk->enable_bit)) && i;  in sh_clk_mstp_enable()
61 			       clk->enable_reg, clk->enable_bit);  in sh_clk_mstp_enable()
68 static void sh_clk_mstp_disable(struct clk *clk)  in sh_clk_mstp_disable()  argument
70 	sh_clk_write(sh_clk_read(clk) | (1 << clk->enable_bit), clk);  in sh_clk_mstp_disable()
79 int __init sh_clk_mstp_register(struct clk *clks, int nr)  in sh_clk_mstp_register()
81 	struct clk *clkp;  in sh_clk_mstp_register()
97 static inline struct clk_div_table *clk_to_div_table(struct clk *clk)  in clk_to_div_table()  argument
99 	return clk->priv;  in clk_to_div_table()
102 static inline struct clk_div_mult_table *clk_to_div_mult_table(struct clk *clk)  in clk_to_div_mult_table()  argument
104 	return clk_to_div_table(clk)->div_mult_table;  in clk_to_div_mult_table()
110 static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate)  in sh_clk_div_round_rate()  argument
112 	return clk_rate_table_round(clk, clk->freq_table, rate);  in sh_clk_div_round_rate()
115 static unsigned long sh_clk_div_recalc(struct clk *clk)  in sh_clk_div_recalc()  argument
117 	struct clk_div_mult_table *table = clk_to_div_mult_table(clk);  in sh_clk_div_recalc()
120 	clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,  in sh_clk_div_recalc()
121 			     table, clk->arch_flags ? &clk->arch_flags : NULL);  in sh_clk_div_recalc()
123 	idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask;  in sh_clk_div_recalc()
125 	return clk->freq_table[idx].frequency;  in sh_clk_div_recalc()
128 static int sh_clk_div_set_rate(struct clk *clk, unsigned long rate)  in sh_clk_div_set_rate()  argument
130 	struct clk_div_table *dt = clk_to_div_table(clk);  in sh_clk_div_set_rate()
134 	idx = clk_rate_table_find(clk, clk->freq_table, rate);  in sh_clk_div_set_rate()
138 	value = sh_clk_read(clk);  in sh_clk_div_set_rate()
139 	value &= ~(clk->div_mask << clk->enable_bit);  in sh_clk_div_set_rate()
140 	value |= (idx << clk->enable_bit);  in sh_clk_div_set_rate()
141 	sh_clk_write(value, clk);  in sh_clk_div_set_rate()
145 		dt->kick(clk);  in sh_clk_div_set_rate()
150 static int sh_clk_div_enable(struct clk *clk)  in sh_clk_div_enable()  argument
152 	if (clk->div_mask == SH_CLK_DIV6_MSK) {  in sh_clk_div_enable()
153 		int ret = sh_clk_div_set_rate(clk, clk->rate);  in sh_clk_div_enable()
158 	sh_clk_write(sh_clk_read(clk) & ~CPG_CKSTP_BIT, clk);  in sh_clk_div_enable()
162 static void sh_clk_div_disable(struct clk *clk)  in sh_clk_div_disable()  argument
166 	val = sh_clk_read(clk);  in sh_clk_div_disable()
174 	if (clk->flags & CLK_MASK_DIV_ON_DISABLE)  in sh_clk_div_disable()
175 		val |= clk->div_mask;  in sh_clk_div_disable()
177 	sh_clk_write(val, clk);  in sh_clk_div_disable()
194 static int __init sh_clk_init_parent(struct clk *clk)  in sh_clk_init_parent()  argument
198 	if (clk->parent)  in sh_clk_init_parent()
201 	if (!clk->parent_table || !clk->parent_num)  in sh_clk_init_parent()
204 	if (!clk->src_width) {  in sh_clk_init_parent()
209 	val  = (sh_clk_read(clk) >> clk->src_shift);  in sh_clk_init_parent()
210 	val &= (1 << clk->src_width) - 1;  in sh_clk_init_parent()
212 	if (val >= clk->parent_num) {  in sh_clk_init_parent()
217 	clk_reparent(clk, clk->parent_table[val]);  in sh_clk_init_parent()
218 	if (!clk->parent) {  in sh_clk_init_parent()
226 static int __init sh_clk_div_register_ops(struct clk *clks, int nr,  in sh_clk_div_register_ops()
229 	struct clk *clkp;  in sh_clk_div_register_ops()
279 static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent)  in sh_clk_div6_set_parent()  argument
281 	struct clk_div_mult_table *table = clk_to_div_mult_table(clk);  in sh_clk_div6_set_parent()
285 	if (!clk->parent_table || !clk->parent_num)  in sh_clk_div6_set_parent()
289 	for (i = 0; i < clk->parent_num; i++)  in sh_clk_div6_set_parent()
290 		if (clk->parent_table[i] == parent)  in sh_clk_div6_set_parent()
293 	if (i == clk->parent_num)  in sh_clk_div6_set_parent()
296 	ret = clk_reparent(clk, parent);  in sh_clk_div6_set_parent()
300 	value = sh_clk_read(clk) &  in sh_clk_div6_set_parent()
301 		~(((1 << clk->src_width) - 1) << clk->src_shift);  in sh_clk_div6_set_parent()
303 	sh_clk_write(value | (i << clk->src_shift), clk);  in sh_clk_div6_set_parent()
306 	clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,  in sh_clk_div6_set_parent()
321 int __init sh_clk_div6_register(struct clk *clks, int nr)  in sh_clk_div6_register()
327 int __init sh_clk_div6_reparent_register(struct clk *clks, int nr)  in sh_clk_div6_reparent_register()
336 static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)  in sh_clk_div4_set_parent()  argument
338 	struct clk_div_mult_table *table = clk_to_div_mult_table(clk);  in sh_clk_div4_set_parent()
348 		value = sh_clk_read(clk) & ~(1 << 7);  in sh_clk_div4_set_parent()
350 		value = sh_clk_read(clk) | (1 << 7);  in sh_clk_div4_set_parent()
352 	ret = clk_reparent(clk, parent);  in sh_clk_div4_set_parent()
356 	sh_clk_write(value, clk);  in sh_clk_div4_set_parent()
359 	clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,  in sh_clk_div4_set_parent()
360 			     table, &clk->arch_flags);  in sh_clk_div4_set_parent()
374 int __init sh_clk_div4_register(struct clk *clks, int nr,  in sh_clk_div4_register()
380 int __init sh_clk_div4_enable_register(struct clk *clks, int nr,  in sh_clk_div4_enable_register()
387 int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,  in sh_clk_div4_reparent_register()
395 static unsigned long fsidiv_recalc(struct clk *clk)  in fsidiv_recalc()  argument
399 	value = __raw_readl(clk->mapping->base);  in fsidiv_recalc()
403 		return clk->parent->rate;  in fsidiv_recalc()
405 	return clk->parent->rate / value;  in fsidiv_recalc()
408 static long fsidiv_round_rate(struct clk *clk, unsigned long rate)  in fsidiv_round_rate()  argument
410 	return clk_rate_div_range_round(clk, 1, 0xffff, rate);  in fsidiv_round_rate()
413 static void fsidiv_disable(struct clk *clk)  in fsidiv_disable()  argument
415 	__raw_writel(0, clk->mapping->base);  in fsidiv_disable()
418 static int fsidiv_enable(struct clk *clk)  in fsidiv_enable()  argument
422 	value  = __raw_readl(clk->mapping->base) >> 16;  in fsidiv_enable()
426 	__raw_writel((value << 16) | 0x3, clk->mapping->base);  in fsidiv_enable()
431 static int fsidiv_set_rate(struct clk *clk, unsigned long rate)  in fsidiv_set_rate()  argument
435 	idx = (clk->parent->rate / rate) & 0xffff;  in fsidiv_set_rate()
437 		__raw_writel(0, clk->mapping->base);  in fsidiv_set_rate()
439 		__raw_writel(idx << 16, clk->mapping->base);  in fsidiv_set_rate()
452 int __init sh_clk_fsidiv_register(struct clk *clks, int nr)  in sh_clk_fsidiv_register()