Lines Matching refs:pd
49 struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd); in meson_gx_pwrc_vpu_power_off() local
52 regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, in meson_gx_pwrc_vpu_power_off()
58 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0, in meson_gx_pwrc_vpu_power_off()
63 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1, in meson_gx_pwrc_vpu_power_off()
68 regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0, in meson_gx_pwrc_vpu_power_off()
74 regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, in meson_gx_pwrc_vpu_power_off()
79 clk_disable_unprepare(pd->vpu_clk); in meson_gx_pwrc_vpu_power_off()
80 clk_disable_unprepare(pd->vapb_clk); in meson_gx_pwrc_vpu_power_off()
87 struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd); in meson_g12a_pwrc_vpu_power_off() local
90 regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, in meson_g12a_pwrc_vpu_power_off()
96 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0, in meson_g12a_pwrc_vpu_power_off()
101 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1, in meson_g12a_pwrc_vpu_power_off()
106 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG2, in meson_g12a_pwrc_vpu_power_off()
111 regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0, in meson_g12a_pwrc_vpu_power_off()
117 regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, in meson_g12a_pwrc_vpu_power_off()
122 clk_disable_unprepare(pd->vpu_clk); in meson_g12a_pwrc_vpu_power_off()
123 clk_disable_unprepare(pd->vapb_clk); in meson_g12a_pwrc_vpu_power_off()
128 static int meson_gx_pwrc_vpu_setup_clk(struct meson_gx_pwrc_vpu *pd) in meson_gx_pwrc_vpu_setup_clk() argument
132 ret = clk_prepare_enable(pd->vpu_clk); in meson_gx_pwrc_vpu_setup_clk()
136 ret = clk_prepare_enable(pd->vapb_clk); in meson_gx_pwrc_vpu_setup_clk()
138 clk_disable_unprepare(pd->vpu_clk); in meson_gx_pwrc_vpu_setup_clk()
145 struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd); in meson_gx_pwrc_vpu_power_on() local
149 regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, in meson_gx_pwrc_vpu_power_on()
155 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0, in meson_gx_pwrc_vpu_power_on()
161 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1, in meson_gx_pwrc_vpu_power_on()
167 regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0, in meson_gx_pwrc_vpu_power_on()
173 ret = reset_control_assert(pd->rstc); in meson_gx_pwrc_vpu_power_on()
177 regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, in meson_gx_pwrc_vpu_power_on()
180 ret = reset_control_deassert(pd->rstc); in meson_gx_pwrc_vpu_power_on()
184 ret = meson_gx_pwrc_vpu_setup_clk(pd); in meson_gx_pwrc_vpu_power_on()
193 struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd); in meson_g12a_pwrc_vpu_power_on() local
197 regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, in meson_g12a_pwrc_vpu_power_on()
203 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0, in meson_g12a_pwrc_vpu_power_on()
209 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1, in meson_g12a_pwrc_vpu_power_on()
215 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG2, in meson_g12a_pwrc_vpu_power_on()
221 regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0, in meson_g12a_pwrc_vpu_power_on()
227 ret = reset_control_assert(pd->rstc); in meson_g12a_pwrc_vpu_power_on()
231 regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, in meson_g12a_pwrc_vpu_power_on()
234 ret = reset_control_deassert(pd->rstc); in meson_g12a_pwrc_vpu_power_on()
238 ret = meson_gx_pwrc_vpu_setup_clk(pd); in meson_g12a_pwrc_vpu_power_on()
245 static bool meson_gx_pwrc_vpu_get_power(struct meson_gx_pwrc_vpu *pd) in meson_gx_pwrc_vpu_get_power() argument
249 regmap_read(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, ®); in meson_gx_pwrc_vpu_get_power()