235 	struct regmap_field	*fields[MAX_FIELDS];  member
251 	ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_ENABLE_STATE);  in serdes_am654_enable_pll()
255 	return regmap_field_read_poll_timeout(phy->fields[PLL_OK], val, val,  in serdes_am654_enable_pll()
264 	ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_DISABLE_STATE);  in serdes_am654_disable_pll()
274 	ret |= regmap_field_write(phy->fields[TX0_ENABLE], TX0_ENABLE_STATE);  in serdes_am654_enable_txrx()
277 	ret |= regmap_field_write(phy->fields[RX0_ENABLE], RX0_ENABLE_STATE);  in serdes_am654_enable_txrx()
290 	ret |= regmap_field_write(phy->fields[TX0_ENABLE], TX0_DISABLE_STATE);  in serdes_am654_disable_txrx()
293 	ret |= regmap_field_write(phy->fields[RX0_ENABLE], RX0_DISABLE_STATE);  in serdes_am654_disable_txrx()
320 	return regmap_field_read_poll_timeout(phy->fields[CMU_OK_I_0], val,  in serdes_am654_power_on()
421 	ret |= regmap_field_write(phy->fields[CMU_PLL_CTRL], 0x2);  in serdes_am654_pcie_init()
422 	ret |= regmap_field_write(phy->fields[AHB_PMA_CM_VCO_VBIAS_VREG], 0x98);  in serdes_am654_pcie_init()
423 	ret |= regmap_field_write(phy->fields[AHB_PMA_CM_VCO_BIAS_VREG], 0x98);  in serdes_am654_pcie_init()
424 	ret |= regmap_field_write(phy->fields[AHB_PMA_CM_SR], 0x45);  in serdes_am654_pcie_init()
425 	ret |= regmap_field_write(phy->fields[AHB_SSC_GEN_Z_O_20_13], 0xe);  in serdes_am654_pcie_init()
426 	ret |= regmap_field_write(phy->fields[LANE_PLL_CTRL_RXEQ_RXIDLE], 0x5);  in serdes_am654_pcie_init()
427 	ret |= regmap_field_write(phy->fields[AHB_PMA_LN_AGC_THSEL_VREGH], 0x83);  in serdes_am654_pcie_init()
428 	ret |= regmap_field_write(phy->fields[AHB_PMA_LN_GEN3_AGC_SD_THSEL], 0x83);  in serdes_am654_pcie_init()
429 	ret |= regmap_field_write(phy->fields[AHB_PMA_LN_RX_SELR_GEN3],	0x81);  in serdes_am654_pcie_init()
430 	ret |= regmap_field_write(phy->fields[AHB_PMA_LN_TX_DRV], 0x3b);  in serdes_am654_pcie_init()
431 	ret |= regmap_field_write(phy->fields[P2S_RBUF_PTR_DIFF], 0x3);  in serdes_am654_pcie_init()
432 	ret |= regmap_field_write(phy->fields[CONFIG_VERSION], VERSION_VAL);  in serdes_am654_pcie_init()
433 	ret |= regmap_field_write(phy->fields[COMRXEQ_MS_INIT_CTRL_7_0], 0xf);  in serdes_am654_pcie_init()
434 	ret |= regmap_field_write(phy->fields[COMRXEQ_HS_INIT_CAL_7_0], 0x4f);  in serdes_am654_pcie_init()
435 	ret |= regmap_field_write(phy->fields[COMRXEQ_MS_RECAL_CTRL_7_0], 0xf);  in serdes_am654_pcie_init()
436 	ret |= regmap_field_write(phy->fields[COMRXEQ_HS_RECAL_CTRL_7_0], 0x4f);  in serdes_am654_pcie_init()
437 	ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_ATT_CONFIG], 0x7);  in serdes_am654_pcie_init()
438 	ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_EBSTADAPT_WIN_LEN], 0x7f);  in serdes_am654_pcie_init()
439 	ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_3_4], 0xf);  in serdes_am654_pcie_init()
440 	ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_14_15_16], 0x9a);  in serdes_am654_pcie_init()
441 	ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_DLEV_ERR_THRESH], 0x32);  in serdes_am654_pcie_init()
442 	ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_25], 0x80);  in serdes_am654_pcie_init()
443 	ret |= regmap_field_write(phy->fields[CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE2_O], 0xf);  in serdes_am654_pcie_init()
444 	ret |= regmap_field_write(phy->fields[COMRXEQ_HS_RCHANGE_CTRL_7_0], 0x4f);  in serdes_am654_pcie_init()
445 	ret |= regmap_field_write(phy->fields[CMU_MASTER_CDN], 0x1);  in serdes_am654_pcie_init()
446 	ret |= regmap_field_write(phy->fields[L1_MASTER_CDN], 0x2);  in serdes_am654_pcie_init()
476 	ret |= regmap_field_write(phy->fields[POR_EN], 0x1);  in serdes_am654_reset()
480 	ret |= regmap_field_write(phy->fields[POR_EN], 0x0);  in serdes_am654_reset()
741 		am654_phy->fields[i] = devm_regmap_field_alloc(dev,  in serdes_am654_regfield_init()
744 		if (IS_ERR(am654_phy->fields[i])) {  in serdes_am654_regfield_init()
746 			return PTR_ERR(am654_phy->fields[i]);  in serdes_am654_regfield_init()