Lines Matching refs:base
53 void __iomem *base = hdmi_phy->regs; in mtk_hdmi_pll_prepare() local
55 mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN); in mtk_hdmi_pll_prepare()
56 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); in mtk_hdmi_pll_prepare()
57 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); in mtk_hdmi_pll_prepare()
58 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); in mtk_hdmi_pll_prepare()
60 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN); in mtk_hdmi_pll_prepare()
61 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); in mtk_hdmi_pll_prepare()
62 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); in mtk_hdmi_pll_prepare()
64 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); in mtk_hdmi_pll_prepare()
65 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK); in mtk_hdmi_pll_prepare()
66 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK); in mtk_hdmi_pll_prepare()
67 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK); in mtk_hdmi_pll_prepare()
75 void __iomem *base = hdmi_phy->regs; in mtk_hdmi_pll_unprepare() local
77 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK); in mtk_hdmi_pll_unprepare()
78 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK); in mtk_hdmi_pll_unprepare()
79 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK); in mtk_hdmi_pll_unprepare()
80 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); in mtk_hdmi_pll_unprepare()
82 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); in mtk_hdmi_pll_unprepare()
83 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); in mtk_hdmi_pll_unprepare()
84 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN); in mtk_hdmi_pll_unprepare()
86 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); in mtk_hdmi_pll_unprepare()
87 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); in mtk_hdmi_pll_unprepare()
88 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); in mtk_hdmi_pll_unprepare()
89 mtk_phy_clear_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN); in mtk_hdmi_pll_unprepare()
103 void __iomem *base = hdmi_phy->regs; in mtk_hdmi_pll_set_rate() local
113 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_PREDIV_MASK); in mtk_hdmi_pll_set_rate()
114 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); in mtk_hdmi_pll_set_rate()
115 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_POSDIV); in mtk_hdmi_pll_set_rate()
116 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IC_MASK, 0x1); in mtk_hdmi_pll_set_rate()
117 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IR_MASK, 0x1); in mtk_hdmi_pll_set_rate()
118 mtk_phy_update_field(base + HDMI_CON2, RG_HDMITX_TX_POSDIV_MASK, pos_div); in mtk_hdmi_pll_set_rate()
119 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKSEL_MASK, 1); in mtk_hdmi_pll_set_rate()
120 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKDIV_MASK, 19); in mtk_hdmi_pll_set_rate()
121 mtk_phy_update_field(base + HDMI_CON7, RG_HTPLL_DIVEN_MASK, 0x2); in mtk_hdmi_pll_set_rate()
122 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BP_MASK, 0xc); in mtk_hdmi_pll_set_rate()
123 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BC_MASK, 0x2); in mtk_hdmi_pll_set_rate()
124 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BR_MASK, 0x1); in mtk_hdmi_pll_set_rate()
126 mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PRED_IMP); in mtk_hdmi_pll_set_rate()
127 mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PRED_IBIAS_MASK, 0x3); in mtk_hdmi_pll_set_rate()
128 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_IMP_MASK); in mtk_hdmi_pll_set_rate()
129 mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_DRV_IMP_MASK, 0x28); in mtk_hdmi_pll_set_rate()
130 mtk_phy_update_field(base + HDMI_CON4, RG_HDMITX_RESERVE_MASK, 0x28); in mtk_hdmi_pll_set_rate()
131 mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_DRV_IBIAS_MASK, 0xa); in mtk_hdmi_pll_set_rate()
179 void __iomem *base = hdmi_phy->regs; in mtk_hdmi_phy_enable_tmds() local
181 mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN); in mtk_hdmi_phy_enable_tmds()
182 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); in mtk_hdmi_phy_enable_tmds()
183 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); in mtk_hdmi_phy_enable_tmds()
184 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); in mtk_hdmi_phy_enable_tmds()
186 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN); in mtk_hdmi_phy_enable_tmds()
187 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); in mtk_hdmi_phy_enable_tmds()
188 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); in mtk_hdmi_phy_enable_tmds()
190 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); in mtk_hdmi_phy_enable_tmds()
191 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK); in mtk_hdmi_phy_enable_tmds()
192 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK); in mtk_hdmi_phy_enable_tmds()
193 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK); in mtk_hdmi_phy_enable_tmds()
199 void __iomem *base = hdmi_phy->regs; in mtk_hdmi_phy_disable_tmds() local
201 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK); in mtk_hdmi_phy_disable_tmds()
202 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK); in mtk_hdmi_phy_disable_tmds()
203 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK); in mtk_hdmi_phy_disable_tmds()
204 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); in mtk_hdmi_phy_disable_tmds()
206 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); in mtk_hdmi_phy_disable_tmds()
207 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); in mtk_hdmi_phy_disable_tmds()
208 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN); in mtk_hdmi_phy_disable_tmds()
210 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); in mtk_hdmi_phy_disable_tmds()
211 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); in mtk_hdmi_phy_disable_tmds()
212 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); in mtk_hdmi_phy_disable_tmds()
213 mtk_phy_clear_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN); in mtk_hdmi_phy_disable_tmds()