Lines Matching refs:pdev
77 static bool dpc_completed(struct pci_dev *pdev) in dpc_completed() argument
81 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_STATUS, &status); in dpc_completed()
85 if (test_bit(PCI_DPC_RECOVERING, &pdev->priv_flags)) in dpc_completed()
99 bool pci_dpc_recovered(struct pci_dev *pdev) in pci_dpc_recovered() argument
103 if (!pdev->dpc_cap) in pci_dpc_recovered()
110 host = pci_find_host_bridge(pdev->bus); in pci_dpc_recovered()
119 wait_event_timeout(dpc_completed_waitqueue, dpc_completed(pdev), in pci_dpc_recovered()
122 return test_and_clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags); in pci_dpc_recovered()
126 static int dpc_wait_rp_inactive(struct pci_dev *pdev) in dpc_wait_rp_inactive() argument
129 u16 cap = pdev->dpc_cap, status; in dpc_wait_rp_inactive()
131 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); in dpc_wait_rp_inactive()
135 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); in dpc_wait_rp_inactive()
138 pci_warn(pdev, "root port still busy\n"); in dpc_wait_rp_inactive()
144 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev) in dpc_reset_link() argument
149 set_bit(PCI_DPC_RECOVERING, &pdev->priv_flags); in dpc_reset_link()
155 cap = pdev->dpc_cap; in dpc_reset_link()
161 if (!pcie_wait_for_link(pdev, false)) in dpc_reset_link()
162 pci_info(pdev, "Data Link Layer Link Active not cleared in 1000 msec\n"); in dpc_reset_link()
164 if (pdev->dpc_rp_extensions && dpc_wait_rp_inactive(pdev)) { in dpc_reset_link()
165 clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags); in dpc_reset_link()
170 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS, in dpc_reset_link()
173 if (pci_bridge_wait_for_secondary_bus(pdev, "DPC")) { in dpc_reset_link()
174 clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags); in dpc_reset_link()
177 set_bit(PCI_DPC_RECOVERED, &pdev->priv_flags); in dpc_reset_link()
181 clear_bit(PCI_DPC_RECOVERING, &pdev->priv_flags); in dpc_reset_link()
186 static void dpc_process_rp_pio_error(struct pci_dev *pdev) in dpc_process_rp_pio_error() argument
188 u16 cap = pdev->dpc_cap, dpc_status, first_error; in dpc_process_rp_pio_error()
192 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status); in dpc_process_rp_pio_error()
193 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask); in dpc_process_rp_pio_error()
194 pci_err(pdev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n", in dpc_process_rp_pio_error()
197 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev); in dpc_process_rp_pio_error()
198 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr); in dpc_process_rp_pio_error()
199 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc); in dpc_process_rp_pio_error()
200 pci_err(pdev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n", in dpc_process_rp_pio_error()
204 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status); in dpc_process_rp_pio_error()
209 pci_err(pdev, "[%2d] %s%s\n", i, rp_pio_error_string[i], in dpc_process_rp_pio_error()
213 if (pdev->dpc_rp_log_size < 4) in dpc_process_rp_pio_error()
215 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG, in dpc_process_rp_pio_error()
217 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4, in dpc_process_rp_pio_error()
219 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8, in dpc_process_rp_pio_error()
221 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12, in dpc_process_rp_pio_error()
223 pci_err(pdev, "TLP Header: %#010x %#010x %#010x %#010x\n", in dpc_process_rp_pio_error()
226 if (pdev->dpc_rp_log_size < 5) in dpc_process_rp_pio_error()
228 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log); in dpc_process_rp_pio_error()
229 pci_err(pdev, "RP PIO ImpSpec Log %#010x\n", log); in dpc_process_rp_pio_error()
231 for (i = 0; i < pdev->dpc_rp_log_size - 5; i++) { in dpc_process_rp_pio_error()
232 pci_read_config_dword(pdev, in dpc_process_rp_pio_error()
234 pci_err(pdev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix); in dpc_process_rp_pio_error()
237 pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, status); in dpc_process_rp_pio_error()
262 void dpc_process_error(struct pci_dev *pdev) in dpc_process_error() argument
264 u16 cap = pdev->dpc_cap, status, source, reason, ext_reason; in dpc_process_error()
267 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); in dpc_process_error()
268 pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID, &source); in dpc_process_error()
270 pci_info(pdev, "containment event, status:%#06x source:%#06x\n", in dpc_process_error()
275 pci_warn(pdev, "%s detected\n", in dpc_process_error()
284 if (pdev->dpc_rp_extensions && reason == 3 && ext_reason == 0) in dpc_process_error()
285 dpc_process_rp_pio_error(pdev); in dpc_process_error()
287 dpc_get_aer_uncorrect_severity(pdev, &info) && in dpc_process_error()
288 aer_get_device_error_info(pdev, &info)) { in dpc_process_error()
289 aer_print_error(pdev, &info); in dpc_process_error()
290 pci_aer_clear_nonfatal_status(pdev); in dpc_process_error()
291 pci_aer_clear_fatal_status(pdev); in dpc_process_error()
297 struct pci_dev *pdev = context; in dpc_handler() local
299 dpc_process_error(pdev); in dpc_handler()
302 pcie_do_recovery(pdev, pci_channel_io_frozen, dpc_reset_link); in dpc_handler()
309 struct pci_dev *pdev = context; in dpc_irq() local
310 u16 cap = pdev->dpc_cap, status; in dpc_irq()
312 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); in dpc_irq()
317 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS, in dpc_irq()
324 void pci_dpc_init(struct pci_dev *pdev) in pci_dpc_init() argument
328 pdev->dpc_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC); in pci_dpc_init()
329 if (!pdev->dpc_cap) in pci_dpc_init()
332 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap); in pci_dpc_init()
336 pdev->dpc_rp_extensions = true; in pci_dpc_init()
339 if (!pdev->dpc_rp_log_size) { in pci_dpc_init()
340 pdev->dpc_rp_log_size = in pci_dpc_init()
342 if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) { in pci_dpc_init()
343 pci_err(pdev, "RP PIO log size %u is invalid\n", in pci_dpc_init()
344 pdev->dpc_rp_log_size); in pci_dpc_init()
345 pdev->dpc_rp_log_size = 0; in pci_dpc_init()
353 struct pci_dev *pdev = dev->port; in dpc_probe() local
358 if (!pcie_aer_is_native(pdev) && !pcie_ports_dpc_native) in dpc_probe()
363 "pcie-dpc", pdev); in dpc_probe()
365 pci_warn(pdev, "request IRQ%d failed: %d\n", dev->irq, in dpc_probe()
370 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap); in dpc_probe()
371 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl); in dpc_probe()
374 pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl); in dpc_probe()
375 pci_info(pdev, "enabled with IRQ %d\n", dev->irq); in dpc_probe()
377 …pci_info(pdev, "error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP … in dpc_probe()
380 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), pdev->dpc_rp_log_size, in dpc_probe()
383 pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_DPC, sizeof(u16)); in dpc_probe()
389 struct pci_dev *pdev = dev->port; in dpc_remove() local
392 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl); in dpc_remove()
394 pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl); in dpc_remove()