145 	int aer = dev->aer_cap;  in enable_ecrc_checking()  local
148 	if (!aer)  in enable_ecrc_checking()
151 	pci_read_config_dword(dev, aer + PCI_ERR_CAP, &reg32);  in enable_ecrc_checking()
156 	pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);  in enable_ecrc_checking()
169 	int aer = dev->aer_cap;  in disable_ecrc_checking()  local
172 	if (!aer)  in disable_ecrc_checking()
175 	pci_read_config_dword(dev, aer + PCI_ERR_CAP, &reg32);  in disable_ecrc_checking()
177 	pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);  in disable_ecrc_checking()
248 	int aer = dev->aer_cap;  in pci_aer_clear_nonfatal_status()  local
255 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in pci_aer_clear_nonfatal_status()
256 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);  in pci_aer_clear_nonfatal_status()
259 		pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);  in pci_aer_clear_nonfatal_status()
267 	int aer = dev->aer_cap;  in pci_aer_clear_fatal_status()  local
274 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in pci_aer_clear_fatal_status()
275 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);  in pci_aer_clear_fatal_status()
278 		pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);  in pci_aer_clear_fatal_status()
292 	int aer = dev->aer_cap;  in pci_aer_raw_clear_status()  local
296 	if (!aer)  in pci_aer_raw_clear_status()
302 		pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &status);  in pci_aer_raw_clear_status()
303 		pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, status);  in pci_aer_raw_clear_status()
306 	pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);  in pci_aer_raw_clear_status()
307 	pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, status);  in pci_aer_raw_clear_status()
309 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in pci_aer_raw_clear_status()
310 	pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);  in pci_aer_raw_clear_status()
325 	int aer = dev->aer_cap;  in pci_save_aer_state()  local
329 	if (!aer)  in pci_save_aer_state()
337 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++);  in pci_save_aer_state()
338 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++);  in pci_save_aer_state()
339 	pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++);  in pci_save_aer_state()
340 	pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++);  in pci_save_aer_state()
342 		pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++);  in pci_save_aer_state()
347 	int aer = dev->aer_cap;  in pci_restore_aer_state()  local
351 	if (!aer)  in pci_restore_aer_state()
359 	pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, *cap++);  in pci_restore_aer_state()
360 	pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, *cap++);  in pci_restore_aer_state()
361 	pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, *cap++);  in pci_restore_aer_state()
362 	pci_write_config_dword(dev, aer + PCI_ERR_CAP, *cap++);  in pci_restore_aer_state()
364 		pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, *cap++);  in pci_restore_aer_state()
765 		    struct aer_capability_regs *aer)  in cper_print_aer()  argument
772 		status = aer->cor_status;  in cper_print_aer()
773 		mask = aer->cor_mask;  in cper_print_aer()
775 		status = aer->uncor_status;  in cper_print_aer()
776 		mask = aer->uncor_mask;  in cper_print_aer()
787 	info.first_error = PCI_ERR_CAP_FEP(aer->cap_control);  in cper_print_aer()
796 			aer->uncor_severity);  in cper_print_aer()
799 		__print_tlp_header(dev, &aer->header_log);  in cper_print_aer()
802 			aer_severity, tlp_header_valid, &aer->header_log);  in cper_print_aer()
828 	int aer = dev->aer_cap;  in is_error_source()  local
863 	if (!aer)  in is_error_source()
868 		pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);  in is_error_source()
869 		pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);  in is_error_source()
871 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in is_error_source()
872 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);  in is_error_source()
951 	int aer = dev->aer_cap;  in handle_error_source()  local
958 		if (aer)  in handle_error_source()
959 			pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS,  in handle_error_source()
1066 	int aer = dev->aer_cap;  in aer_get_device_error_info()  local
1074 	if (!aer)  in aer_get_device_error_info()
1078 		pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS,  in aer_get_device_error_info()
1080 		pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK,  in aer_get_device_error_info()
1090 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS,  in aer_get_device_error_info()
1092 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK,  in aer_get_device_error_info()
1098 		pci_read_config_dword(dev, aer + PCI_ERR_CAP, &temp);  in aer_get_device_error_info()
1104 				aer + PCI_ERR_HEADER_LOG, &info->tlp.dw0);  in aer_get_device_error_info()
1106 				aer + PCI_ERR_HEADER_LOG + 4, &info->tlp.dw1);  in aer_get_device_error_info()
1108 				aer + PCI_ERR_HEADER_LOG + 8, &info->tlp.dw2);  in aer_get_device_error_info()
1110 				aer + PCI_ERR_HEADER_LOG + 12, &info->tlp.dw3);  in aer_get_device_error_info()
1216 	int aer = rp->aer_cap;  in aer_irq()  local
1219 	pci_read_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, &e_src.status);  in aer_irq()
1223 	pci_read_config_dword(rp, aer + PCI_ERR_ROOT_ERR_SRC, &e_src.id);  in aer_irq()
1224 	pci_write_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, e_src.status);  in aer_irq()
1241 	int aer = pdev->aer_cap;  in aer_enable_rootport()  local
1254 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, &reg32);  in aer_enable_rootport()
1255 	pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);  in aer_enable_rootport()
1256 	pci_read_config_dword(pdev, aer + PCI_ERR_COR_STATUS, &reg32);  in aer_enable_rootport()
1257 	pci_write_config_dword(pdev, aer + PCI_ERR_COR_STATUS, reg32);  in aer_enable_rootport()
1258 	pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, &reg32);  in aer_enable_rootport()
1259 	pci_write_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, reg32);  in aer_enable_rootport()
1262 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_enable_rootport()
1264 	pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);  in aer_enable_rootport()
1276 	int aer = pdev->aer_cap;  in aer_disable_rootport()  local
1280 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_disable_rootport()
1282 	pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);  in aer_disable_rootport()
1285 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, &reg32);  in aer_disable_rootport()
1286 	pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);  in aer_disable_rootport()
1355 	int aer;  in aer_root_reset()  local
1375 	aer = root ? root->aer_cap : 0;  in aer_root_reset()
1377 	if ((host->native_aer || pcie_ports_native) && aer) {  in aer_root_reset()
1379 		pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_root_reset()
1381 		pci_write_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, reg32);  in aer_root_reset()
1396 	if ((host->native_aer || pcie_ports_native) && aer) {  in aer_root_reset()
1398 		pci_read_config_dword(root, aer + PCI_ERR_ROOT_STATUS, &reg32);  in aer_root_reset()
1399 		pci_write_config_dword(root, aer + PCI_ERR_ROOT_STATUS, reg32);  in aer_root_reset()
1402 		pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_root_reset()
1404 		pci_write_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, reg32);  in aer_root_reset()