1451 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_iqk()
1478 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_a_iqk()
1487 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_iqk()
1524 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1536 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_a_rx_iqk()
1557 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_a_rx_iqk()
1566 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1599 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1628 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_a_rx_iqk()
1637 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1644 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1671 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_iqk()
1698 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_b_iqk()
1707 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_iqk()
1744 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_rx_iqk()
1777 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_b_rx_iqk()
1786 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_rx_iqk()
1819 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_rx_iqk()
1847 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_b_rx_iqk()
1856 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_rx_iqk()
2130 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0);  in _rtl8723be_phy_iq_calibrate()