1930 	u32 reg_eac, reg_e94, reg_e9c;  in _rtl92ee_phy_path_a_iqk()  local
1956 	reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);  in _rtl92ee_phy_path_a_iqk()
1960 	    (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&  in _rtl92ee_phy_path_a_iqk()
2015 	u32 reg_eac, reg_e94, reg_e9c, reg_ea4 , u32temp;  in _rtl92ee_phy_path_a_rx_iqk()  local
2058 	reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2062 	    (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&  in _rtl92ee_phy_path_a_rx_iqk()
2072 	u32temp = 0x80007C00 | (reg_e94 & 0x3FF0000)  |  in _rtl92ee_phy_path_a_rx_iqk()
2789 	long reg_e94, reg_e9c, reg_ea4;  in rtl92ee_phy_iq_calibrate()  local
2857 	reg_e94 = result[3][0];  in rtl92ee_phy_iq_calibrate()
2865 		reg_e94 = result[final_candidate][0];  in rtl92ee_phy_iq_calibrate()
2866 		rtlphy->reg_e94 = reg_e94;  in rtl92ee_phy_iq_calibrate()
2878 		rtlphy->reg_e94 = 0x100;  in rtl92ee_phy_iq_calibrate()
2884 	if (reg_e94 != 0)  in rtl92ee_phy_iq_calibrate()