Lines Matching refs:priv
481 static int rtl8192eu_identify_chip(struct rtl8xxxu_priv *priv) in rtl8192eu_identify_chip() argument
483 struct device *dev = &priv->udev->dev; in rtl8192eu_identify_chip()
487 sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); in rtl8192eu_identify_chip()
488 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); in rtl8192eu_identify_chip()
495 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM); in rtl8192eu_identify_chip()
498 strscpy(priv->chip_name, "8191EU", sizeof(priv->chip_name)); in rtl8192eu_identify_chip()
499 priv->tx_paths = 1; in rtl8192eu_identify_chip()
500 priv->rtl_chip = RTL8191E; in rtl8192eu_identify_chip()
502 strscpy(priv->chip_name, "8192EU", sizeof(priv->chip_name)); in rtl8192eu_identify_chip()
503 priv->tx_paths = 2; in rtl8192eu_identify_chip()
504 priv->rtl_chip = RTL8192E; in rtl8192eu_identify_chip()
506 priv->rf_paths = 2; in rtl8192eu_identify_chip()
507 priv->rx_paths = 2; in rtl8192eu_identify_chip()
508 priv->has_wifi = 1; in rtl8192eu_identify_chip()
511 rtl8xxxu_identify_vendor_2bits(priv, vendor); in rtl8192eu_identify_chip()
513 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); in rtl8192eu_identify_chip()
514 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); in rtl8192eu_identify_chip()
516 rtl8xxxu_config_endpoints_sie(priv); in rtl8192eu_identify_chip()
521 if (!priv->ep_tx_count) in rtl8192eu_identify_chip()
522 ret = rtl8xxxu_config_endpoints_no_sie(priv); in rtl8192eu_identify_chip()
529 rtl8192e_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) in rtl8192e_set_tx_power() argument
538 cck = priv->cck_tx_power_index_A[group]; in rtl8192e_set_tx_power()
540 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); in rtl8192e_set_tx_power()
543 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8192e_set_tx_power()
545 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8192e_set_tx_power()
548 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8192e_set_tx_power()
550 ofdmbase = priv->ht40_1s_tx_power_index_A[group]; in rtl8192e_set_tx_power()
551 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].a; in rtl8192e_set_tx_power()
554 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); in rtl8192e_set_tx_power()
555 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); in rtl8192e_set_tx_power()
557 mcsbase = priv->ht40_1s_tx_power_index_A[group]; in rtl8192e_set_tx_power()
559 mcsbase += priv->ht40_tx_power_diff[tx_idx++].a; in rtl8192e_set_tx_power()
561 mcsbase += priv->ht20_tx_power_diff[tx_idx++].a; in rtl8192e_set_tx_power()
564 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); in rtl8192e_set_tx_power()
565 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); in rtl8192e_set_tx_power()
566 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs); in rtl8192e_set_tx_power()
567 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs); in rtl8192e_set_tx_power()
569 if (priv->tx_paths > 1) { in rtl8192e_set_tx_power()
570 cck = priv->cck_tx_power_index_B[group]; in rtl8192e_set_tx_power()
572 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); in rtl8192e_set_tx_power()
575 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); in rtl8192e_set_tx_power()
577 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8192e_set_tx_power()
580 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8192e_set_tx_power()
582 ofdmbase = priv->ht40_1s_tx_power_index_B[group]; in rtl8192e_set_tx_power()
583 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b; in rtl8192e_set_tx_power()
587 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm); in rtl8192e_set_tx_power()
588 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm); in rtl8192e_set_tx_power()
590 mcsbase = priv->ht40_1s_tx_power_index_B[group]; in rtl8192e_set_tx_power()
592 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b; in rtl8192e_set_tx_power()
594 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b; in rtl8192e_set_tx_power()
597 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs); in rtl8192e_set_tx_power()
598 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs); in rtl8192e_set_tx_power()
599 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs); in rtl8192e_set_tx_power()
600 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs); in rtl8192e_set_tx_power()
604 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv) in rtl8192eu_parse_efuse() argument
606 struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu; in rtl8192eu_parse_efuse()
612 ether_addr_copy(priv->mac_addr, efuse->mac_addr); in rtl8192eu_parse_efuse()
614 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, in rtl8192eu_parse_efuse()
616 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, in rtl8192eu_parse_efuse()
619 memcpy(priv->ht40_1s_tx_power_index_A, in rtl8192eu_parse_efuse()
622 memcpy(priv->ht40_1s_tx_power_index_B, in rtl8192eu_parse_efuse()
626 priv->ht20_tx_power_diff[0].a = in rtl8192eu_parse_efuse()
628 priv->ht20_tx_power_diff[0].b = in rtl8192eu_parse_efuse()
631 priv->ht40_tx_power_diff[0].a = 0; in rtl8192eu_parse_efuse()
632 priv->ht40_tx_power_diff[0].b = 0; in rtl8192eu_parse_efuse()
635 priv->ofdm_tx_power_diff[i].a = in rtl8192eu_parse_efuse()
637 priv->ofdm_tx_power_diff[i].b = in rtl8192eu_parse_efuse()
640 priv->ht20_tx_power_diff[i].a = in rtl8192eu_parse_efuse()
642 priv->ht20_tx_power_diff[i].b = in rtl8192eu_parse_efuse()
645 priv->ht40_tx_power_diff[i].a = in rtl8192eu_parse_efuse()
647 priv->ht40_tx_power_diff[i].b = in rtl8192eu_parse_efuse()
651 priv->default_crystal_cap = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f; in rtl8192eu_parse_efuse()
656 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv) in rtl8192eu_load_firmware() argument
663 ret = rtl8xxxu_load_firmware(priv, fw_name); in rtl8192eu_load_firmware()
668 static void rtl8192eu_init_phy_bb(struct rtl8xxxu_priv *priv) in rtl8192eu_init_phy_bb() argument
673 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8192eu_init_phy_bb()
675 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8192eu_init_phy_bb()
679 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); in rtl8192eu_init_phy_bb()
681 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8192eu_init_phy_bb()
684 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8192eu_init_phy_bb()
686 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); in rtl8192eu_init_phy_bb()
687 rtl8xxxu_init_phy_regs(priv, rtl8192eu_phy_init_table); in rtl8192eu_init_phy_bb()
689 if (priv->hi_pa) in rtl8192eu_init_phy_bb()
690 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_highpa_table); in rtl8192eu_init_phy_bb()
692 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_std_table); in rtl8192eu_init_phy_bb()
695 static int rtl8192eu_init_phy_rf(struct rtl8xxxu_priv *priv) in rtl8192eu_init_phy_rf() argument
699 ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radioa_init_table, RF_A); in rtl8192eu_init_phy_rf()
703 ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radiob_init_table, RF_B); in rtl8192eu_init_phy_rf()
709 static int rtl8192eu_iqk_path_a(struct rtl8xxxu_priv *priv) in rtl8192eu_iqk_path_a() argument
718 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_iqk_path_a()
719 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00180); in rtl8192eu_iqk_path_a()
721 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_iqk_path_a()
722 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); in rtl8192eu_iqk_path_a()
723 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_iqk_path_a()
724 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07f77); in rtl8192eu_iqk_path_a()
726 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_iqk_path_a()
729 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); in rtl8192eu_iqk_path_a()
730 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_iqk_path_a()
731 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_iqk_path_a()
732 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_iqk_path_a()
734 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140303); in rtl8192eu_iqk_path_a()
735 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160000); in rtl8192eu_iqk_path_a()
738 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); in rtl8192eu_iqk_path_a()
741 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8192eu_iqk_path_a()
742 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_iqk_path_a()
747 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_iqk_path_a()
748 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); in rtl8192eu_iqk_path_a()
749 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); in rtl8192eu_iqk_path_a()
759 static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) in rtl8192eu_rx_iqk_path_a() argument
765 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00); in rtl8192eu_rx_iqk_path_a()
768 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_a()
769 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_a()
770 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_a()
771 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173); in rtl8192eu_rx_iqk_path_a()
773 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_a()
774 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_a()
775 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_a()
776 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf1173); in rtl8192eu_rx_iqk_path_a()
779 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00980); in rtl8192eu_rx_iqk_path_a()
780 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x511e0); in rtl8192eu_rx_iqk_path_a()
783 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_rx_iqk_path_a()
786 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192eu_rx_iqk_path_a()
787 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_rx_iqk_path_a()
790 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); in rtl8192eu_rx_iqk_path_a()
791 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
792 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
793 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
795 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8216031f); in rtl8192eu_rx_iqk_path_a()
796 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x6816031f); in rtl8192eu_rx_iqk_path_a()
799 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); in rtl8192eu_rx_iqk_path_a()
802 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8192eu_rx_iqk_path_a()
803 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_rx_iqk_path_a()
808 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_rx_iqk_path_a()
809 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); in rtl8192eu_rx_iqk_path_a()
810 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); in rtl8192eu_rx_iqk_path_a()
818 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_a()
819 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); in rtl8192eu_rx_iqk_path_a()
825 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8192eu_rx_iqk_path_a()
828 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_a()
830 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_a()
831 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_a()
832 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_a()
833 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2); in rtl8192eu_rx_iqk_path_a()
835 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_a()
836 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_a()
837 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_a()
838 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ff2); in rtl8192eu_rx_iqk_path_a()
841 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00980); in rtl8192eu_rx_iqk_path_a()
842 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x510e0); in rtl8192eu_rx_iqk_path_a()
845 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_rx_iqk_path_a()
848 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_rx_iqk_path_a()
851 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
852 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); in rtl8192eu_rx_iqk_path_a()
853 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
854 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
856 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821608ff); in rtl8192eu_rx_iqk_path_a()
857 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281608ff); in rtl8192eu_rx_iqk_path_a()
860 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891); in rtl8192eu_rx_iqk_path_a()
863 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8192eu_rx_iqk_path_a()
864 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_rx_iqk_path_a()
868 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_rx_iqk_path_a()
869 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); in rtl8192eu_rx_iqk_path_a()
871 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_a()
872 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); in rtl8192eu_rx_iqk_path_a()
879 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", in rtl8192eu_rx_iqk_path_a()
886 static int rtl8192eu_iqk_path_b(struct rtl8xxxu_priv *priv) in rtl8192eu_iqk_path_b() argument
891 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_iqk_path_b()
892 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00180); in rtl8192eu_iqk_path_b()
894 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_iqk_path_b()
895 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x20000); in rtl8192eu_iqk_path_b()
896 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_iqk_path_b()
897 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0x07f77); in rtl8192eu_iqk_path_b()
899 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_iqk_path_b()
902 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_iqk_path_b()
903 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_iqk_path_b()
904 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); in rtl8192eu_iqk_path_b()
905 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_iqk_path_b()
907 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140303); in rtl8192eu_iqk_path_b()
908 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160000); in rtl8192eu_iqk_path_b()
911 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); in rtl8192eu_iqk_path_b()
914 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); in rtl8192eu_iqk_path_b()
915 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_iqk_path_b()
920 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_iqk_path_b()
921 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8192eu_iqk_path_b()
922 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8192eu_iqk_path_b()
929 dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n", in rtl8192eu_iqk_path_b()
935 static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv) in rtl8192eu_rx_iqk_path_b() argument
941 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_b()
944 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_b()
945 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_b()
946 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_b()
947 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf1173); in rtl8192eu_rx_iqk_path_b()
949 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_b()
950 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_b()
951 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_b()
952 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173); in rtl8192eu_rx_iqk_path_b()
955 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00980); in rtl8192eu_rx_iqk_path_b()
956 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_PAD_TXG, 0x511e0); in rtl8192eu_rx_iqk_path_b()
959 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_rx_iqk_path_b()
962 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192eu_rx_iqk_path_b()
963 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_rx_iqk_path_b()
966 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
967 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
968 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); in rtl8192eu_rx_iqk_path_b()
969 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
971 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x8216031f); in rtl8192eu_rx_iqk_path_b()
972 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x6816031f); in rtl8192eu_rx_iqk_path_b()
975 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); in rtl8192eu_rx_iqk_path_b()
978 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); in rtl8192eu_rx_iqk_path_b()
979 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_rx_iqk_path_b()
984 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_rx_iqk_path_b()
985 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8192eu_rx_iqk_path_b()
986 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8192eu_rx_iqk_path_b()
997 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_b()
998 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x180); in rtl8192eu_rx_iqk_path_b()
1004 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8192eu_rx_iqk_path_b()
1007 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_b()
1009 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_b()
1010 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_b()
1011 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_b()
1012 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ff2); in rtl8192eu_rx_iqk_path_b()
1014 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_b()
1015 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_b()
1016 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_b()
1017 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2); in rtl8192eu_rx_iqk_path_b()
1020 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00980); in rtl8192eu_rx_iqk_path_b()
1021 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_PAD_TXG, 0x510e0); in rtl8192eu_rx_iqk_path_b()
1024 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_rx_iqk_path_b()
1027 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_rx_iqk_path_b()
1030 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
1031 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
1032 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
1033 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c); in rtl8192eu_rx_iqk_path_b()
1035 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821608ff); in rtl8192eu_rx_iqk_path_b()
1036 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281608ff); in rtl8192eu_rx_iqk_path_b()
1039 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891); in rtl8192eu_rx_iqk_path_b()
1042 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); in rtl8192eu_rx_iqk_path_b()
1043 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_rx_iqk_path_b()
1047 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_rx_iqk_path_b()
1048 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); in rtl8192eu_rx_iqk_path_b()
1049 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); in rtl8192eu_rx_iqk_path_b()
1051 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_b()
1052 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x180); in rtl8192eu_rx_iqk_path_b()
1059 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", in rtl8192eu_rx_iqk_path_b()
1066 static void rtl8192eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, in rtl8192eu_phy_iqcalibrate() argument
1069 struct device *dev = &priv->udev->dev; in rtl8192eu_phy_iqcalibrate()
1093 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff; in rtl8192eu_phy_iqcalibrate()
1094 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff; in rtl8192eu_phy_iqcalibrate()
1103 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, in rtl8192eu_phy_iqcalibrate()
1105 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); in rtl8192eu_phy_iqcalibrate()
1106 rtl8xxxu_save_regs(priv, iqk_bb_regs, in rtl8192eu_phy_iqcalibrate()
1107 priv->bb_backup, RTL8XXXU_BB_REGS); in rtl8192eu_phy_iqcalibrate()
1110 rtl8xxxu_path_adda_on(priv, adda_regs, true); in rtl8192eu_phy_iqcalibrate()
1113 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); in rtl8192eu_phy_iqcalibrate()
1115 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); in rtl8192eu_phy_iqcalibrate()
1117 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); in rtl8192eu_phy_iqcalibrate()
1119 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); in rtl8192eu_phy_iqcalibrate()
1120 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); in rtl8192eu_phy_iqcalibrate()
1121 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22208200); in rtl8192eu_phy_iqcalibrate()
1123 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); in rtl8192eu_phy_iqcalibrate()
1125 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); in rtl8192eu_phy_iqcalibrate()
1127 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); in rtl8192eu_phy_iqcalibrate()
1129 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); in rtl8192eu_phy_iqcalibrate()
1130 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); in rtl8192eu_phy_iqcalibrate()
1132 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); in rtl8192eu_phy_iqcalibrate()
1134 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_phy_iqcalibrate()
1135 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192eu_phy_iqcalibrate()
1136 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_phy_iqcalibrate()
1139 path_a_ok = rtl8192eu_iqk_path_a(priv); in rtl8192eu_phy_iqcalibrate()
1141 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1144 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1156 path_a_ok = rtl8192eu_rx_iqk_path_a(priv); in rtl8192eu_phy_iqcalibrate()
1158 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1161 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1172 if (priv->rf_paths > 1) { in rtl8192eu_phy_iqcalibrate()
1174 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_phy_iqcalibrate()
1175 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000); in rtl8192eu_phy_iqcalibrate()
1176 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_phy_iqcalibrate()
1179 rtl8xxxu_path_adda_on(priv, adda_regs, false); in rtl8192eu_phy_iqcalibrate()
1181 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_phy_iqcalibrate()
1182 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192eu_phy_iqcalibrate()
1183 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_phy_iqcalibrate()
1186 path_b_ok = rtl8192eu_iqk_path_b(priv); in rtl8192eu_phy_iqcalibrate()
1188 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8192eu_phy_iqcalibrate()
1190 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8192eu_phy_iqcalibrate()
1200 path_b_ok = rtl8192eu_rx_iqk_path_b(priv); in rtl8192eu_phy_iqcalibrate()
1202 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1205 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1217 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_phy_iqcalibrate()
1221 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, in rtl8192eu_phy_iqcalibrate()
1225 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); in rtl8192eu_phy_iqcalibrate()
1228 rtl8xxxu_restore_regs(priv, iqk_bb_regs, in rtl8192eu_phy_iqcalibrate()
1229 priv->bb_backup, RTL8XXXU_BB_REGS); in rtl8192eu_phy_iqcalibrate()
1232 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8192eu_phy_iqcalibrate()
1234 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); in rtl8192eu_phy_iqcalibrate()
1235 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); in rtl8192eu_phy_iqcalibrate()
1237 if (priv->rf_paths > 1) { in rtl8192eu_phy_iqcalibrate()
1238 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); in rtl8192eu_phy_iqcalibrate()
1240 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, in rtl8192eu_phy_iqcalibrate()
1242 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, in rtl8192eu_phy_iqcalibrate()
1247 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); in rtl8192eu_phy_iqcalibrate()
1248 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); in rtl8192eu_phy_iqcalibrate()
1252 static void rtl8192eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) in rtl8192eu_phy_iq_calibrate() argument
1254 struct device *dev = &priv->udev->dev; in rtl8192eu_phy_iq_calibrate()
1269 rtl8192eu_phy_iqcalibrate(priv, result, i); in rtl8192eu_phy_iq_calibrate()
1272 simu = rtl8xxxu_gen2_simularity_compare(priv, in rtl8192eu_phy_iq_calibrate()
1281 simu = rtl8xxxu_gen2_simularity_compare(priv, in rtl8192eu_phy_iq_calibrate()
1288 simu = rtl8xxxu_gen2_simularity_compare(priv, in rtl8192eu_phy_iq_calibrate()
1308 priv->rege94 = reg_e94; in rtl8192eu_phy_iq_calibrate()
1310 priv->rege9c = reg_e9c; in rtl8192eu_phy_iq_calibrate()
1314 priv->regeb4 = reg_eb4; in rtl8192eu_phy_iq_calibrate()
1316 priv->regebc = reg_ebc; in rtl8192eu_phy_iq_calibrate()
1327 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; in rtl8192eu_phy_iq_calibrate()
1328 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; in rtl8192eu_phy_iq_calibrate()
1332 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, in rtl8192eu_phy_iq_calibrate()
1335 if (priv->rf_paths > 1) in rtl8192eu_phy_iq_calibrate()
1336 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, in rtl8192eu_phy_iq_calibrate()
1339 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, in rtl8192eu_phy_iq_calibrate()
1340 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); in rtl8192eu_phy_iq_calibrate()
1346 static void rtl8192e_crystal_afe_adjust(struct rtl8xxxu_priv *priv) in rtl8192e_crystal_afe_adjust() argument
1354 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); in rtl8192e_crystal_afe_adjust()
1356 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); in rtl8192e_crystal_afe_adjust()
1358 val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4); in rtl8192e_crystal_afe_adjust()
1360 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); in rtl8192e_crystal_afe_adjust()
1366 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); in rtl8192e_crystal_afe_adjust()
1368 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); in rtl8192e_crystal_afe_adjust()
1373 val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4); in rtl8192e_crystal_afe_adjust()
1375 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); in rtl8192e_crystal_afe_adjust()
1378 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv) in rtl8192e_disabled_to_emu() argument
1383 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192e_disabled_to_emu()
1385 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192e_disabled_to_emu()
1388 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv) in rtl8192e_emu_to_active() argument
1395 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192e_emu_to_active()
1397 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192e_emu_to_active()
1400 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192e_emu_to_active()
1402 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192e_emu_to_active()
1405 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192e_emu_to_active()
1407 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192e_emu_to_active()
1411 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192e_emu_to_active()
1426 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); in rtl8192e_emu_to_active()
1428 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); in rtl8192e_emu_to_active()
1431 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192e_emu_to_active()
1433 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8192e_emu_to_active()
1436 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192e_emu_to_active()
1453 static int rtl8192eu_active_to_lps(struct rtl8xxxu_priv *priv) in rtl8192eu_active_to_lps() argument
1455 struct device *dev = &priv->udev->dev; in rtl8192eu_active_to_lps()
1461 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); in rtl8192eu_active_to_lps()
1469 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); in rtl8192eu_active_to_lps()
1483 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); in rtl8192eu_active_to_lps()
1485 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); in rtl8192eu_active_to_lps()
1490 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); in rtl8192eu_active_to_lps()
1492 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); in rtl8192eu_active_to_lps()
1495 val16 = rtl8xxxu_read16(priv, REG_CR); in rtl8192eu_active_to_lps()
1498 rtl8xxxu_write16(priv, REG_CR, val16); in rtl8192eu_active_to_lps()
1500 val16 = rtl8xxxu_read16(priv, REG_CR); in rtl8192eu_active_to_lps()
1502 rtl8xxxu_write16(priv, REG_CR, val16); in rtl8192eu_active_to_lps()
1504 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); in rtl8192eu_active_to_lps()
1506 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); in rtl8192eu_active_to_lps()
1512 static int rtl8192eu_active_to_emu(struct rtl8xxxu_priv *priv) in rtl8192eu_active_to_emu() argument
1518 val8 = rtl8xxxu_read8(priv, REG_RF_CTRL); in rtl8192eu_active_to_emu()
1520 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); in rtl8192eu_active_to_emu()
1523 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); in rtl8192eu_active_to_emu()
1525 rtl8xxxu_write8(priv, REG_LEDCFG2, val8); in rtl8192eu_active_to_emu()
1528 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192eu_active_to_emu()
1530 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192eu_active_to_emu()
1533 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192eu_active_to_emu()
1540 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", in rtl8192eu_active_to_emu()
1550 static int rtl8192eu_emu_to_disabled(struct rtl8xxxu_priv *priv) in rtl8192eu_emu_to_disabled() argument
1555 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192eu_emu_to_disabled()
1558 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192eu_emu_to_disabled()
1563 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv) in rtl8192eu_power_on() argument
1569 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG); in rtl8192eu_power_on()
1571 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3); in rtl8192eu_power_on()
1576 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL); in rtl8192eu_power_on()
1579 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32); in rtl8192eu_power_on()
1580 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83); in rtl8192eu_power_on()
1586 rtl8192e_crystal_afe_adjust(priv); in rtl8192eu_power_on()
1587 rtl8192e_disabled_to_emu(priv); in rtl8192eu_power_on()
1589 ret = rtl8192e_emu_to_active(priv); in rtl8192eu_power_on()
1593 rtl8xxxu_write16(priv, REG_CR, 0x0000); in rtl8192eu_power_on()
1599 val16 = rtl8xxxu_read16(priv, REG_CR); in rtl8192eu_power_on()
1605 rtl8xxxu_write16(priv, REG_CR, val16); in rtl8192eu_power_on()
1611 static void rtl8192eu_power_off(struct rtl8xxxu_priv *priv) in rtl8192eu_power_off() argument
1616 rtl8xxxu_flush_fifo(priv); in rtl8192eu_power_off()
1618 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); in rtl8192eu_power_off()
1620 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); in rtl8192eu_power_off()
1623 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); in rtl8192eu_power_off()
1625 rtl8192eu_active_to_lps(priv); in rtl8192eu_power_off()
1628 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) in rtl8192eu_power_off()
1629 rtl8xxxu_firmware_self_reset(priv); in rtl8192eu_power_off()
1632 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8192eu_power_off()
1634 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8192eu_power_off()
1637 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); in rtl8192eu_power_off()
1639 rtl8xxxu_reset_8051(priv); in rtl8192eu_power_off()
1641 rtl8192eu_active_to_emu(priv); in rtl8192eu_power_off()
1642 rtl8192eu_emu_to_disabled(priv); in rtl8192eu_power_off()
1645 static void rtl8192e_enable_rf(struct rtl8xxxu_priv *priv) in rtl8192e_enable_rf() argument
1650 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); in rtl8192e_enable_rf()
1652 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); in rtl8192e_enable_rf()
1654 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); in rtl8192e_enable_rf()
1656 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); in rtl8192e_enable_rf()
1661 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04); in rtl8192e_enable_rf()
1663 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); in rtl8192e_enable_rf()
1665 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); in rtl8192e_enable_rf()
1667 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); in rtl8192e_enable_rf()
1669 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); in rtl8192e_enable_rf()
1671 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77); in rtl8192e_enable_rf()
1673 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8192e_enable_rf()
1676 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8192e_enable_rf()
1681 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); in rtl8192e_enable_rf()
1683 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); in rtl8192e_enable_rf()
1688 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); in rtl8192e_enable_rf()
1691 static s8 rtl8192e_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) in rtl8192e_cck_rssi() argument
1704 if (priv->cck_agc_report_type == 0) in rtl8192e_cck_rssi()
1717 struct rtl8xxxu_priv *priv = container_of(led_cdev, in rtl8192eu_led_brightness_set() local
1720 u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG1); in rtl8192eu_led_brightness_set()
1732 rtl8xxxu_write8(priv, REG_LEDCFG1, ledcfg); in rtl8192eu_led_brightness_set()