Lines Matching refs:dev
16 static void mt7601u_agc_reset(struct mt7601u_dev *dev);
19 mt7601u_rf_wr(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 value) in mt7601u_rf_wr() argument
23 if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) || in mt7601u_rf_wr()
26 if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) in mt7601u_rf_wr()
29 mutex_lock(&dev->reg_atomic_mutex); in mt7601u_rf_wr()
31 if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) { in mt7601u_rf_wr()
36 mt7601u_wr(dev, MT_RF_CSR_CFG, in mt7601u_rf_wr()
42 trace_rf_write(dev, bank, offset, value); in mt7601u_rf_wr()
44 mutex_unlock(&dev->reg_atomic_mutex); in mt7601u_rf_wr()
47 dev_err(dev->dev, "Error: RF write %02hhx:%02hhx failed:%d!!\n", in mt7601u_rf_wr()
54 mt7601u_rf_rr(struct mt7601u_dev *dev, u8 bank, u8 offset) in mt7601u_rf_rr() argument
59 if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) || in mt7601u_rf_rr()
62 if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) in mt7601u_rf_rr()
65 mutex_lock(&dev->reg_atomic_mutex); in mt7601u_rf_rr()
67 if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) in mt7601u_rf_rr()
70 mt7601u_wr(dev, MT_RF_CSR_CFG, in mt7601u_rf_rr()
75 if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) in mt7601u_rf_rr()
78 val = mt7601u_rr(dev, MT_RF_CSR_CFG); in mt7601u_rf_rr()
82 trace_rf_read(dev, bank, offset, ret); in mt7601u_rf_rr()
85 mutex_unlock(&dev->reg_atomic_mutex); in mt7601u_rf_rr()
88 dev_err(dev->dev, "Error: RF read %02hhx:%02hhx failed:%d!!\n", in mt7601u_rf_rr()
95 mt7601u_rf_rmw(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask, u8 val) in mt7601u_rf_rmw() argument
99 ret = mt7601u_rf_rr(dev, bank, offset); in mt7601u_rf_rmw()
103 ret = mt7601u_rf_wr(dev, bank, offset, val); in mt7601u_rf_rmw()
111 mt7601u_rf_set(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 val) in mt7601u_rf_set() argument
113 return mt7601u_rf_rmw(dev, bank, offset, 0, val); in mt7601u_rf_set()
117 mt7601u_rf_clear(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask) in mt7601u_rf_clear() argument
119 return mt7601u_rf_rmw(dev, bank, offset, mask, 0); in mt7601u_rf_clear()
122 static void mt7601u_bbp_wr(struct mt7601u_dev *dev, u8 offset, u8 val) in mt7601u_bbp_wr() argument
124 if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) || in mt7601u_bbp_wr()
125 test_bit(MT7601U_STATE_REMOVED, &dev->state)) in mt7601u_bbp_wr()
128 mutex_lock(&dev->reg_atomic_mutex); in mt7601u_bbp_wr()
130 if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000)) { in mt7601u_bbp_wr()
131 dev_err(dev->dev, "Error: BBP write %02hhx failed!!\n", offset); in mt7601u_bbp_wr()
135 mt7601u_wr(dev, MT_BBP_CSR_CFG, in mt7601u_bbp_wr()
139 trace_bbp_write(dev, offset, val); in mt7601u_bbp_wr()
141 mutex_unlock(&dev->reg_atomic_mutex); in mt7601u_bbp_wr()
144 static int mt7601u_bbp_rr(struct mt7601u_dev *dev, u8 offset) in mt7601u_bbp_rr() argument
149 if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state))) in mt7601u_bbp_rr()
151 if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) in mt7601u_bbp_rr()
154 mutex_lock(&dev->reg_atomic_mutex); in mt7601u_bbp_rr()
156 if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000)) in mt7601u_bbp_rr()
159 mt7601u_wr(dev, MT_BBP_CSR_CFG, in mt7601u_bbp_rr()
164 if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000)) in mt7601u_bbp_rr()
167 val = mt7601u_rr(dev, MT_BBP_CSR_CFG); in mt7601u_bbp_rr()
170 trace_bbp_read(dev, offset, ret); in mt7601u_bbp_rr()
173 mutex_unlock(&dev->reg_atomic_mutex); in mt7601u_bbp_rr()
176 dev_err(dev->dev, "Error: BBP read %02hhx failed:%d!!\n", in mt7601u_bbp_rr()
182 static int mt7601u_bbp_rmw(struct mt7601u_dev *dev, u8 offset, u8 mask, u8 val) in mt7601u_bbp_rmw() argument
186 ret = mt7601u_bbp_rr(dev, offset); in mt7601u_bbp_rmw()
190 mt7601u_bbp_wr(dev, offset, val); in mt7601u_bbp_rmw()
195 static u8 mt7601u_bbp_rmc(struct mt7601u_dev *dev, u8 offset, u8 mask, u8 val) in mt7601u_bbp_rmc() argument
199 ret = mt7601u_bbp_rr(dev, offset); in mt7601u_bbp_rmc()
204 mt7601u_bbp_wr(dev, offset, val); in mt7601u_bbp_rmc()
209 int mt7601u_wait_bbp_ready(struct mt7601u_dev *dev) in mt7601u_wait_bbp_ready() argument
215 val = mt7601u_bbp_rr(dev, MT_BBP_REG_VERSION); in mt7601u_wait_bbp_ready()
221 dev_err(dev->dev, "Error: BBP is not ready\n"); in mt7601u_wait_bbp_ready()
228 u32 mt7601u_bbp_set_ctrlch(struct mt7601u_dev *dev, bool below) in mt7601u_bbp_set_ctrlch() argument
230 return mt7601u_bbp_rmc(dev, 3, 0x20, below ? 0x20 : 0); in mt7601u_bbp_set_ctrlch()
233 int mt7601u_phy_get_rssi(struct mt7601u_dev *dev, in mt7601u_phy_get_rssi() argument
257 val -= dev->ee->lna_gain; in mt7601u_phy_get_rssi()
258 val -= dev->ee->rssi_offset[0]; in mt7601u_phy_get_rssi()
263 static void mt7601u_vco_cal(struct mt7601u_dev *dev) in mt7601u_vco_cal() argument
265 mt7601u_rf_wr(dev, 0, 4, 0x0a); in mt7601u_vco_cal()
266 mt7601u_rf_wr(dev, 0, 5, 0x20); in mt7601u_vco_cal()
267 mt7601u_rf_set(dev, 0, 4, BIT(7)); in mt7601u_vco_cal()
271 static int mt7601u_set_bw_filter(struct mt7601u_dev *dev, bool cal) in mt7601u_set_bw_filter() argument
278 if (dev->bw != MT_BW_20) in mt7601u_set_bw_filter()
282 ret = mt7601u_mcu_calibrate(dev, MCU_CAL_BW, filter | 1); in mt7601u_set_bw_filter()
286 return mt7601u_mcu_calibrate(dev, MCU_CAL_BW, filter); in mt7601u_set_bw_filter()
289 static int mt7601u_load_bbp_temp_table_bw(struct mt7601u_dev *dev) in mt7601u_load_bbp_temp_table_bw() argument
293 if (WARN_ON(dev->temp_mode > MT_TEMP_MODE_LOW)) in mt7601u_load_bbp_temp_table_bw()
296 t = &bbp_mode_table[dev->temp_mode][dev->bw]; in mt7601u_load_bbp_temp_table_bw()
298 return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, t->regs, t->n); in mt7601u_load_bbp_temp_table_bw()
301 static int mt7601u_bbp_temp(struct mt7601u_dev *dev, int mode, const char *name) in mt7601u_bbp_temp() argument
306 if (dev->temp_mode == mode) in mt7601u_bbp_temp()
309 dev->temp_mode = mode; in mt7601u_bbp_temp()
310 trace_temp_mode(dev, mode); in mt7601u_bbp_temp()
312 t = bbp_mode_table[dev->temp_mode]; in mt7601u_bbp_temp()
313 ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, in mt7601u_bbp_temp()
318 return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, in mt7601u_bbp_temp()
319 t[dev->bw].regs, t[dev->bw].n); in mt7601u_bbp_temp()
322 static void mt7601u_apply_ch14_fixup(struct mt7601u_dev *dev, int hw_chan) in mt7601u_apply_ch14_fixup() argument
324 struct mt7601u_rate_power *t = &dev->ee->power_rate_table; in mt7601u_apply_ch14_fixup()
326 if (hw_chan != 14 || dev->bw != MT_BW_20) { in mt7601u_apply_ch14_fixup()
327 mt7601u_bbp_rmw(dev, 4, 0x20, 0); in mt7601u_apply_ch14_fixup()
328 mt7601u_bbp_wr(dev, 178, 0xff); in mt7601u_apply_ch14_fixup()
330 t->cck[0].bw20 = dev->ee->real_cck_bw20[0]; in mt7601u_apply_ch14_fixup()
331 t->cck[1].bw20 = dev->ee->real_cck_bw20[1]; in mt7601u_apply_ch14_fixup()
333 mt7601u_bbp_wr(dev, 4, 0x60); in mt7601u_apply_ch14_fixup()
334 mt7601u_bbp_wr(dev, 178, 0); in mt7601u_apply_ch14_fixup()
337 t->cck[0].bw20 = dev->ee->real_cck_bw20[0] - 2; in mt7601u_apply_ch14_fixup()
338 t->cck[1].bw20 = dev->ee->real_cck_bw20[1] - 2; in mt7601u_apply_ch14_fixup()
342 static int __mt7601u_phy_set_channel(struct mt7601u_dev *dev, in __mt7601u_phy_set_channel() argument
366 { 62, 0x37 - dev->ee->lna_gain }, in __mt7601u_phy_set_channel()
367 { 63, 0x37 - dev->ee->lna_gain }, in __mt7601u_phy_set_channel()
368 { 64, 0x37 - dev->ee->lna_gain }, in __mt7601u_phy_set_channel()
374 struct mt7601u_rate_power *t = &dev->ee->power_rate_table; in __mt7601u_phy_set_channel()
392 dev_err(dev->dev, "Error: invalid 40MHz channel!!\n"); in __mt7601u_phy_set_channel()
395 if (bw != dev->bw || chan_ext_below != dev->chan_ext_below) { in __mt7601u_phy_set_channel()
396 dev_dbg(dev->dev, "Info: switching HT mode bw:%d below:%d\n", in __mt7601u_phy_set_channel()
399 mt7601u_bbp_set_bw(dev, bw); in __mt7601u_phy_set_channel()
401 mt7601u_bbp_set_ctrlch(dev, chan_ext_below); in __mt7601u_phy_set_channel()
402 mt7601u_mac_set_ctrlch(dev, chan_ext_below); in __mt7601u_phy_set_channel()
403 dev->chan_ext_below = chan_ext_below; in __mt7601u_phy_set_channel()
409 ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_RF, in __mt7601u_phy_set_channel()
414 mt7601u_rmw(dev, MT_TX_ALC_CFG_0, 0x3f3f, in __mt7601u_phy_set_channel()
415 dev->ee->chan_pwr[chan_idx] & 0x3f); in __mt7601u_phy_set_channel()
417 ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, in __mt7601u_phy_set_channel()
422 mt7601u_vco_cal(dev); in __mt7601u_phy_set_channel()
423 mt7601u_bbp_set_bw(dev, bw); in __mt7601u_phy_set_channel()
424 ret = mt7601u_set_bw_filter(dev, false); in __mt7601u_phy_set_channel()
428 mt7601u_apply_ch14_fixup(dev, chan->hw_value); in __mt7601u_phy_set_channel()
429 mt7601u_wr(dev, MT_TX_PWR_CFG_0, int_to_s6(t->ofdm[1].bw20) << 24 | in __mt7601u_phy_set_channel()
434 if (test_bit(MT7601U_STATE_SCANNING, &dev->state)) in __mt7601u_phy_set_channel()
435 mt7601u_agc_reset(dev); in __mt7601u_phy_set_channel()
437 dev->chandef = *chandef; in __mt7601u_phy_set_channel()
442 int mt7601u_phy_set_channel(struct mt7601u_dev *dev, in mt7601u_phy_set_channel() argument
447 cancel_delayed_work_sync(&dev->cal_work); in mt7601u_phy_set_channel()
448 cancel_delayed_work_sync(&dev->freq_cal.work); in mt7601u_phy_set_channel()
450 mutex_lock(&dev->hw_atomic_mutex); in mt7601u_phy_set_channel()
451 ret = __mt7601u_phy_set_channel(dev, chandef); in mt7601u_phy_set_channel()
452 mutex_unlock(&dev->hw_atomic_mutex); in mt7601u_phy_set_channel()
456 if (test_bit(MT7601U_STATE_SCANNING, &dev->state)) in mt7601u_phy_set_channel()
459 ieee80211_queue_delayed_work(dev->hw, &dev->cal_work, in mt7601u_phy_set_channel()
461 if (dev->freq_cal.enabled) in mt7601u_phy_set_channel()
462 ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work, in mt7601u_phy_set_channel()
484 static u8 mt7601u_bbp_r47_get(struct mt7601u_dev *dev, u8 reg, u8 flag) in mt7601u_bbp_r47_get() argument
487 mt7601u_bbp_wr(dev, 47, flag); in mt7601u_bbp_r47_get()
489 return mt7601u_bbp_rr(dev, 49); in mt7601u_bbp_r47_get()
492 static s8 mt7601u_read_bootup_temp(struct mt7601u_dev *dev) in mt7601u_read_bootup_temp() argument
498 rf_set = mt7601u_rr(dev, MT_RF_SETTING_0); in mt7601u_read_bootup_temp()
499 rf_bp = mt7601u_rr(dev, MT_RF_BYPASS_0); in mt7601u_read_bootup_temp()
501 mt7601u_wr(dev, MT_RF_BYPASS_0, 0); in mt7601u_read_bootup_temp()
502 mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000010); in mt7601u_read_bootup_temp()
503 mt7601u_wr(dev, MT_RF_BYPASS_0, 0x00000010); in mt7601u_read_bootup_temp()
505 bbp_val = mt7601u_bbp_rmw(dev, 47, 0, 0x10); in mt7601u_read_bootup_temp()
507 mt7601u_bbp_wr(dev, 22, 0x40); in mt7601u_read_bootup_temp()
510 bbp_val = mt7601u_bbp_rr(dev, 47); in mt7601u_read_bootup_temp()
512 temp = mt7601u_bbp_r47_get(dev, bbp_val, BBP_R47_F_TEMP); in mt7601u_read_bootup_temp()
514 mt7601u_bbp_wr(dev, 22, 0); in mt7601u_read_bootup_temp()
516 bbp_val = mt7601u_bbp_rr(dev, 21); in mt7601u_read_bootup_temp()
518 mt7601u_bbp_wr(dev, 21, bbp_val); in mt7601u_read_bootup_temp()
520 mt7601u_bbp_wr(dev, 21, bbp_val); in mt7601u_read_bootup_temp()
522 mt7601u_wr(dev, MT_RF_BYPASS_0, 0); in mt7601u_read_bootup_temp()
523 mt7601u_wr(dev, MT_RF_SETTING_0, rf_set); in mt7601u_read_bootup_temp()
524 mt7601u_wr(dev, MT_RF_BYPASS_0, rf_bp); in mt7601u_read_bootup_temp()
526 trace_read_temp(dev, temp); in mt7601u_read_bootup_temp()
530 static s8 mt7601u_read_temp(struct mt7601u_dev *dev) in mt7601u_read_temp() argument
536 val = mt7601u_bbp_rmw(dev, 47, 0x7f, 0x10); in mt7601u_read_temp()
540 val = mt7601u_bbp_rr(dev, 47); in mt7601u_read_temp()
542 temp = mt7601u_bbp_r47_get(dev, val, BBP_R47_F_TEMP); in mt7601u_read_temp()
544 trace_read_temp(dev, temp); in mt7601u_read_temp()
548 static void mt7601u_rxdc_cal(struct mt7601u_dev *dev) in mt7601u_rxdc_cal() argument
559 mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL); in mt7601u_rxdc_cal()
560 mt7601u_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX); in mt7601u_rxdc_cal()
562 ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, in mt7601u_rxdc_cal()
565 dev_err(dev->dev, "%s intro failed:%d\n", __func__, ret); in mt7601u_rxdc_cal()
570 mt7601u_bbp_wr(dev, 158, 0x8c); in mt7601u_rxdc_cal()
571 if (mt7601u_bbp_rr(dev, 159) == 0x0c) in mt7601u_rxdc_cal()
575 dev_err(dev->dev, "%s timed out\n", __func__); in mt7601u_rxdc_cal()
577 mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0); in mt7601u_rxdc_cal()
579 ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, in mt7601u_rxdc_cal()
582 dev_err(dev->dev, "%s outro failed:%d\n", __func__, ret); in mt7601u_rxdc_cal()
584 mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl); in mt7601u_rxdc_cal()
587 void mt7601u_phy_recalibrate_after_assoc(struct mt7601u_dev *dev) in mt7601u_phy_recalibrate_after_assoc() argument
589 if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) in mt7601u_phy_recalibrate_after_assoc()
592 mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->curr_temp); in mt7601u_phy_recalibrate_after_assoc()
594 mt7601u_rxdc_cal(dev); in mt7601u_phy_recalibrate_after_assoc()
630 mt7601u_set_initial_tssi(struct mt7601u_dev *dev, s16 tssi_db, s16 tssi_hvga_db) in mt7601u_set_initial_tssi() argument
632 struct tssi_data *d = &dev->ee->tssi_data; in mt7601u_set_initial_tssi()
637 mt76_rmw(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP, in mt7601u_set_initial_tssi()
641 static void mt7601u_tssi_dc_gain_cal(struct mt7601u_dev *dev) in mt7601u_tssi_dc_gain_cal() argument
648 mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000030); in mt7601u_tssi_dc_gain_cal()
649 mt7601u_wr(dev, MT_RF_BYPASS_0, 0x000c0030); in mt7601u_tssi_dc_gain_cal()
650 mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0); in mt7601u_tssi_dc_gain_cal()
652 mt7601u_bbp_wr(dev, 58, 0); in mt7601u_tssi_dc_gain_cal()
653 mt7601u_bbp_wr(dev, 241, 0x2); in mt7601u_tssi_dc_gain_cal()
654 mt7601u_bbp_wr(dev, 23, 0x8); in mt7601u_tssi_dc_gain_cal()
655 bbp_r47 = mt7601u_bbp_rr(dev, 47); in mt7601u_tssi_dc_gain_cal()
658 rf_vga = mt7601u_rf_rr(dev, 5, 3); in mt7601u_tssi_dc_gain_cal()
659 mt7601u_rf_wr(dev, 5, 3, 8); in mt7601u_tssi_dc_gain_cal()
662 rf_mixer = mt7601u_rf_rr(dev, 4, 39); in mt7601u_tssi_dc_gain_cal()
663 mt7601u_rf_wr(dev, 4, 39, 0); in mt7601u_tssi_dc_gain_cal()
666 mt7601u_rf_wr(dev, 4, 39, (i & 1) ? rf_mixer : 0); in mt7601u_tssi_dc_gain_cal()
668 mt7601u_bbp_wr(dev, 23, (i < 2) ? 0x08 : 0x02); in mt7601u_tssi_dc_gain_cal()
669 mt7601u_rf_wr(dev, 5, 3, (i < 2) ? 0x08 : 0x11); in mt7601u_tssi_dc_gain_cal()
672 mt7601u_bbp_wr(dev, 22, 0); in mt7601u_tssi_dc_gain_cal()
673 mt7601u_bbp_wr(dev, 244, 0); in mt7601u_tssi_dc_gain_cal()
675 mt7601u_bbp_wr(dev, 21, 1); in mt7601u_tssi_dc_gain_cal()
677 mt7601u_bbp_wr(dev, 21, 0); in mt7601u_tssi_dc_gain_cal()
680 mt7601u_bbp_wr(dev, 47, 0x50); in mt7601u_tssi_dc_gain_cal()
681 mt7601u_bbp_wr(dev, (i & 1) ? 244 : 22, (i & 1) ? 0x31 : 0x40); in mt7601u_tssi_dc_gain_cal()
684 if (!(mt7601u_bbp_rr(dev, 47) & 0x10)) in mt7601u_tssi_dc_gain_cal()
687 dev_err(dev->dev, "%s timed out\n", __func__); in mt7601u_tssi_dc_gain_cal()
690 mt7601u_bbp_wr(dev, 47, 0x40); in mt7601u_tssi_dc_gain_cal()
691 res[i] = mt7601u_bbp_rr(dev, 49); in mt7601u_tssi_dc_gain_cal()
696 dev->tssi_init = res[0]; in mt7601u_tssi_dc_gain_cal()
697 dev->tssi_init_hvga = res[2]; in mt7601u_tssi_dc_gain_cal()
698 dev->tssi_init_hvga_offset_db = tssi_init_hvga_db - tssi_init_db; in mt7601u_tssi_dc_gain_cal()
700 dev_dbg(dev->dev, in mt7601u_tssi_dc_gain_cal()
702 dev->tssi_init, tssi_init_db, dev->tssi_init_hvga, in mt7601u_tssi_dc_gain_cal()
703 tssi_init_hvga_db, dev->tssi_init_hvga_offset_db); in mt7601u_tssi_dc_gain_cal()
705 mt7601u_bbp_wr(dev, 22, 0); in mt7601u_tssi_dc_gain_cal()
706 mt7601u_bbp_wr(dev, 244, 0); in mt7601u_tssi_dc_gain_cal()
708 mt7601u_bbp_wr(dev, 21, 1); in mt7601u_tssi_dc_gain_cal()
710 mt7601u_bbp_wr(dev, 21, 0); in mt7601u_tssi_dc_gain_cal()
712 mt7601u_wr(dev, MT_RF_BYPASS_0, 0); in mt7601u_tssi_dc_gain_cal()
713 mt7601u_wr(dev, MT_RF_SETTING_0, 0); in mt7601u_tssi_dc_gain_cal()
715 mt7601u_rf_wr(dev, 5, 3, rf_vga); in mt7601u_tssi_dc_gain_cal()
716 mt7601u_rf_wr(dev, 4, 39, rf_mixer); in mt7601u_tssi_dc_gain_cal()
717 mt7601u_bbp_wr(dev, 47, bbp_r47); in mt7601u_tssi_dc_gain_cal()
719 mt7601u_set_initial_tssi(dev, tssi_init_db, tssi_init_hvga_db); in mt7601u_tssi_dc_gain_cal()
722 static int mt7601u_temp_comp(struct mt7601u_dev *dev, bool on) in mt7601u_temp_comp() argument
726 temp = (dev->raw_temp - dev->ee->ref_temp) * MT_EE_TEMPERATURE_SLOPE; in mt7601u_temp_comp()
727 dev->curr_temp = temp; in mt7601u_temp_comp()
730 if (temp - dev->dpd_temp > 450 || temp - dev->dpd_temp < -450) { in mt7601u_temp_comp()
731 dev->dpd_temp = temp; in mt7601u_temp_comp()
733 ret = mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->dpd_temp); in mt7601u_temp_comp()
737 mt7601u_vco_cal(dev); in mt7601u_temp_comp()
739 dev_dbg(dev->dev, "Recalibrate DPD\n"); in mt7601u_temp_comp()
743 if (temp < -50 && !dev->pll_lock_protect) { /* < 20C */ in mt7601u_temp_comp()
744 dev->pll_lock_protect = true; in mt7601u_temp_comp()
746 mt7601u_rf_wr(dev, 4, 4, 6); in mt7601u_temp_comp()
747 mt7601u_rf_clear(dev, 4, 10, 0x30); in mt7601u_temp_comp()
749 dev_dbg(dev->dev, "PLL lock protect on - too cold\n"); in mt7601u_temp_comp()
750 } else if (temp > 50 && dev->pll_lock_protect) { /* > 30C */ in mt7601u_temp_comp()
751 dev->pll_lock_protect = false; in mt7601u_temp_comp()
753 mt7601u_rf_wr(dev, 4, 4, 0); in mt7601u_temp_comp()
754 mt7601u_rf_rmw(dev, 4, 10, 0x30, 0x10); in mt7601u_temp_comp()
756 dev_dbg(dev->dev, "PLL lock protect off\n"); in mt7601u_temp_comp()
766 return mt7601u_bbp_temp(dev, MT_TEMP_MODE_HIGH, "high"); in mt7601u_temp_comp()
768 return mt7601u_bbp_temp(dev, MT_TEMP_MODE_NORMAL, "normal"); in mt7601u_temp_comp()
770 return mt7601u_bbp_temp(dev, MT_TEMP_MODE_LOW, "low"); in mt7601u_temp_comp()
774 static int mt7601u_current_tx_power(struct mt7601u_dev *dev) in mt7601u_current_tx_power() argument
776 return dev->ee->chan_pwr[dev->chandef.chan->hw_value - 1]; in mt7601u_current_tx_power()
779 static bool mt7601u_use_hvga(struct mt7601u_dev *dev) in mt7601u_use_hvga() argument
781 return !(mt7601u_current_tx_power(dev) > 20); in mt7601u_use_hvga()
785 mt7601u_phy_rf_pa_mode_val(struct mt7601u_dev *dev, int phy_mode, int tx_rate) in mt7601u_phy_rf_pa_mode_val() argument
795 reg = dev->rf_pa_mode[0]; in mt7601u_phy_rf_pa_mode_val()
798 reg = dev->rf_pa_mode[1]; in mt7601u_phy_rf_pa_mode_val()
806 mt7601u_tssi_params_get(struct mt7601u_dev *dev) in mt7601u_tssi_params_get() argument
814 bbp_r47 = mt7601u_bbp_rr(dev, 47); in mt7601u_tssi_params_get()
816 p.tssi0 = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TSSI); in mt7601u_tssi_params_get()
817 dev->raw_temp = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TEMP); in mt7601u_tssi_params_get()
818 pkt_type = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_PKT_T); in mt7601u_tssi_params_get()
820 p.trgt_power = mt7601u_current_tx_power(dev); in mt7601u_tssi_params_get()
825 rate_table = dev->ee->power_rate_table.cck; in mt7601u_tssi_params_get()
830 rate_table = dev->ee->power_rate_table.ofdm; in mt7601u_tssi_params_get()
834 tx_rate = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TX_RATE); in mt7601u_tssi_params_get()
836 rate_table = dev->ee->power_rate_table.ht; in mt7601u_tssi_params_get()
840 if (dev->bw == MT_BW_20) in mt7601u_tssi_params_get()
847 dev_dbg(dev->dev, "tx_rate:%02hhx pwr:%08x\n", tx_rate, p.trgt_power); in mt7601u_tssi_params_get()
849 p.trgt_power += mt7601u_phy_rf_pa_mode_val(dev, pkt_type & 0x03, in mt7601u_tssi_params_get()
854 if (mt7601u_bbp_rr(dev, 4) & 0x20) in mt7601u_tssi_params_get()
855 p.trgt_power += mt7601u_bbp_rr(dev, 178) ? 18022 : 9830; in mt7601u_tssi_params_get()
857 p.trgt_power += mt7601u_bbp_rr(dev, 178) ? 819 : 24576; in mt7601u_tssi_params_get()
860 p.trgt_power += static_power[mt7601u_bbp_rr(dev, 1) & 0x03]; in mt7601u_tssi_params_get()
862 p.trgt_power += dev->ee->tssi_data.tx0_delta_offset; in mt7601u_tssi_params_get()
864 dev_dbg(dev->dev, in mt7601u_tssi_params_get()
866 p.tssi0, p.trgt_power, dev->raw_temp, pkt_type); in mt7601u_tssi_params_get()
871 static bool mt7601u_tssi_read_ready(struct mt7601u_dev *dev) in mt7601u_tssi_read_ready() argument
873 return !(mt7601u_bbp_rr(dev, 47) & 0x10); in mt7601u_tssi_read_ready()
876 static int mt7601u_tssi_cal(struct mt7601u_dev *dev) in mt7601u_tssi_cal() argument
886 if (!dev->ee->tssi_enabled) in mt7601u_tssi_cal()
889 hvga = mt7601u_use_hvga(dev); in mt7601u_tssi_cal()
890 if (!dev->tssi_read_trig) in mt7601u_tssi_cal()
891 return mt7601u_mcu_tssi_read_kick(dev, hvga); in mt7601u_tssi_cal()
893 if (!mt7601u_tssi_read_ready(dev)) in mt7601u_tssi_cal()
896 params = mt7601u_tssi_params_get(dev); in mt7601u_tssi_cal()
898 tssi_init = (hvga ? dev->tssi_init_hvga : dev->tssi_init); in mt7601u_tssi_cal()
901 dev_dbg(dev->dev, "tssi dc:%04hx db:%04hx hvga:%d\n", in mt7601u_tssi_cal()
904 if (dev->chandef.chan->hw_value < 5) in mt7601u_tssi_cal()
905 tssi_offset = dev->ee->tssi_data.offset[0]; in mt7601u_tssi_cal()
906 else if (dev->chandef.chan->hw_value < 9) in mt7601u_tssi_cal()
907 tssi_offset = dev->ee->tssi_data.offset[1]; in mt7601u_tssi_cal()
909 tssi_offset = dev->ee->tssi_data.offset[2]; in mt7601u_tssi_cal()
912 tssi_db -= dev->tssi_init_hvga_offset_db; in mt7601u_tssi_cal()
914 curr_pwr = tssi_db * dev->ee->tssi_data.slope + (tssi_offset << 9); in mt7601u_tssi_cal()
916 dev_dbg(dev->dev, "Power curr:%08x diff:%08x\n", curr_pwr, diff_pwr); in mt7601u_tssi_cal()
919 dev_err(dev->dev, "Error: TSSI upper saturation\n"); in mt7601u_tssi_cal()
923 dev_err(dev->dev, "Error: TSSI lower saturation\n"); in mt7601u_tssi_cal()
927 if ((dev->prev_pwr_diff ^ diff_pwr) < 0 && abs(diff_pwr) < 4096 && in mt7601u_tssi_cal()
928 (abs(diff_pwr) > abs(dev->prev_pwr_diff) || in mt7601u_tssi_cal()
929 (diff_pwr > 0 && diff_pwr == -dev->prev_pwr_diff))) in mt7601u_tssi_cal()
932 dev->prev_pwr_diff = diff_pwr; in mt7601u_tssi_cal()
937 dev_dbg(dev->dev, "final diff: %08x\n", diff_pwr); in mt7601u_tssi_cal()
939 val = mt7601u_rr(dev, MT_TX_ALC_CFG_1); in mt7601u_tssi_cal()
943 mt7601u_wr(dev, MT_TX_ALC_CFG_1, val); in mt7601u_tssi_cal()
945 return mt7601u_mcu_tssi_read_kick(dev, hvga); in mt7601u_tssi_cal()
948 static u8 mt7601u_agc_default(struct mt7601u_dev *dev) in mt7601u_agc_default() argument
950 return (dev->ee->lna_gain - 8) * 2 + 0x34; in mt7601u_agc_default()
953 static void mt7601u_agc_reset(struct mt7601u_dev *dev) in mt7601u_agc_reset() argument
955 u8 agc = mt7601u_agc_default(dev); in mt7601u_agc_reset()
957 mt7601u_bbp_wr(dev, 66, agc); in mt7601u_agc_reset()
960 void mt7601u_agc_save(struct mt7601u_dev *dev) in mt7601u_agc_save() argument
962 dev->agc_save = mt7601u_bbp_rr(dev, 66); in mt7601u_agc_save()
965 void mt7601u_agc_restore(struct mt7601u_dev *dev) in mt7601u_agc_restore() argument
967 mt7601u_bbp_wr(dev, 66, dev->agc_save); in mt7601u_agc_restore()
970 static void mt7601u_agc_tune(struct mt7601u_dev *dev) in mt7601u_agc_tune() argument
972 u8 val = mt7601u_agc_default(dev); in mt7601u_agc_tune()
975 if (test_bit(MT7601U_STATE_SCANNING, &dev->state)) in mt7601u_agc_tune()
982 spin_lock_bh(&dev->con_mon_lock); in mt7601u_agc_tune()
983 avg_rssi = ewma_rssi_read(&dev->avg_rssi); in mt7601u_agc_tune()
984 spin_unlock_bh(&dev->con_mon_lock); in mt7601u_agc_tune()
994 if (val != mt7601u_bbp_rr(dev, 66)) in mt7601u_agc_tune()
995 mt7601u_bbp_wr(dev, 66, val); in mt7601u_agc_tune()
1004 struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev, in mt7601u_phy_calibrate() local
1007 mt7601u_agc_tune(dev); in mt7601u_phy_calibrate()
1008 mt7601u_tssi_cal(dev); in mt7601u_phy_calibrate()
1010 if (!dev->ee->tssi_enabled) in mt7601u_phy_calibrate()
1011 dev->raw_temp = mt7601u_read_temp(dev); in mt7601u_phy_calibrate()
1012 mt7601u_temp_comp(dev, true); /* TODO: find right value for @on */ in mt7601u_phy_calibrate()
1014 ieee80211_queue_delayed_work(dev->hw, &dev->cal_work, in mt7601u_phy_calibrate()
1019 __mt7601u_phy_freq_cal(struct mt7601u_dev *dev, s8 last_offset, u8 phy_mode) in __mt7601u_phy_freq_cal() argument
1023 trace_freq_cal_offset(dev, phy_mode, last_offset); in __mt7601u_phy_freq_cal()
1049 dev->freq_cal.adjusting = true; in __mt7601u_phy_freq_cal()
1051 dev->freq_cal.adjusting = false; in __mt7601u_phy_freq_cal()
1053 if (!dev->freq_cal.adjusting) in __mt7601u_phy_freq_cal()
1057 if (dev->freq_cal.freq > 0) in __mt7601u_phy_freq_cal()
1058 dev->freq_cal.freq--; in __mt7601u_phy_freq_cal()
1060 dev->freq_cal.adjusting = false; in __mt7601u_phy_freq_cal()
1062 if (dev->freq_cal.freq < 0xbf) in __mt7601u_phy_freq_cal()
1063 dev->freq_cal.freq++; in __mt7601u_phy_freq_cal()
1065 dev->freq_cal.adjusting = false; in __mt7601u_phy_freq_cal()
1068 trace_freq_cal_adjust(dev, dev->freq_cal.freq); in __mt7601u_phy_freq_cal()
1069 mt7601u_rf_wr(dev, 0, 12, dev->freq_cal.freq); in __mt7601u_phy_freq_cal()
1070 mt7601u_vco_cal(dev); in __mt7601u_phy_freq_cal()
1072 return dev->freq_cal.adjusting ? MT_FREQ_CAL_ADJ_INTERVAL : in __mt7601u_phy_freq_cal()
1078 struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev, in mt7601u_phy_freq_cal() local
1084 spin_lock_bh(&dev->con_mon_lock); in mt7601u_phy_freq_cal()
1085 last_offset = dev->bcn_freq_off; in mt7601u_phy_freq_cal()
1086 phy_mode = dev->bcn_phy_mode; in mt7601u_phy_freq_cal()
1087 spin_unlock_bh(&dev->con_mon_lock); in mt7601u_phy_freq_cal()
1089 delay = __mt7601u_phy_freq_cal(dev, last_offset, phy_mode); in mt7601u_phy_freq_cal()
1090 ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work, delay); in mt7601u_phy_freq_cal()
1092 spin_lock_bh(&dev->con_mon_lock); in mt7601u_phy_freq_cal()
1093 dev->bcn_freq_off = MT_FREQ_OFFSET_INVALID; in mt7601u_phy_freq_cal()
1094 spin_unlock_bh(&dev->con_mon_lock); in mt7601u_phy_freq_cal()
1097 void mt7601u_phy_con_cal_onoff(struct mt7601u_dev *dev, in mt7601u_phy_con_cal_onoff() argument
1104 cancel_delayed_work_sync(&dev->freq_cal.work); in mt7601u_phy_con_cal_onoff()
1107 spin_lock_bh(&dev->con_mon_lock); in mt7601u_phy_con_cal_onoff()
1108 ether_addr_copy(dev->ap_bssid, info->bssid); in mt7601u_phy_con_cal_onoff()
1109 ewma_rssi_init(&dev->avg_rssi); in mt7601u_phy_con_cal_onoff()
1110 dev->bcn_freq_off = MT_FREQ_OFFSET_INVALID; in mt7601u_phy_con_cal_onoff()
1111 spin_unlock_bh(&dev->con_mon_lock); in mt7601u_phy_con_cal_onoff()
1113 dev->freq_cal.freq = dev->ee->rf_freq_off; in mt7601u_phy_con_cal_onoff()
1114 dev->freq_cal.enabled = vif->cfg.assoc; in mt7601u_phy_con_cal_onoff()
1115 dev->freq_cal.adjusting = false; in mt7601u_phy_con_cal_onoff()
1118 ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work, in mt7601u_phy_con_cal_onoff()
1122 static int mt7601u_init_cal(struct mt7601u_dev *dev) in mt7601u_init_cal() argument
1127 dev->raw_temp = mt7601u_read_bootup_temp(dev); in mt7601u_init_cal()
1128 dev->curr_temp = (dev->raw_temp - dev->ee->ref_temp) * in mt7601u_init_cal()
1130 dev->dpd_temp = dev->curr_temp; in mt7601u_init_cal()
1132 mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL); in mt7601u_init_cal()
1134 ret = mt7601u_mcu_calibrate(dev, MCU_CAL_R, 0); in mt7601u_init_cal()
1138 ret = mt7601u_rf_rr(dev, 0, 4); in mt7601u_init_cal()
1142 ret = mt7601u_rf_wr(dev, 0, 4, ret); in mt7601u_init_cal()
1147 ret = mt7601u_mcu_calibrate(dev, MCU_CAL_TXDCOC, 0); in mt7601u_init_cal()
1151 mt7601u_rxdc_cal(dev); in mt7601u_init_cal()
1153 ret = mt7601u_set_bw_filter(dev, true); in mt7601u_init_cal()
1156 ret = mt7601u_mcu_calibrate(dev, MCU_CAL_LOFT, 0); in mt7601u_init_cal()
1159 ret = mt7601u_mcu_calibrate(dev, MCU_CAL_TXIQ, 0); in mt7601u_init_cal()
1162 ret = mt7601u_mcu_calibrate(dev, MCU_CAL_RXIQ, 0); in mt7601u_init_cal()
1165 ret = mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->dpd_temp); in mt7601u_init_cal()
1169 mt7601u_rxdc_cal(dev); in mt7601u_init_cal()
1171 mt7601u_tssi_dc_gain_cal(dev); in mt7601u_init_cal()
1173 mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl); in mt7601u_init_cal()
1175 mt7601u_temp_comp(dev, true); in mt7601u_init_cal()
1180 int mt7601u_bbp_set_bw(struct mt7601u_dev *dev, int bw) in mt7601u_bbp_set_bw() argument
1184 if (bw == dev->bw) { in mt7601u_bbp_set_bw()
1186 mt7601u_bbp_rmc(dev, 4, 0x18, bw == MT_BW_20 ? 0 : 0x10); in mt7601u_bbp_set_bw()
1190 dev->bw = bw; in mt7601u_bbp_set_bw()
1193 old = mt7601u_rr(dev, MT_MAC_SYS_CTRL); in mt7601u_bbp_set_bw()
1195 mt7601u_wr(dev, MT_MAC_SYS_CTRL, val); in mt7601u_bbp_set_bw()
1196 mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX | MT_MAC_STATUS_RX, in mt7601u_bbp_set_bw()
1199 mt7601u_bbp_rmc(dev, 4, 0x18, bw == MT_BW_20 ? 0 : 0x10); in mt7601u_bbp_set_bw()
1201 mt7601u_wr(dev, MT_MAC_SYS_CTRL, old); in mt7601u_bbp_set_bw()
1203 return mt7601u_load_bbp_temp_table_bw(dev); in mt7601u_bbp_set_bw()
1211 void mt7601u_set_rx_path(struct mt7601u_dev *dev, u8 path) in mt7601u_set_rx_path() argument
1213 mt7601u_bbp_rmw(dev, 3, 0x18, path << 3); in mt7601u_set_rx_path()
1221 void mt7601u_set_tx_dac(struct mt7601u_dev *dev, u8 dac) in mt7601u_set_tx_dac() argument
1223 mt7601u_bbp_rmc(dev, 1, 0x18, dac << 3); in mt7601u_set_tx_dac()
1226 int mt7601u_phy_init(struct mt7601u_dev *dev) in mt7601u_phy_init() argument
1230 dev->rf_pa_mode[0] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG0); in mt7601u_phy_init()
1231 dev->rf_pa_mode[1] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG1); in mt7601u_phy_init()
1233 ret = mt7601u_rf_wr(dev, 0, 12, dev->ee->rf_freq_off); in mt7601u_phy_init()
1236 ret = mt7601u_write_reg_pairs(dev, 0, rf_central, in mt7601u_phy_init()
1240 ret = mt7601u_write_reg_pairs(dev, 0, rf_channel, in mt7601u_phy_init()
1244 ret = mt7601u_write_reg_pairs(dev, 0, rf_vga, ARRAY_SIZE(rf_vga)); in mt7601u_phy_init()
1248 ret = mt7601u_init_cal(dev); in mt7601u_phy_init()
1252 dev->prev_pwr_diff = 100; in mt7601u_phy_init()
1254 INIT_DELAYED_WORK(&dev->cal_work, mt7601u_phy_calibrate); in mt7601u_phy_init()
1255 INIT_DELAYED_WORK(&dev->freq_cal.work, mt7601u_phy_freq_cal); in mt7601u_phy_init()