Lines Matching refs:ah
31 static bool ar9002_hw_is_cal_supported(struct ath_hw *ah, in ar9002_hw_is_cal_supported() argument
36 switch (ah->supp_cals & cal_type) { in ar9002_hw_is_cal_supported()
50 static void ar9002_hw_setup_calibration(struct ath_hw *ah, in ar9002_hw_setup_calibration() argument
53 struct ath_common *common = ath9k_hw_common(ah); in ar9002_hw_setup_calibration()
55 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
61 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); in ar9002_hw_setup_calibration()
66 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); in ar9002_hw_setup_calibration()
70 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); in ar9002_hw_setup_calibration()
75 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
79 static bool ar9002_hw_per_calibration(struct ath_hw *ah, in ar9002_hw_per_calibration() argument
84 struct ath9k_hw_cal_data *caldata = ah->caldata; in ar9002_hw_per_calibration()
88 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & in ar9002_hw_per_calibration()
91 currCal->calData->calCollect(ah); in ar9002_hw_per_calibration()
92 ah->cal_samples++; in ar9002_hw_per_calibration()
94 if (ah->cal_samples >= in ar9002_hw_per_calibration()
102 currCal->calData->calPostProc(ah, numChains); in ar9002_hw_per_calibration()
107 ar9002_hw_setup_calibration(ah, currCal); in ar9002_hw_per_calibration()
109 } else if (time_after(jiffies, ah->cal_start_time + in ar9002_hw_per_calibration()
111 REG_CLR_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_per_calibration()
113 ath_dbg(ath9k_hw_common(ah), CALIBRATE, in ar9002_hw_per_calibration()
119 ath9k_hw_reset_calibration(ah, currCal); in ar9002_hw_per_calibration()
125 static void ar9002_hw_iqcal_collect(struct ath_hw *ah) in ar9002_hw_iqcal_collect() argument
130 ah->totalPowerMeasI[i] += in ar9002_hw_iqcal_collect()
131 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_iqcal_collect()
132 ah->totalPowerMeasQ[i] += in ar9002_hw_iqcal_collect()
133 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_iqcal_collect()
134 ah->totalIqCorrMeas[i] += in ar9002_hw_iqcal_collect()
135 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_iqcal_collect()
136 ath_dbg(ath9k_hw_common(ah), CALIBRATE, in ar9002_hw_iqcal_collect()
138 ah->cal_samples, i, ah->totalPowerMeasI[i], in ar9002_hw_iqcal_collect()
139 ah->totalPowerMeasQ[i], in ar9002_hw_iqcal_collect()
140 ah->totalIqCorrMeas[i]); in ar9002_hw_iqcal_collect()
144 static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah) in ar9002_hw_adc_gaincal_collect() argument
149 ah->totalAdcIOddPhase[i] += in ar9002_hw_adc_gaincal_collect()
150 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_gaincal_collect()
151 ah->totalAdcIEvenPhase[i] += in ar9002_hw_adc_gaincal_collect()
152 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_gaincal_collect()
153 ah->totalAdcQOddPhase[i] += in ar9002_hw_adc_gaincal_collect()
154 REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_adc_gaincal_collect()
155 ah->totalAdcQEvenPhase[i] += in ar9002_hw_adc_gaincal_collect()
156 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); in ar9002_hw_adc_gaincal_collect()
158 ath_dbg(ath9k_hw_common(ah), CALIBRATE, in ar9002_hw_adc_gaincal_collect()
160 ah->cal_samples, i, in ar9002_hw_adc_gaincal_collect()
161 ah->totalAdcIOddPhase[i], in ar9002_hw_adc_gaincal_collect()
162 ah->totalAdcIEvenPhase[i], in ar9002_hw_adc_gaincal_collect()
163 ah->totalAdcQOddPhase[i], in ar9002_hw_adc_gaincal_collect()
164 ah->totalAdcQEvenPhase[i]); in ar9002_hw_adc_gaincal_collect()
168 static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah) in ar9002_hw_adc_dccal_collect() argument
173 ah->totalAdcDcOffsetIOddPhase[i] += in ar9002_hw_adc_dccal_collect()
174 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_dccal_collect()
175 ah->totalAdcDcOffsetIEvenPhase[i] += in ar9002_hw_adc_dccal_collect()
176 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_dccal_collect()
177 ah->totalAdcDcOffsetQOddPhase[i] += in ar9002_hw_adc_dccal_collect()
178 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_adc_dccal_collect()
179 ah->totalAdcDcOffsetQEvenPhase[i] += in ar9002_hw_adc_dccal_collect()
180 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); in ar9002_hw_adc_dccal_collect()
182 ath_dbg(ath9k_hw_common(ah), CALIBRATE, in ar9002_hw_adc_dccal_collect()
184 ah->cal_samples, i, in ar9002_hw_adc_dccal_collect()
185 ah->totalAdcDcOffsetIOddPhase[i], in ar9002_hw_adc_dccal_collect()
186 ah->totalAdcDcOffsetIEvenPhase[i], in ar9002_hw_adc_dccal_collect()
187 ah->totalAdcDcOffsetQOddPhase[i], in ar9002_hw_adc_dccal_collect()
188 ah->totalAdcDcOffsetQEvenPhase[i]); in ar9002_hw_adc_dccal_collect()
192 static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) in ar9002_hw_iqcalibrate() argument
194 struct ath_common *common = ath9k_hw_common(ah); in ar9002_hw_iqcalibrate()
201 powerMeasI = ah->totalPowerMeasI[i]; in ar9002_hw_iqcalibrate()
202 powerMeasQ = ah->totalPowerMeasQ[i]; in ar9002_hw_iqcalibrate()
203 iqCorrMeas = ah->totalIqCorrMeas[i]; in ar9002_hw_iqcalibrate()
211 i, ah->totalIqCorrMeas[i]); in ar9002_hw_iqcalibrate()
253 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), in ar9002_hw_iqcalibrate()
256 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), in ar9002_hw_iqcalibrate()
265 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_iqcalibrate()
269 static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) in ar9002_hw_adc_gaincal_calibrate() argument
271 struct ath_common *common = ath9k_hw_common(ah); in ar9002_hw_adc_gaincal_calibrate()
276 iOddMeasOffset = ah->totalAdcIOddPhase[i]; in ar9002_hw_adc_gaincal_calibrate()
277 iEvenMeasOffset = ah->totalAdcIEvenPhase[i]; in ar9002_hw_adc_gaincal_calibrate()
278 qOddMeasOffset = ah->totalAdcQOddPhase[i]; in ar9002_hw_adc_gaincal_calibrate()
279 qEvenMeasOffset = ah->totalAdcQEvenPhase[i]; in ar9002_hw_adc_gaincal_calibrate()
308 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); in ar9002_hw_adc_gaincal_calibrate()
311 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); in ar9002_hw_adc_gaincal_calibrate()
318 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), in ar9002_hw_adc_gaincal_calibrate()
319 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) | in ar9002_hw_adc_gaincal_calibrate()
323 static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) in ar9002_hw_adc_dccal_calibrate() argument
325 struct ath_common *common = ath9k_hw_common(ah); in ar9002_hw_adc_dccal_calibrate()
329 ah->cal_list_curr->calData; in ar9002_hw_adc_dccal_calibrate()
334 iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i]; in ar9002_hw_adc_dccal_calibrate()
335 iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i]; in ar9002_hw_adc_dccal_calibrate()
336 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i]; in ar9002_hw_adc_dccal_calibrate()
337 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i]; in ar9002_hw_adc_dccal_calibrate()
363 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); in ar9002_hw_adc_dccal_calibrate()
366 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); in ar9002_hw_adc_dccal_calibrate()
372 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), in ar9002_hw_adc_dccal_calibrate()
373 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) | in ar9002_hw_adc_dccal_calibrate()
377 static void ar9287_hw_olc_temp_compensation(struct ath_hw *ah) in ar9287_hw_olc_temp_compensation() argument
382 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4); in ar9287_hw_olc_temp_compensation()
385 if (ah->initPDADC == 0 || currPDADC == 0) { in ar9287_hw_olc_temp_compensation()
393 slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE); in ar9287_hw_olc_temp_compensation()
398 delta = ((currPDADC - ah->initPDADC)*4) / slope; in ar9287_hw_olc_temp_compensation()
400 REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11, in ar9287_hw_olc_temp_compensation()
402 REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11, in ar9287_hw_olc_temp_compensation()
407 static void ar9280_hw_olc_temp_compensation(struct ath_hw *ah) in ar9280_hw_olc_temp_compensation() argument
412 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4); in ar9280_hw_olc_temp_compensation()
415 if (ah->initPDADC == 0 || currPDADC == 0) in ar9280_hw_olc_temp_compensation()
418 if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G)) in ar9280_hw_olc_temp_compensation()
419 delta = (currPDADC - ah->initPDADC + 4) / 8; in ar9280_hw_olc_temp_compensation()
421 delta = (currPDADC - ah->initPDADC + 5) / 10; in ar9280_hw_olc_temp_compensation()
423 if (delta != ah->PDADCdelta) { in ar9280_hw_olc_temp_compensation()
424 ah->PDADCdelta = delta; in ar9280_hw_olc_temp_compensation()
426 regval = ah->originalGain[i] - delta; in ar9280_hw_olc_temp_compensation()
430 REG_RMW_FIELD(ah, in ar9280_hw_olc_temp_compensation()
437 static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset) in ar9271_hw_pa_cal() argument
452 REG_READ_ARRAY(ah, regList, ARRAY_SIZE(regList)); in ar9271_hw_pa_cal()
454 ENABLE_REG_RMW_BUFFER(ah); in ar9271_hw_pa_cal()
456 REG_CLR_BIT(ah, AR9285_AN_RF2G6, 1 << 0); in ar9271_hw_pa_cal()
458 REG_SET_BIT(ah, 0x9808, 1 << 27); in ar9271_hw_pa_cal()
460 REG_SET_BIT(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC); in ar9271_hw_pa_cal()
462 REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1); in ar9271_hw_pa_cal()
464 REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I); in ar9271_hw_pa_cal()
466 REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF); in ar9271_hw_pa_cal()
468 REG_CLR_BIT(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL); in ar9271_hw_pa_cal()
470 REG_CLR_BIT(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB); in ar9271_hw_pa_cal()
472 REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL); in ar9271_hw_pa_cal()
474 REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1); in ar9271_hw_pa_cal()
476 REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2); in ar9271_hw_pa_cal()
478 REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT); in ar9271_hw_pa_cal()
480 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7); in ar9271_hw_pa_cal()
485 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0); in ar9271_hw_pa_cal()
487 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff); in ar9271_hw_pa_cal()
488 REG_RMW_BUFFER_FLUSH(ah); in ar9271_hw_pa_cal()
494 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0); in ar9271_hw_pa_cal()
496 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0); in ar9271_hw_pa_cal()
500 regVal = REG_READ(ah, AR9285_AN_RF2G6); in ar9271_hw_pa_cal()
502 REG_WRITE(ah, AR9285_AN_RF2G6, regVal); in ar9271_hw_pa_cal()
506 regVal |= (MS(REG_READ(ah, AR9285_AN_RF2G9), in ar9271_hw_pa_cal()
509 REG_WRITE(ah, AR9285_AN_RF2G6, regVal); in ar9271_hw_pa_cal()
515 if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) { in ar9271_hw_pa_cal()
516 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT) in ar9271_hw_pa_cal()
517 ah->pacal_info.max_skipcount = in ar9271_hw_pa_cal()
518 2 * ah->pacal_info.max_skipcount; in ar9271_hw_pa_cal()
519 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount; in ar9271_hw_pa_cal()
521 ah->pacal_info.max_skipcount = 1; in ar9271_hw_pa_cal()
522 ah->pacal_info.skipcount = 0; in ar9271_hw_pa_cal()
523 ah->pacal_info.prev_offset = regVal; in ar9271_hw_pa_cal()
527 ENABLE_REG_RMW_BUFFER(ah); in ar9271_hw_pa_cal()
529 REG_SET_BIT(ah, AR9285_AN_RF2G6, 1 << 0); in ar9271_hw_pa_cal()
531 REG_CLR_BIT(ah, 0x9808, 1 << 27); in ar9271_hw_pa_cal()
532 REG_RMW_BUFFER_FLUSH(ah); in ar9271_hw_pa_cal()
534 ENABLE_REGWRITE_BUFFER(ah); in ar9271_hw_pa_cal()
536 REG_WRITE(ah, regList[i][0], regList[i][1]); in ar9271_hw_pa_cal()
538 REGWRITE_BUFFER_FLUSH(ah); in ar9271_hw_pa_cal()
541 static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset) in ar9285_hw_pa_cal() argument
543 struct ath_common *common = ath9k_hw_common(ah); in ar9285_hw_pa_cal()
560 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == in ar9285_hw_pa_cal()
565 regList[i][1] = REG_READ(ah, regList[i][0]); in ar9285_hw_pa_cal()
567 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
569 REG_WRITE(ah, 0x7834, regVal); in ar9285_hw_pa_cal()
570 regVal = REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
572 REG_WRITE(ah, 0x9808, regVal); in ar9285_hw_pa_cal()
574 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1); in ar9285_hw_pa_cal()
575 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1); in ar9285_hw_pa_cal()
576 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1); in ar9285_hw_pa_cal()
577 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1); in ar9285_hw_pa_cal()
578 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0); in ar9285_hw_pa_cal()
579 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0); in ar9285_hw_pa_cal()
580 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0); in ar9285_hw_pa_cal()
581 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0); in ar9285_hw_pa_cal()
582 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0); in ar9285_hw_pa_cal()
583 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0); in ar9285_hw_pa_cal()
584 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7); in ar9285_hw_pa_cal()
585 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0); in ar9285_hw_pa_cal()
586 ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP); in ar9285_hw_pa_cal()
587 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf); in ar9285_hw_pa_cal()
589 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0); in ar9285_hw_pa_cal()
591 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0); in ar9285_hw_pa_cal()
592 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0); in ar9285_hw_pa_cal()
595 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
597 REG_WRITE(ah, 0x7834, regVal); in ar9285_hw_pa_cal()
599 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
601 reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9); in ar9285_hw_pa_cal()
603 REG_WRITE(ah, 0x7834, regVal); in ar9285_hw_pa_cal()
606 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1); in ar9285_hw_pa_cal()
608 reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9); in ar9285_hw_pa_cal()
609 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field); in ar9285_hw_pa_cal()
610 offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS); in ar9285_hw_pa_cal()
611 offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP); in ar9285_hw_pa_cal()
618 if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) { in ar9285_hw_pa_cal()
619 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT) in ar9285_hw_pa_cal()
620 ah->pacal_info.max_skipcount = in ar9285_hw_pa_cal()
621 2 * ah->pacal_info.max_skipcount; in ar9285_hw_pa_cal()
622 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount; in ar9285_hw_pa_cal()
624 ah->pacal_info.max_skipcount = 1; in ar9285_hw_pa_cal()
625 ah->pacal_info.skipcount = 0; in ar9285_hw_pa_cal()
626 ah->pacal_info.prev_offset = offset; in ar9285_hw_pa_cal()
629 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1); in ar9285_hw_pa_cal()
630 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0); in ar9285_hw_pa_cal()
632 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
634 REG_WRITE(ah, 0x7834, regVal); in ar9285_hw_pa_cal()
635 regVal = REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
637 REG_WRITE(ah, 0x9808, regVal); in ar9285_hw_pa_cal()
640 REG_WRITE(ah, regList[i][0], regList[i][1]); in ar9285_hw_pa_cal()
642 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org); in ar9285_hw_pa_cal()
645 static void ar9002_hw_pa_cal(struct ath_hw *ah, bool is_reset) in ar9002_hw_pa_cal() argument
647 if (AR_SREV_9271(ah)) { in ar9002_hw_pa_cal()
648 if (is_reset || !ah->pacal_info.skipcount) in ar9002_hw_pa_cal()
649 ar9271_hw_pa_cal(ah, is_reset); in ar9002_hw_pa_cal()
651 ah->pacal_info.skipcount--; in ar9002_hw_pa_cal()
652 } else if (AR_SREV_9285_12_OR_LATER(ah)) { in ar9002_hw_pa_cal()
653 if (is_reset || !ah->pacal_info.skipcount) in ar9002_hw_pa_cal()
654 ar9285_hw_pa_cal(ah, is_reset); in ar9002_hw_pa_cal()
656 ah->pacal_info.skipcount--; in ar9002_hw_pa_cal()
660 static void ar9002_hw_olc_temp_compensation(struct ath_hw *ah) in ar9002_hw_olc_temp_compensation() argument
662 if (OLC_FOR_AR9287_10_LATER(ah)) in ar9002_hw_olc_temp_compensation()
663 ar9287_hw_olc_temp_compensation(ah); in ar9002_hw_olc_temp_compensation()
664 else if (OLC_FOR_AR9280_20_LATER(ah)) in ar9002_hw_olc_temp_compensation()
665 ar9280_hw_olc_temp_compensation(ah); in ar9002_hw_olc_temp_compensation()
668 static int ar9002_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, in ar9002_hw_calibrate() argument
671 struct ath9k_cal_list *currCal = ah->cal_list_curr; in ar9002_hw_calibrate()
675 nfcal = !!(REG_READ(ah, AR_PHY_AGC_CONTROL(ah)) & AR_PHY_AGC_CONTROL_NF); in ar9002_hw_calibrate()
676 if (ah->caldata) { in ar9002_hw_calibrate()
677 nfcal_pending = test_bit(NFCAL_PENDING, &ah->caldata->cal_flags); in ar9002_hw_calibrate()
679 set_bit(LONGCAL_PENDING, &ah->caldata->cal_flags); in ar9002_hw_calibrate()
680 else if (test_bit(LONGCAL_PENDING, &ah->caldata->cal_flags)) in ar9002_hw_calibrate()
689 if (!ar9002_hw_per_calibration(ah, chan, rxchainmask, currCal)) in ar9002_hw_calibrate()
693 for (currCal = currCal->calNext; currCal != ah->cal_list_curr; in ar9002_hw_calibrate()
700 ah->cal_list_curr = currCal; in ar9002_hw_calibrate()
703 ah->cal_list_curr = ah->cal_list; in ar9002_hw_calibrate()
709 ath9k_hw_reset_calibration(ah, currCal); in ar9002_hw_calibrate()
720 if (ath9k_hw_getnf(ah, chan)) { in ar9002_hw_calibrate()
727 ret = ath9k_hw_loadnf(ah, ah->curchan); in ar9002_hw_calibrate()
733 if (ah->caldata) in ar9002_hw_calibrate()
735 &ah->caldata->cal_flags); in ar9002_hw_calibrate()
736 ath9k_hw_start_nfcal(ah, false); in ar9002_hw_calibrate()
738 ar9002_hw_pa_cal(ah, false); in ar9002_hw_calibrate()
739 ar9002_hw_olc_temp_compensation(ah); in ar9002_hw_calibrate()
747 static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan) in ar9285_hw_cl_cal() argument
749 struct ath_common *common = ath9k_hw_common(ah); in ar9285_hw_cl_cal()
751 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal()
753 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); in ar9285_hw_cl_cal()
754 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); in ar9285_hw_cl_cal()
755 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ar9285_hw_cl_cal()
757 REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); in ar9285_hw_cl_cal()
758 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal()
759 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL(ah), in ar9285_hw_cl_cal()
766 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); in ar9285_hw_cl_cal()
767 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); in ar9285_hw_cl_cal()
768 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal()
770 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); in ar9285_hw_cl_cal()
771 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9285_hw_cl_cal()
772 REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); in ar9285_hw_cl_cal()
773 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal()
774 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_CAL, in ar9285_hw_cl_cal()
782 REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); in ar9285_hw_cl_cal()
783 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal()
784 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9285_hw_cl_cal()
789 static bool ar9285_hw_clc(struct ath_hw *ah, struct ath9k_channel *chan) in ar9285_hw_clc() argument
801 if (!(ar9285_hw_cl_cal(ah, chan))) in ar9285_hw_clc()
804 txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7), in ar9285_hw_clc()
808 clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) & in ar9285_hw_clc()
817 reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2))) in ar9285_hw_clc()
819 reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2))) in ar9285_hw_clc()
829 reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5); in ar9285_hw_clc()
830 if (AR_SREV_9285E_20(ah)) { in ar9285_hw_clc()
831 REG_WRITE(ah, AR9285_RF2G5, in ar9285_hw_clc()
835 REG_WRITE(ah, AR9285_RF2G5, in ar9285_hw_clc()
839 retv = ar9285_hw_cl_cal(ah, chan); in ar9285_hw_clc()
840 REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org); in ar9285_hw_clc()
845 static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) in ar9002_hw_init_cal() argument
847 struct ath_common *common = ath9k_hw_common(ah); in ar9002_hw_init_cal()
849 if (AR_SREV_9271(ah)) { in ar9002_hw_init_cal()
850 if (!ar9285_hw_cl_cal(ah, chan)) in ar9002_hw_init_cal()
852 } else if (AR_SREV_9285(ah) && AR_SREV_9285_12_OR_LATER(ah)) { in ar9002_hw_init_cal()
853 if (!ar9285_hw_clc(ah, chan)) in ar9002_hw_init_cal()
856 if (AR_SREV_9280_20_OR_LATER(ah)) { in ar9002_hw_init_cal()
857 if (!AR_SREV_9287_11_OR_LATER(ah)) in ar9002_hw_init_cal()
858 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, in ar9002_hw_init_cal()
860 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ar9002_hw_init_cal()
865 REG_WRITE(ah, AR_PHY_AGC_CONTROL(ah), in ar9002_hw_init_cal()
866 REG_READ(ah, AR_PHY_AGC_CONTROL(ah)) | in ar9002_hw_init_cal()
870 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL(ah), in ar9002_hw_init_cal()
879 if (AR_SREV_9280_20_OR_LATER(ah)) { in ar9002_hw_init_cal()
880 if (!AR_SREV_9287_11_OR_LATER(ah)) in ar9002_hw_init_cal()
881 REG_SET_BIT(ah, AR_PHY_ADC_CTL, in ar9002_hw_init_cal()
883 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ar9002_hw_init_cal()
889 ar9002_hw_pa_cal(ah, true); in ar9002_hw_init_cal()
890 ath9k_hw_loadnf(ah, chan); in ar9002_hw_init_cal()
891 ath9k_hw_start_nfcal(ah, true); in ar9002_hw_init_cal()
893 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL; in ar9002_hw_init_cal()
896 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) { in ar9002_hw_init_cal()
897 ah->supp_cals = IQ_MISMATCH_CAL; in ar9002_hw_init_cal()
899 if (AR_SREV_9160_10_OR_LATER(ah)) in ar9002_hw_init_cal()
900 ah->supp_cals |= ADC_GAIN_CAL | ADC_DC_CAL; in ar9002_hw_init_cal()
902 if (AR_SREV_9287(ah)) in ar9002_hw_init_cal()
903 ah->supp_cals &= ~ADC_GAIN_CAL; in ar9002_hw_init_cal()
905 if (ar9002_hw_is_cal_supported(ah, chan, ADC_GAIN_CAL)) { in ar9002_hw_init_cal()
906 INIT_CAL(&ah->adcgain_caldata); in ar9002_hw_init_cal()
907 INSERT_CAL(ah, &ah->adcgain_caldata); in ar9002_hw_init_cal()
912 if (ar9002_hw_is_cal_supported(ah, chan, ADC_DC_CAL)) { in ar9002_hw_init_cal()
913 INIT_CAL(&ah->adcdc_caldata); in ar9002_hw_init_cal()
914 INSERT_CAL(ah, &ah->adcdc_caldata); in ar9002_hw_init_cal()
919 if (ar9002_hw_is_cal_supported(ah, chan, IQ_MISMATCH_CAL)) { in ar9002_hw_init_cal()
920 INIT_CAL(&ah->iq_caldata); in ar9002_hw_init_cal()
921 INSERT_CAL(ah, &ah->iq_caldata); in ar9002_hw_init_cal()
925 ah->cal_list_curr = ah->cal_list; in ar9002_hw_init_cal()
927 if (ah->cal_list_curr) in ar9002_hw_init_cal()
928 ath9k_hw_reset_calibration(ah, ah->cal_list_curr); in ar9002_hw_init_cal()
931 if (ah->caldata) in ar9002_hw_init_cal()
932 ah->caldata->CalValid = 0; in ar9002_hw_init_cal()
980 static void ar9002_hw_init_cal_settings(struct ath_hw *ah) in ar9002_hw_init_cal_settings() argument
982 if (AR_SREV_9100(ah)) { in ar9002_hw_init_cal_settings()
983 ah->iq_caldata.calData = &iq_cal_multi_sample; in ar9002_hw_init_cal_settings()
984 ah->supp_cals = IQ_MISMATCH_CAL; in ar9002_hw_init_cal_settings()
988 if (AR_SREV_9160_10_OR_LATER(ah)) { in ar9002_hw_init_cal_settings()
989 if (AR_SREV_9280_20_OR_LATER(ah)) { in ar9002_hw_init_cal_settings()
990 ah->iq_caldata.calData = &iq_cal_single_sample; in ar9002_hw_init_cal_settings()
991 ah->adcgain_caldata.calData = in ar9002_hw_init_cal_settings()
993 ah->adcdc_caldata.calData = in ar9002_hw_init_cal_settings()
996 ah->iq_caldata.calData = &iq_cal_multi_sample; in ar9002_hw_init_cal_settings()
997 ah->adcgain_caldata.calData = in ar9002_hw_init_cal_settings()
999 ah->adcdc_caldata.calData = in ar9002_hw_init_cal_settings()
1002 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; in ar9002_hw_init_cal_settings()
1004 if (AR_SREV_9287(ah)) in ar9002_hw_init_cal_settings()
1005 ah->supp_cals &= ~ADC_GAIN_CAL; in ar9002_hw_init_cal_settings()
1009 void ar9002_hw_attach_calib_ops(struct ath_hw *ah) in ar9002_hw_attach_calib_ops() argument
1011 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); in ar9002_hw_attach_calib_ops()
1012 struct ath_hw_ops *ops = ath9k_hw_ops(ah); in ar9002_hw_attach_calib_ops()