Lines Matching refs:ah
85 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum nl80211_band band) in ath5k_hw_radio_revision() argument
96 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); in ath5k_hw_radio_revision()
99 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); in ath5k_hw_radio_revision()
108 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); in ath5k_hw_radio_revision()
111 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); in ath5k_hw_radio_revision()
113 if (ah->ah_version == AR5K_AR5210) { in ath5k_hw_radio_revision()
114 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(256)) >> 28) & 0xf; in ath5k_hw_radio_revision()
117 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; in ath5k_hw_radio_revision()
123 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); in ath5k_hw_radio_revision()
137 ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel) in ath5k_channel_ok() argument
143 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && in ath5k_channel_ok()
144 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) in ath5k_channel_ok()
147 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && in ath5k_channel_ok()
148 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) in ath5k_channel_ok()
160 ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, in ath5k_hw_chan_has_spur_noise() argument
165 if ((ah->ah_radio == AR5K_RF5112) || in ath5k_hw_chan_has_spur_noise()
166 (ah->ah_radio == AR5K_RF5413) || in ath5k_hw_chan_has_spur_noise()
167 (ah->ah_radio == AR5K_RF2413) || in ath5k_hw_chan_has_spur_noise()
168 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) in ath5k_hw_chan_has_spur_noise()
194 ath5k_hw_rfb_op(struct ath5k_hw *ah, const struct ath5k_rf_reg *rf_regs, in ath5k_hw_rfb_op() argument
206 rfb = ah->ah_rf_banks; in ath5k_hw_rfb_op()
208 for (i = 0; i < ah->ah_rf_regs_count; i++) { in ath5k_hw_rfb_op()
230 offset = ah->ah_offset[bank]; in ath5k_hw_rfb_op()
286 ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, in ath5k_hw_write_ofdm_timings() argument
293 BUG_ON(!(ah->ah_version == AR5K_AR5212) || in ath5k_hw_write_ofdm_timings()
300 switch (ah->ah_bwmode) { in ath5k_hw_write_ofdm_timings()
338 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, in ath5k_hw_write_ofdm_timings()
340 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, in ath5k_hw_write_ofdm_timings()
350 int ath5k_hw_phy_disable(struct ath5k_hw *ah) in ath5k_hw_phy_disable() argument
353 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); in ath5k_hw_phy_disable()
364 ath5k_hw_wait_for_synth(struct ath5k_hw *ah, in ath5k_hw_wait_for_synth() argument
371 if (ah->ah_version != AR5K_AR5210) { in ath5k_hw_wait_for_synth()
373 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & in ath5k_hw_wait_for_synth()
377 if (ah->ah_bwmode == AR5K_BWMODE_10MHZ) in ath5k_hw_wait_for_synth()
379 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ) in ath5k_hw_wait_for_synth()
421 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) in ath5k_hw_rfgain_opt_init() argument
424 switch (ah->ah_radio) { in ath5k_hw_rfgain_opt_init()
426 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; in ath5k_hw_rfgain_opt_init()
427 ah->ah_gain.g_low = 20; in ath5k_hw_rfgain_opt_init()
428 ah->ah_gain.g_high = 35; in ath5k_hw_rfgain_opt_init()
429 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; in ath5k_hw_rfgain_opt_init()
432 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; in ath5k_hw_rfgain_opt_init()
433 ah->ah_gain.g_low = 20; in ath5k_hw_rfgain_opt_init()
434 ah->ah_gain.g_high = 85; in ath5k_hw_rfgain_opt_init()
435 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; in ath5k_hw_rfgain_opt_init()
458 ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) in ath5k_hw_request_rfgain_probe() argument
463 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE) in ath5k_hw_request_rfgain_probe()
468 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4, in ath5k_hw_request_rfgain_probe()
472 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED; in ath5k_hw_request_rfgain_probe()
484 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) in ath5k_hw_rf_gainf_corr() argument
492 if ((ah->ah_radio != AR5K_RF5112) || in ath5k_hw_rf_gainf_corr()
493 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A)) in ath5k_hw_rf_gainf_corr()
498 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); in ath5k_hw_rf_gainf_corr()
500 g_step = &go->go_step[ah->ah_gain.g_step_idx]; in ath5k_hw_rf_gainf_corr()
502 if (ah->ah_rf_banks == NULL) in ath5k_hw_rf_gainf_corr()
505 ah->ah_gain.g_f_corr = 0; in ath5k_hw_rf_gainf_corr()
508 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1) in ath5k_hw_rf_gainf_corr()
512 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false); in ath5k_hw_rf_gainf_corr()
519 ah->ah_gain.g_f_corr = step * 2; in ath5k_hw_rf_gainf_corr()
522 ah->ah_gain.g_f_corr = (step - 5) * 2; in ath5k_hw_rf_gainf_corr()
525 ah->ah_gain.g_f_corr = step; in ath5k_hw_rf_gainf_corr()
528 ah->ah_gain.g_f_corr = 0; in ath5k_hw_rf_gainf_corr()
532 return ah->ah_gain.g_f_corr; in ath5k_hw_rf_gainf_corr()
547 ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) in ath5k_hw_rf_check_gainf_readback() argument
552 if (ah->ah_rf_banks == NULL) in ath5k_hw_rf_check_gainf_readback()
555 if (ah->ah_radio == AR5K_RF5111) { in ath5k_hw_rf_check_gainf_readback()
558 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); in ath5k_hw_rf_check_gainf_readback()
560 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP, in ath5k_hw_rf_check_gainf_readback()
568 ah->ah_gain.g_high = level[3] - in ath5k_hw_rf_check_gainf_readback()
570 ah->ah_gain.g_low = level[0] + in ath5k_hw_rf_check_gainf_readback()
575 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); in ath5k_hw_rf_check_gainf_readback()
577 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, in ath5k_hw_rf_check_gainf_readback()
586 ah->ah_gain.g_high = 55; in ath5k_hw_rf_check_gainf_readback()
590 return (ah->ah_gain.g_current >= level[0] && in ath5k_hw_rf_check_gainf_readback()
591 ah->ah_gain.g_current <= level[1]) || in ath5k_hw_rf_check_gainf_readback()
592 (ah->ah_gain.g_current >= level[2] && in ath5k_hw_rf_check_gainf_readback()
593 ah->ah_gain.g_current <= level[3]); in ath5k_hw_rf_check_gainf_readback()
604 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) in ath5k_hw_rf_gainf_adjust() argument
610 switch (ah->ah_radio) { in ath5k_hw_rf_gainf_adjust()
621 g_step = &go->go_step[ah->ah_gain.g_step_idx]; in ath5k_hw_rf_gainf_adjust()
623 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { in ath5k_hw_rf_gainf_adjust()
626 if (ah->ah_gain.g_step_idx == 0) in ath5k_hw_rf_gainf_adjust()
629 for (ah->ah_gain.g_target = ah->ah_gain.g_current; in ath5k_hw_rf_gainf_adjust()
630 ah->ah_gain.g_target >= ah->ah_gain.g_high && in ath5k_hw_rf_gainf_adjust()
631 ah->ah_gain.g_step_idx > 0; in ath5k_hw_rf_gainf_adjust()
632 g_step = &go->go_step[ah->ah_gain.g_step_idx]) in ath5k_hw_rf_gainf_adjust()
633 ah->ah_gain.g_target -= 2 * in ath5k_hw_rf_gainf_adjust()
634 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain - in ath5k_hw_rf_gainf_adjust()
641 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { in ath5k_hw_rf_gainf_adjust()
644 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1)) in ath5k_hw_rf_gainf_adjust()
647 for (ah->ah_gain.g_target = ah->ah_gain.g_current; in ath5k_hw_rf_gainf_adjust()
648 ah->ah_gain.g_target <= ah->ah_gain.g_low && in ath5k_hw_rf_gainf_adjust()
649 ah->ah_gain.g_step_idx < go->go_steps_count - 1; in ath5k_hw_rf_gainf_adjust()
650 g_step = &go->go_step[ah->ah_gain.g_step_idx]) in ath5k_hw_rf_gainf_adjust()
651 ah->ah_gain.g_target -= 2 * in ath5k_hw_rf_gainf_adjust()
652 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - in ath5k_hw_rf_gainf_adjust()
660 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_rf_gainf_adjust()
662 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, in ath5k_hw_rf_gainf_adjust()
663 ah->ah_gain.g_target); in ath5k_hw_rf_gainf_adjust()
679 ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) in ath5k_hw_gainf_calibrate() argument
682 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_hw_gainf_calibrate()
684 if (ah->ah_rf_banks == NULL || in ath5k_hw_gainf_calibrate()
685 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) in ath5k_hw_gainf_calibrate()
690 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) in ath5k_hw_gainf_calibrate()
695 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); in ath5k_hw_gainf_calibrate()
699 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; in ath5k_hw_gainf_calibrate()
705 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) in ath5k_hw_gainf_calibrate()
706 ah->ah_gain.g_current += in ath5k_hw_gainf_calibrate()
709 ah->ah_gain.g_current += in ath5k_hw_gainf_calibrate()
715 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { in ath5k_hw_gainf_calibrate()
716 ath5k_hw_rf_gainf_corr(ah); in ath5k_hw_gainf_calibrate()
717 ah->ah_gain.g_current = in ath5k_hw_gainf_calibrate()
718 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? in ath5k_hw_gainf_calibrate()
719 (ah->ah_gain.g_current - ah->ah_gain.g_f_corr) : in ath5k_hw_gainf_calibrate()
726 if (ath5k_hw_rf_check_gainf_readback(ah) && in ath5k_hw_gainf_calibrate()
727 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && in ath5k_hw_gainf_calibrate()
728 ath5k_hw_rf_gainf_adjust(ah)) { in ath5k_hw_gainf_calibrate()
729 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; in ath5k_hw_gainf_calibrate()
731 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; in ath5k_hw_gainf_calibrate()
736 return ah->ah_gain.g_state; in ath5k_hw_gainf_calibrate()
750 ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum nl80211_band band) in ath5k_hw_rfgain_init() argument
755 switch (ah->ah_radio) { in ath5k_hw_rfgain_init()
789 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[index], in ath5k_hw_rfgain_init()
811 ath5k_hw_rfregs_init(struct ath5k_hw *ah, in ath5k_hw_rfregs_init() argument
819 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_hw_rfregs_init()
824 switch (ah->ah_radio) { in ath5k_hw_rfregs_init()
827 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); in ath5k_hw_rfregs_init()
829 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); in ath5k_hw_rfregs_init()
833 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { in ath5k_hw_rfregs_init()
835 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); in ath5k_hw_rfregs_init()
837 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); in ath5k_hw_rfregs_init()
840 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); in ath5k_hw_rfregs_init()
842 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); in ath5k_hw_rfregs_init()
848 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); in ath5k_hw_rfregs_init()
850 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); in ath5k_hw_rfregs_init()
854 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); in ath5k_hw_rfregs_init()
856 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); in ath5k_hw_rfregs_init()
860 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); in ath5k_hw_rfregs_init()
862 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); in ath5k_hw_rfregs_init()
866 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); in ath5k_hw_rfregs_init()
868 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); in ath5k_hw_rfregs_init()
872 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); in ath5k_hw_rfregs_init()
873 if (ah->ah_mac_srev < AR5K_SREV_AR2417) { in ath5k_hw_rfregs_init()
875 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); in ath5k_hw_rfregs_init()
878 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); in ath5k_hw_rfregs_init()
888 if (ah->ah_rf_banks == NULL) { in ath5k_hw_rfregs_init()
889 ah->ah_rf_banks = kmalloc_array(ah->ah_rf_banks_size, in ath5k_hw_rfregs_init()
892 if (ah->ah_rf_banks == NULL) { in ath5k_hw_rfregs_init()
893 ATH5K_ERR(ah, "out of memory\n"); in ath5k_hw_rfregs_init()
899 rfb = ah->ah_rf_banks; in ath5k_hw_rfregs_init()
901 for (i = 0; i < ah->ah_rf_banks_size; i++) { in ath5k_hw_rfregs_init()
903 ATH5K_ERR(ah, "invalid bank\n"); in ath5k_hw_rfregs_init()
910 ah->ah_offset[bank] = i; in ath5k_hw_rfregs_init()
931 if ((ah->ah_radio == AR5K_RF5111) || in ath5k_hw_rfregs_init()
932 (ah->ah_radio == AR5K_RF5112)) in ath5k_hw_rfregs_init()
937 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], in ath5k_hw_rfregs_init()
940 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], in ath5k_hw_rfregs_init()
945 (ah->ah_radio == AR5K_RF5111)) { in ath5k_hw_rfregs_init()
958 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], in ath5k_hw_rfregs_init()
961 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], in ath5k_hw_rfregs_init()
965 g_step = &go->go_step[ah->ah_gain.g_step_idx]; in ath5k_hw_rfregs_init()
968 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) && in ath5k_hw_rfregs_init()
969 (ah->ah_radio != AR5K_RF5413)) in ath5k_hw_rfregs_init()
970 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_TURBO, false); in ath5k_hw_rfregs_init()
973 if (ah->ah_radio == AR5K_RF5111) { in ath5k_hw_rfregs_init()
978 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, in ath5k_hw_rfregs_init()
982 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], in ath5k_hw_rfregs_init()
985 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], in ath5k_hw_rfregs_init()
988 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], in ath5k_hw_rfregs_init()
993 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; in ath5k_hw_rfregs_init()
999 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], in ath5k_hw_rfregs_init()
1002 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], in ath5k_hw_rfregs_init()
1005 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], in ath5k_hw_rfregs_init()
1008 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], in ath5k_hw_rfregs_init()
1012 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || in ath5k_hw_rfregs_init()
1013 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { in ath5k_hw_rfregs_init()
1016 ath5k_hw_rfb_op(ah, rf_regs, 0x1f, in ath5k_hw_rfregs_init()
1019 wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? in ath5k_hw_rfregs_init()
1022 ath5k_hw_rfb_op(ah, rf_regs, wait_i, in ath5k_hw_rfregs_init()
1024 ath5k_hw_rfb_op(ah, rf_regs, 3, in ath5k_hw_rfregs_init()
1030 if (ah->ah_radio == AR5K_RF5112) { in ath5k_hw_rfregs_init()
1035 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], in ath5k_hw_rfregs_init()
1038 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], in ath5k_hw_rfregs_init()
1041 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], in ath5k_hw_rfregs_init()
1044 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], in ath5k_hw_rfregs_init()
1047 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], in ath5k_hw_rfregs_init()
1050 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], in ath5k_hw_rfregs_init()
1053 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], in ath5k_hw_rfregs_init()
1058 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; in ath5k_hw_rfregs_init()
1063 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], in ath5k_hw_rfregs_init()
1066 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { in ath5k_hw_rfregs_init()
1068 ath5k_hw_rfb_op(ah, rf_regs, in ath5k_hw_rfregs_init()
1075 ath5k_hw_rfb_op(ah, rf_regs, in ath5k_hw_rfregs_init()
1078 ath5k_hw_rfb_op(ah, rf_regs, in ath5k_hw_rfregs_init()
1082 ath5k_hw_rfb_op(ah, rf_regs, in ath5k_hw_rfregs_init()
1085 ath5k_hw_rfb_op(ah, rf_regs, in ath5k_hw_rfregs_init()
1091 if (ah->ah_radio == AR5K_RF5112 && in ath5k_hw_rfregs_init()
1092 (ah->ah_radio_5ghz_revision & AR5K_SREV_REV) > 0) { in ath5k_hw_rfregs_init()
1093 ath5k_hw_rfb_op(ah, rf_regs, 2, in ath5k_hw_rfregs_init()
1096 ath5k_hw_rfb_op(ah, rf_regs, 2, in ath5k_hw_rfregs_init()
1099 ath5k_hw_rfb_op(ah, rf_regs, 2, in ath5k_hw_rfregs_init()
1102 ath5k_hw_rfb_op(ah, rf_regs, 2, in ath5k_hw_rfregs_init()
1107 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { in ath5k_hw_rfregs_init()
1108 ath5k_hw_rfb_op(ah, rf_regs, 1, in ath5k_hw_rfregs_init()
1111 ath5k_hw_rfb_op(ah, rf_regs, 1, in ath5k_hw_rfregs_init()
1114 ath5k_hw_rfb_op(ah, rf_regs, 1, in ath5k_hw_rfregs_init()
1117 ath5k_hw_rfb_op(ah, rf_regs, 1, in ath5k_hw_rfregs_init()
1120 ath5k_hw_rfb_op(ah, rf_regs, 1, in ath5k_hw_rfregs_init()
1125 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], in ath5k_hw_rfregs_init()
1129 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || in ath5k_hw_rfregs_init()
1130 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { in ath5k_hw_rfregs_init()
1133 pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? in ath5k_hw_rfregs_init()
1136 ath5k_hw_rfb_op(ah, rf_regs, pd_delay, in ath5k_hw_rfregs_init()
1138 ath5k_hw_rfb_op(ah, rf_regs, 0xf, in ath5k_hw_rfregs_init()
1144 if (ah->ah_radio == AR5K_RF5413 && in ath5k_hw_rfregs_init()
1147 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, in ath5k_hw_rfregs_init()
1151 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && in ath5k_hw_rfregs_init()
1152 ah->ah_mac_srev < AR5K_SREV_AR5413) in ath5k_hw_rfregs_init()
1153 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), in ath5k_hw_rfregs_init()
1159 for (i = 0; i < ah->ah_rf_banks_size; i++) { in ath5k_hw_rfregs_init()
1161 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); in ath5k_hw_rfregs_init()
1197 ath5k_hw_rf5110_channel(struct ath5k_hw *ah, in ath5k_hw_rf5110_channel() argument
1206 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER); in ath5k_hw_rf5110_channel()
1207 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0); in ath5k_hw_rf5110_channel()
1256 ath5k_hw_rf5111_channel(struct ath5k_hw *ah, in ath5k_hw_rf5111_channel() argument
1293 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8), in ath5k_hw_rf5111_channel()
1295 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00), in ath5k_hw_rf5111_channel()
1314 ath5k_hw_rf5112_channel(struct ath5k_hw *ah, in ath5k_hw_rf5112_channel() argument
1373 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); in ath5k_hw_rf5112_channel()
1374 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); in ath5k_hw_rf5112_channel()
1388 ath5k_hw_rf2425_channel(struct ath5k_hw *ah, in ath5k_hw_rf2425_channel() argument
1418 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); in ath5k_hw_rf2425_channel()
1419 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); in ath5k_hw_rf2425_channel()
1433 ath5k_hw_channel(struct ath5k_hw *ah, in ath5k_hw_channel() argument
1441 if (!ath5k_channel_ok(ah, channel)) { in ath5k_hw_channel()
1442 ATH5K_ERR(ah, in ath5k_hw_channel()
1452 switch (ah->ah_radio) { in ath5k_hw_channel()
1454 ret = ath5k_hw_rf5110_channel(ah, channel); in ath5k_hw_channel()
1457 ret = ath5k_hw_rf5111_channel(ah, channel); in ath5k_hw_channel()
1461 ret = ath5k_hw_rf2425_channel(ah, channel); in ath5k_hw_channel()
1464 ret = ath5k_hw_rf5112_channel(ah, channel); in ath5k_hw_channel()
1473 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, in ath5k_hw_channel()
1476 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, in ath5k_hw_channel()
1480 ah->ah_current_channel = channel; in ath5k_hw_channel()
1524 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah) in ath5k_hw_read_measured_noise_floor() argument
1528 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF); in ath5k_hw_read_measured_noise_floor()
1537 ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah) in ath5k_hw_init_nfcal_hist() argument
1541 ah->ah_nfcal_hist.index = 0; in ath5k_hw_init_nfcal_hist()
1543 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE; in ath5k_hw_init_nfcal_hist()
1551 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor) in ath5k_hw_update_nfcal_hist() argument
1553 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist; in ath5k_hw_update_nfcal_hist()
1568 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah) in ath5k_hw_get_median_noise_floor() argument
1573 memcpy(sorted_nfval, ah->ah_nfcal_hist.nfval, sizeof(sorted_nfval)); in ath5k_hw_get_median_noise_floor()
1576 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_get_median_noise_floor()
1591 ath5k_hw_update_noise_floor(struct ath5k_hw *ah) in ath5k_hw_update_noise_floor() argument
1593 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_hw_update_noise_floor()
1599 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) { in ath5k_hw_update_noise_floor()
1600 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_update_noise_floor()
1606 ah->ah_cal_mask |= AR5K_CALIBRATION_NF; in ath5k_hw_update_noise_floor()
1608 ee_mode = ath5k_eeprom_mode_from_channel(ah, ah->ah_current_channel); in ath5k_hw_update_noise_floor()
1611 nf = ath5k_hw_read_measured_noise_floor(ah); in ath5k_hw_update_noise_floor()
1615 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_update_noise_floor()
1623 ath5k_hw_update_nfcal_hist(ah, nf); in ath5k_hw_update_noise_floor()
1624 nf = ath5k_hw_get_median_noise_floor(ah); in ath5k_hw_update_noise_floor()
1627 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M; in ath5k_hw_update_noise_floor()
1629 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); in ath5k_hw_update_noise_floor()
1631 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, in ath5k_hw_update_noise_floor()
1634 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, in ath5k_hw_update_noise_floor()
1644 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); in ath5k_hw_update_noise_floor()
1645 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_update_noise_floor()
1650 ah->ah_noise_floor = nf; in ath5k_hw_update_noise_floor()
1652 ah->ah_cal_mask &= ~AR5K_CALIBRATION_NF; in ath5k_hw_update_noise_floor()
1654 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_update_noise_floor()
1666 ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, in ath5k_hw_rf5110_calibrate() argument
1672 if (!(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) in ath5k_hw_rf5110_calibrate()
1678 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, in ath5k_hw_rf5110_calibrate()
1680 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); in ath5k_hw_rf5110_calibrate()
1681 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); in ath5k_hw_rf5110_calibrate()
1688 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); in ath5k_hw_rf5110_calibrate()
1690 ret = ath5k_hw_channel(ah, channel); in ath5k_hw_rf5110_calibrate()
1695 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); in ath5k_hw_rf5110_calibrate()
1698 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); in ath5k_hw_rf5110_calibrate()
1708 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG); in ath5k_hw_rf5110_calibrate()
1709 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE); in ath5k_hw_rf5110_calibrate()
1710 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT); in ath5k_hw_rf5110_calibrate()
1713 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | in ath5k_hw_rf5110_calibrate()
1716 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | in ath5k_hw_rf5110_calibrate()
1721 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | in ath5k_hw_rf5110_calibrate()
1728 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); in ath5k_hw_rf5110_calibrate()
1730 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); in ath5k_hw_rf5110_calibrate()
1731 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); in ath5k_hw_rf5110_calibrate()
1738 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); in ath5k_hw_rf5110_calibrate()
1740 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, in ath5k_hw_rf5110_calibrate()
1744 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG); in ath5k_hw_rf5110_calibrate()
1745 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE); in ath5k_hw_rf5110_calibrate()
1746 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); in ath5k_hw_rf5110_calibrate()
1749 ATH5K_ERR(ah, "calibration timeout (%uMHz)\n", in ath5k_hw_rf5110_calibrate()
1757 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, in ath5k_hw_rf5110_calibrate()
1759 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); in ath5k_hw_rf5110_calibrate()
1769 ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah) in ath5k_hw_rf511x_iq_calibrate() argument
1776 if (!ah->ah_iq_cal_needed) in ath5k_hw_rf511x_iq_calibrate()
1778 else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) { in ath5k_hw_rf511x_iq_calibrate()
1779 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_rf511x_iq_calibrate()
1789 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); in ath5k_hw_rf511x_iq_calibrate()
1790 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); in ath5k_hw_rf511x_iq_calibrate()
1791 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); in ath5k_hw_rf511x_iq_calibrate()
1792 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_rf511x_iq_calibrate()
1800 if (ah->ah_version == AR5K_AR5211) in ath5k_hw_rf511x_iq_calibrate()
1816 if (ah->ah_version == AR5K_AR5211) in ath5k_hw_rf511x_iq_calibrate()
1822 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_rf511x_iq_calibrate()
1827 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff); in ath5k_hw_rf511x_iq_calibrate()
1828 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff); in ath5k_hw_rf511x_iq_calibrate()
1829 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); in ath5k_hw_rf511x_iq_calibrate()
1833 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, in ath5k_hw_rf511x_iq_calibrate()
1835 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); in ath5k_hw_rf511x_iq_calibrate()
1850 ath5k_hw_phy_calibrate(struct ath5k_hw *ah, in ath5k_hw_phy_calibrate() argument
1855 if (ah->ah_radio == AR5K_RF5110) in ath5k_hw_phy_calibrate()
1856 return ath5k_hw_rf5110_calibrate(ah, channel); in ath5k_hw_phy_calibrate()
1858 ret = ath5k_hw_rf511x_iq_calibrate(ah); in ath5k_hw_phy_calibrate()
1860 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_phy_calibrate()
1871 if ((ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && in ath5k_hw_phy_calibrate()
1872 (ah->ah_radio == AR5K_RF5111 || in ath5k_hw_phy_calibrate()
1873 ah->ah_radio == AR5K_RF5112) && in ath5k_hw_phy_calibrate()
1875 ath5k_hw_request_rfgain_probe(ah); in ath5k_hw_phy_calibrate()
1878 if (!(ah->ah_cal_mask & AR5K_CALIBRATION_NF)) in ath5k_hw_phy_calibrate()
1879 ath5k_hw_update_noise_floor(ah); in ath5k_hw_phy_calibrate()
1900 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, in ath5k_hw_set_spur_mitigation_filter() argument
1903 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_hw_set_spur_mitigation_filter()
1928 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) in ath5k_hw_set_spur_mitigation_filter()
1959 switch (ah->ah_bwmode) { in ath5k_hw_set_spur_mitigation_filter()
2053 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, in ath5k_hw_set_spur_mitigation_filter()
2056 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, in ath5k_hw_set_spur_mitigation_filter()
2062 ath5k_hw_reg_write(ah, in ath5k_hw_set_spur_mitigation_filter()
2071 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7); in ath5k_hw_set_spur_mitigation_filter()
2072 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, in ath5k_hw_set_spur_mitigation_filter()
2076 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9); in ath5k_hw_set_spur_mitigation_filter()
2077 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, in ath5k_hw_set_spur_mitigation_filter()
2082 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1); in ath5k_hw_set_spur_mitigation_filter()
2083 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2); in ath5k_hw_set_spur_mitigation_filter()
2084 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3); in ath5k_hw_set_spur_mitigation_filter()
2085 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, in ath5k_hw_set_spur_mitigation_filter()
2089 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1); in ath5k_hw_set_spur_mitigation_filter()
2090 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2); in ath5k_hw_set_spur_mitigation_filter()
2091 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3); in ath5k_hw_set_spur_mitigation_filter()
2092 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, in ath5k_hw_set_spur_mitigation_filter()
2096 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & in ath5k_hw_set_spur_mitigation_filter()
2099 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, in ath5k_hw_set_spur_mitigation_filter()
2101 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ, in ath5k_hw_set_spur_mitigation_filter()
2105 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11); in ath5k_hw_set_spur_mitigation_filter()
2108 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7); in ath5k_hw_set_spur_mitigation_filter()
2109 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, in ath5k_hw_set_spur_mitigation_filter()
2113 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9); in ath5k_hw_set_spur_mitigation_filter()
2114 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, in ath5k_hw_set_spur_mitigation_filter()
2119 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1); in ath5k_hw_set_spur_mitigation_filter()
2120 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2); in ath5k_hw_set_spur_mitigation_filter()
2121 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3); in ath5k_hw_set_spur_mitigation_filter()
2122 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, in ath5k_hw_set_spur_mitigation_filter()
2126 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1); in ath5k_hw_set_spur_mitigation_filter()
2127 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2); in ath5k_hw_set_spur_mitigation_filter()
2128 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3); in ath5k_hw_set_spur_mitigation_filter()
2129 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, in ath5k_hw_set_spur_mitigation_filter()
2196 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant) in ath5k_hw_set_def_antenna() argument
2198 if (ah->ah_version != AR5K_AR5210) in ath5k_hw_set_def_antenna()
2199 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA); in ath5k_hw_set_def_antenna()
2209 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable) in ath5k_hw_set_fast_div() argument
2217 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_set_fast_div()
2220 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_set_fast_div()
2224 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_set_fast_div()
2232 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, in ath5k_hw_set_fast_div()
2235 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, in ath5k_hw_set_fast_div()
2238 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, in ath5k_hw_set_fast_div()
2241 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, in ath5k_hw_set_fast_div()
2255 ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode) in ath5k_hw_set_antenna_switch() argument
2263 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A) in ath5k_hw_set_antenna_switch()
2265 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B) in ath5k_hw_set_antenna_switch()
2273 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL, in ath5k_hw_set_antenna_switch()
2275 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] | in ath5k_hw_set_antenna_switch()
2279 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0], in ath5k_hw_set_antenna_switch()
2281 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1], in ath5k_hw_set_antenna_switch()
2291 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) in ath5k_hw_set_antenna_mode() argument
2293 struct ieee80211_channel *channel = ah->ah_current_channel; in ath5k_hw_set_antenna_mode()
2303 ah->ah_ant_mode = ant_mode; in ath5k_hw_set_antenna_mode()
2307 def_ant = ah->ah_def_ant; in ath5k_hw_set_antenna_mode()
2309 ee_mode = ath5k_eeprom_mode_from_channel(ah, channel); in ath5k_hw_set_antenna_mode()
2376 ah->ah_tx_ant = tx_ant; in ath5k_hw_set_antenna_mode()
2377 ah->ah_ant_mode = ant_mode; in ath5k_hw_set_antenna_mode()
2378 ah->ah_def_ant = def_ant; in ath5k_hw_set_antenna_mode()
2385 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS); in ath5k_hw_set_antenna_mode()
2388 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1); in ath5k_hw_set_antenna_mode()
2390 ath5k_hw_set_antenna_switch(ah, ee_mode); in ath5k_hw_set_antenna_mode()
2393 ath5k_hw_set_fast_div(ah, ee_mode, fast_div); in ath5k_hw_set_antenna_mode()
2394 ath5k_hw_set_def_antenna(ah, def_ant); in ath5k_hw_set_antenna_mode()
2577 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah, in ath5k_get_chan_pcal_surrounding_piers() argument
2582 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_get_chan_pcal_surrounding_piers()
2666 ath5k_get_rate_pcal_data(struct ath5k_hw *ah, in ath5k_get_rate_pcal_data() argument
2670 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_get_rate_pcal_data()
2761 ath5k_get_max_ctl_power(struct ath5k_hw *ah, in ath5k_get_max_ctl_power() argument
2764 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); in ath5k_get_max_ctl_power()
2765 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_get_max_ctl_power()
2768 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4; in ath5k_get_max_ctl_power()
2779 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) in ath5k_get_max_ctl_power()
2785 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) in ath5k_get_max_ctl_power()
2827 ah->ah_txpower.txp_max_pwr = 4 * min(edge_pwr, max_chan_pwr); in ath5k_get_max_ctl_power()
2874 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, in ath5k_fill_pwr_to_pcdac_table() argument
2877 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; in ath5k_fill_pwr_to_pcdac_table()
2878 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; in ath5k_fill_pwr_to_pcdac_table()
2924 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, in ath5k_combine_linear_pcdac_curves() argument
2927 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; in ath5k_combine_linear_pcdac_curves()
2949 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; in ath5k_combine_linear_pcdac_curves()
2950 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; in ath5k_combine_linear_pcdac_curves()
2968 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */ in ath5k_combine_linear_pcdac_curves()
2969 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; in ath5k_combine_linear_pcdac_curves()
2977 ah->ah_txpower.txp_min_idx = min_pwr_idx / 2; in ath5k_combine_linear_pcdac_curves()
3022 ath5k_write_pcdac_table(struct ath5k_hw *ah) in ath5k_write_pcdac_table() argument
3024 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; in ath5k_write_pcdac_table()
3031 ath5k_hw_reg_write(ah, in ath5k_write_pcdac_table()
3074 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, in ath5k_combine_pwr_to_pdadc_curves() argument
3078 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; in ath5k_combine_pwr_to_pdadc_curves()
3087 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) & in ath5k_combine_pwr_to_pdadc_curves()
3092 pdadc_tmp = ah->ah_txpower.tmpL[pdg]; in ath5k_combine_pwr_to_pdadc_curves()
3174 ath5k_hw_reg_write(ah, in ath5k_combine_pwr_to_pdadc_curves()
3188 ah->ah_txpower.txp_min_idx = pwr_min[0]; in ath5k_combine_pwr_to_pdadc_curves()
3198 ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode) in ath5k_write_pwr_to_pdadc_table() argument
3200 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_write_pwr_to_pdadc_table()
3201 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; in ath5k_write_pwr_to_pdadc_table()
3210 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1); in ath5k_write_pwr_to_pdadc_table()
3237 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1); in ath5k_write_pwr_to_pdadc_table()
3244 ath5k_hw_reg_write(ah, val, AR5K_PHY_PDADC_TXPOWER(i)); in ath5k_write_pwr_to_pdadc_table()
3267 ath5k_setup_channel_powertable(struct ath5k_hw *ah, in ath5k_setup_channel_powertable() argument
3274 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_setup_channel_powertable()
3284 ath5k_get_chan_pcal_surrounding_piers(ah, channel, in ath5k_setup_channel_powertable()
3303 tmpL = ah->ah_txpower.tmpL[pdg]; in ath5k_setup_channel_powertable()
3304 tmpR = ah->ah_txpower.tmpR[pdg]; in ath5k_setup_channel_powertable()
3405 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target, in ath5k_setup_channel_powertable()
3410 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target, in ath5k_setup_channel_powertable()
3421 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max, in ath5k_setup_channel_powertable()
3427 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2); in ath5k_setup_channel_powertable()
3432 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max); in ath5k_setup_channel_powertable()
3435 ah->ah_txpower.txp_min_idx = 0; in ath5k_setup_channel_powertable()
3436 ah->ah_txpower.txp_offset = 0; in ath5k_setup_channel_powertable()
3441 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max, in ath5k_setup_channel_powertable()
3446 ah->ah_txpower.txp_offset = table_min[0]; in ath5k_setup_channel_powertable()
3452 ah->ah_txpower.txp_setup = true; in ath5k_setup_channel_powertable()
3464 ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type) in ath5k_write_channel_powertable() argument
3467 ath5k_write_pwr_to_pdadc_table(ah, ee_mode); in ath5k_write_channel_powertable()
3469 ath5k_write_pcdac_table(ah); in ath5k_write_channel_powertable()
3503 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, in ath5k_setup_rate_powertable() argument
3514 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2; in ath5k_setup_rate_powertable()
3517 rates = ah->ah_txpower.txp_rates_power_table; in ath5k_setup_rate_powertable()
3552 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A)) in ath5k_setup_rate_powertable()
3554 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta; in ath5k_setup_rate_powertable()
3562 ah->ah_txpower.txp_min_pwr = 2 * rates[7]; in ath5k_setup_rate_powertable()
3563 ah->ah_txpower.txp_cur_pwr = 2 * rates[0]; in ath5k_setup_rate_powertable()
3568 ah->ah_txpower.txp_ofdm = rates[7]; in ath5k_setup_rate_powertable()
3574 rate_idx_scaled = rates[i] + ah->ah_txpower.txp_offset; in ath5k_setup_rate_powertable()
3595 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, in ath5k_hw_txpower() argument
3599 struct ieee80211_channel *curr_channel = ah->ah_current_channel; in ath5k_hw_txpower()
3605 ATH5K_ERR(ah, "invalid tx power: %u\n", txpower); in ath5k_hw_txpower()
3609 ee_mode = ath5k_eeprom_mode_from_channel(ah, channel); in ath5k_hw_txpower()
3612 switch (ah->ah_radio) { in ath5k_hw_txpower()
3637 if (!ah->ah_txpower.txp_setup || in ath5k_hw_txpower()
3642 int requested_txpower = ah->ah_txpower.txp_requested; in ath5k_hw_txpower()
3644 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); in ath5k_hw_txpower()
3647 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; in ath5k_hw_txpower()
3649 ah->ah_txpower.txp_requested = requested_txpower; in ath5k_hw_txpower()
3652 ret = ath5k_setup_channel_powertable(ah, channel, in ath5k_hw_txpower()
3659 ath5k_write_channel_powertable(ah, ee_mode, type); in ath5k_hw_txpower()
3662 ath5k_get_max_ctl_power(ah, channel); in ath5k_hw_txpower()
3672 ath5k_get_rate_pcal_data(ah, channel, &rate_info); in ath5k_hw_txpower()
3675 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode); in ath5k_hw_txpower()
3678 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | in ath5k_hw_txpower()
3682 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | in ath5k_hw_txpower()
3686 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | in ath5k_hw_txpower()
3690 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | in ath5k_hw_txpower()
3695 if (ah->ah_txpower.txp_tpc) { in ath5k_hw_txpower()
3696 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | in ath5k_hw_txpower()
3699 ath5k_hw_reg_write(ah, in ath5k_hw_txpower()
3705 ath5k_hw_reg_write(ah, AR5K_TUNE_MAX_TXPOWER, in ath5k_hw_txpower()
3721 ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower) in ath5k_hw_set_txpower_limit() argument
3723 ATH5K_DBG(ah, ATH5K_DEBUG_TXPOWER, in ath5k_hw_set_txpower_limit()
3726 return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower); in ath5k_hw_set_txpower_limit()
3748 ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, in ath5k_hw_phy_init() argument
3762 curr_channel = ah->ah_current_channel; in ath5k_hw_phy_init()
3771 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ, in ath5k_hw_phy_init()
3774 if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT)) in ath5k_hw_phy_init()
3783 ret = ath5k_hw_channel(ah, channel); in ath5k_hw_phy_init()
3787 ath5k_hw_wait_for_synth(ah, channel); in ath5k_hw_phy_init()
3797 ret = ath5k_hw_txpower(ah, channel, ah->ah_txpower.txp_requested ? in ath5k_hw_phy_init()
3798 ah->ah_txpower.txp_requested * 2 : in ath5k_hw_phy_init()
3804 if (ah->ah_version == AR5K_AR5212 && in ath5k_hw_phy_init()
3807 ret = ath5k_hw_write_ofdm_timings(ah, channel); in ath5k_hw_phy_init()
3814 if (ah->ah_mac_srev >= AR5K_SREV_AR5424) in ath5k_hw_phy_init()
3815 ath5k_hw_set_spur_mitigation_filter(ah, in ath5k_hw_phy_init()
3831 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ, in ath5k_hw_phy_init()
3837 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_phy_init()
3849 if (ah->ah_version != AR5K_AR5210) { in ath5k_hw_phy_init()
3855 ret = ath5k_hw_rfgain_init(ah, channel->band); in ath5k_hw_phy_init()
3864 ret = ath5k_hw_rfregs_init(ah, channel, mode); in ath5k_hw_phy_init()
3870 if (ah->ah_radio == AR5K_RF5111) { in ath5k_hw_phy_init()
3872 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, in ath5k_hw_phy_init()
3875 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, in ath5k_hw_phy_init()
3879 } else if (ah->ah_version == AR5K_AR5210) { in ath5k_hw_phy_init()
3882 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); in ath5k_hw_phy_init()
3887 ret = ath5k_hw_channel(ah, channel); in ath5k_hw_phy_init()
3896 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); in ath5k_hw_phy_init()
3898 ath5k_hw_wait_for_synth(ah, channel); in ath5k_hw_phy_init()
3904 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1); in ath5k_hw_phy_init()
3905 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1); in ath5k_hw_phy_init()
3907 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10)) in ath5k_hw_phy_init()
3911 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1); in ath5k_hw_phy_init()
3932 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_phy_init()
3937 ah->ah_iq_cal_needed = false; in ath5k_hw_phy_init()
3939 ah->ah_iq_cal_needed = true; in ath5k_hw_phy_init()
3940 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, in ath5k_hw_phy_init()
3942 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, in ath5k_hw_phy_init()
3948 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, in ath5k_hw_phy_init()
3950 ATH5K_ERR(ah, "gain calibration timeout (%uMHz)\n", in ath5k_hw_phy_init()
3955 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode); in ath5k_hw_phy_init()