Lines Matching refs:u32
42 u32 cmd_id;
46 u32 header;
2215 u32 pdev_id;
2216 u32 start_freq;
2217 u32 end_freq;
2221 u32 numss_m1;
2222 u32 ru_bit_mask;
2223 u32 ppet16_ppet8_ru3_ru0[PSOC_HOST_MAX_NUM_SS];
2227 u32 default_conc_scan_config_bits;
2228 u32 default_fw_config_bits;
2230 u32 he_cap_info;
2231 u32 mpdu_density;
2232 u32 max_bssid_rx_filters;
2233 u32 num_hw_modes;
2234 u32 num_phy;
2238 u32 hw_mode_id;
2239 u32 phy_id_map;
2240 u32 hw_mode_config_type;
2252 u32 phy_id;
2253 u32 eeprom_reg_domain;
2254 u32 eeprom_reg_domain_ext;
2255 u32 regcap1;
2256 u32 regcap2;
2257 u32 wireless_modes;
2258 u32 low_2ghz_chan;
2259 u32 high_2ghz_chan;
2260 u32 low_5ghz_chan;
2261 u32 high_5ghz_chan;
2267 u32 tlv_header;
2268 u32 req_id;
2269 u32 ptr;
2270 u32 size;
2276 u32 len;
2277 u32 req_id;
2281 u32 tlv_header;
2285 u32 hw_mode_id;
2286 u32 num_band_to_mac;
2291 u32 tlv_header;
2292 u32 pdev_id;
2293 u32 start_freq;
2294 u32 end_freq;
2298 u32 tlv_header;
2299 u32 pdev_id;
2300 u32 hw_mode_index;
2301 u32 num_band_to_mac;
2305 u32 numss_m1; /** NSS - 1*/
2307 u32 ru_count;
2308 u32 ru_mask;
2310 u32 ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS];
2316 u32 abi_version_0;
2317 u32 abi_version_1;
2318 u32 abi_version_ns_0;
2319 u32 abi_version_ns_1;
2320 u32 abi_version_ns_2;
2321 u32 abi_version_ns_3;
2325 u32 tlv_header;
2327 u32 num_host_mem_chunks;
2337 u32 tlv_header;
2338 u32 num_vdevs;
2339 u32 num_peers;
2340 u32 num_offload_peers;
2341 u32 num_offload_reorder_buffs;
2342 u32 num_peer_keys;
2343 u32 num_tids;
2344 u32 ast_skid_limit;
2345 u32 tx_chain_mask;
2346 u32 rx_chain_mask;
2347 u32 rx_timeout_pri[4];
2348 u32 rx_decap_mode;
2349 u32 scan_max_pending_req;
2350 u32 bmiss_offload_max_vdev;
2351 u32 roam_offload_max_vdev;
2352 u32 roam_offload_max_ap_profiles;
2353 u32 num_mcast_groups;
2354 u32 num_mcast_table_elems;
2355 u32 mcast2ucast_mode;
2356 u32 tx_dbg_log_size;
2357 u32 num_wds_entries;
2358 u32 dma_burst_size;
2359 u32 mac_aggr_delim;
2360 u32 rx_skip_defrag_timeout_dup_detection_check;
2361 u32 vow_config;
2362 u32 gtk_offload_max_vdev;
2363 u32 num_msdu_desc;
2364 u32 max_frag_entries;
2365 u32 num_tdls_vdevs;
2366 u32 num_tdls_conn_table_entries;
2367 u32 beacon_tx_offload_max_vdev;
2368 u32 num_multicast_filter_entries;
2369 u32 num_wow_filters;
2370 u32 num_keep_alive_pattern;
2371 u32 keep_alive_pattern_size;
2372 u32 max_tdls_concurrent_sleep_sta;
2373 u32 max_tdls_concurrent_buffer_sta;
2374 u32 wmi_send_separate;
2375 u32 num_ocb_vdevs;
2376 u32 num_ocb_channels;
2377 u32 num_ocb_schedules;
2378 u32 flag1;
2379 u32 smart_ant_cap;
2380 u32 bk_minfree;
2381 u32 be_minfree;
2382 u32 vi_minfree;
2383 u32 vo_minfree;
2384 u32 alloc_frag_desc_for_data_pkt;
2385 u32 num_ns_ext_tuples_cfg;
2386 u32 bpf_instruction_size;
2387 u32 max_bssid_rx_filters;
2388 u32 use_pdev_id;
2389 u32 max_num_dbs_scan_duty_cycle;
2390 u32 max_num_group_keys;
2391 u32 peer_map_unmap_v2_support;
2392 u32 sched_params;
2393 u32 twt_ap_pdev_count;
2394 u32 twt_ap_sta_count;
2395 u32 max_nlo_ssids;
2396 u32 num_pkt_filters;
2397 u32 num_max_sta_vdevs;
2398 u32 max_bssid_indicator;
2399 u32 ul_resp_config;
2400 u32 msdu_flow_override_config0;
2401 u32 msdu_flow_override_config1;
2402 u32 flags2;
2403 u32 host_service_flags;
2404 u32 max_rnr_neighbours;
2405 u32 ema_max_vap_cnt;
2406 u32 ema_max_profile_period;
2410 u32 fw_build_vers;
2412 u32 phy_capability;
2413 u32 max_frag_entry;
2414 u32 num_rf_chains;
2415 u32 ht_cap_info;
2416 u32 vht_cap_info;
2417 u32 vht_supp_mcs;
2418 u32 hw_min_tx_power;
2419 u32 hw_max_tx_power;
2420 u32 sys_cap_info;
2421 u32 min_pkt_size_enable;
2422 u32 max_bcn_ie_size;
2423 u32 num_mem_reqs;
2424 u32 max_num_scan_channels;
2425 u32 hw_bd_id;
2426 u32 hw_bd_info[HW_BD_INFO_SIZE];
2427 u32 max_supported_macs;
2428 u32 wmi_fw_sub_feat_caps;
2429 u32 num_dbs_hw_modes;
2436 u32 txrx_chainmask;
2437 u32 default_dbs_hw_mode_index;
2438 u32 num_msdu_desc;
2441 #define WMI_SERVICE_BM_SIZE ((WMI_MAX_SERVICE + sizeof(u32) - 1) / sizeof(u32))
2444 #define WMI_SERVICE_EXT_BM_SIZE (WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(u32))
2449 u32 default_conc_scan_config_bits;
2450 u32 default_fw_config_bits;
2452 u32 he_cap_info;
2453 u32 mpdu_density;
2454 u32 max_bssid_rx_filters;
2455 u32 fw_build_vers_ext;
2456 u32 max_nlo_ssids;
2457 u32 max_bssid_indicator;
2458 u32 he_cap_info_ext;
2462 u32 num_hw_modes;
2463 u32 num_chainmask_tables;
2467 u32 tlv_header;
2468 u32 hw_mode_id;
2469 u32 phy_id_map;
2470 u32 hw_mode_config_type;
2482 u32 hw_mode_id;
2483 u32 pdev_id;
2484 u32 phy_id;
2485 u32 supported_flags;
2486 u32 supported_bands;
2487 u32 ampdu_density;
2488 u32 max_bw_supported_2g;
2489 u32 ht_cap_info_2g;
2490 u32 vht_cap_info_2g;
2491 u32 vht_supp_mcs_2g;
2492 u32 he_cap_info_2g;
2493 u32 he_supp_mcs_2g;
2494 u32 tx_chain_mask_2g;
2495 u32 rx_chain_mask_2g;
2496 u32 max_bw_supported_5g;
2497 u32 ht_cap_info_5g;
2498 u32 vht_cap_info_5g;
2499 u32 vht_supp_mcs_5g;
2500 u32 he_cap_info_5g;
2501 u32 he_supp_mcs_5g;
2502 u32 tx_chain_mask_5g;
2503 u32 rx_chain_mask_5g;
2504 u32 he_cap_phy_info_2g[WMI_MAX_HECAP_PHY_SIZE];
2505 u32 he_cap_phy_info_5g[WMI_MAX_HECAP_PHY_SIZE];
2508 u32 chainmask_table_id;
2509 u32 lmac_id;
2510 u32 he_cap_info_2g_ext;
2511 u32 he_cap_info_5g_ext;
2512 u32 he_cap_info_internal;
2513 u32 wireless_modes;
2514 u32 low_2ghz_chan_freq;
2515 u32 high_2ghz_chan_freq;
2516 u32 low_5ghz_chan_freq;
2517 u32 high_5ghz_chan_freq;
2518 u32 nss_ratio;
2522 u32 tlv_header;
2523 u32 phy_id;
2524 u32 eeprom_reg_domain;
2525 u32 eeprom_reg_domain_ext;
2526 u32 regcap1;
2527 u32 regcap2;
2528 u32 wireless_modes;
2529 u32 low_2ghz_chan;
2530 u32 high_2ghz_chan;
2531 u32 low_5ghz_chan;
2532 u32 high_5ghz_chan;
2536 u32 num_phy;
2544 u32 word0;
2545 u32 word1;
2551 u32 tlv_header;
2552 u32 pdev_id;
2553 u32 module_id;
2554 u32 min_elem;
2555 u32 min_buf_sz;
2556 u32 min_buf_align;
2562 u32 status;
2563 u32 num_dscp_table;
2564 u32 num_extra_mac_addr;
2565 u32 num_total_peers;
2566 u32 num_extra_peers;
2571 u32 max_ast_index;
2572 u32 pktlog_defs_checksum;
2576 u32 wmi_service_segment_offset;
2577 u32 wmi_service_segment_bitmap[WMI_SERVICE_SEGMENT_BM_SIZE32];
2584 u32 rx_decap_mode;
2590 u32 type;
2591 u32 subtype;
2596 u32 pdev_id;
2597 u32 mbssid_flags;
2598 u32 mbssid_tx_vdev_id;
2602 u32 tlv_header;
2603 u32 vdev_id;
2604 u32 vdev_type;
2605 u32 vdev_subtype;
2607 u32 num_cfg_txrx_streams;
2608 u32 pdev_id;
2609 u32 mbssid_flags;
2610 u32 mbssid_tx_vdev_id;
2614 u32 tlv_header;
2615 u32 band;
2616 u32 supported_tx_streams;
2617 u32 supported_rx_streams;
2621 u32 tlv_header;
2622 u32 vdev_id;
2626 u32 tlv_header;
2627 u32 vdev_id;
2628 u32 vdev_assoc_id;
2631 u32 nontx_profile_idx;
2632 u32 nontx_profile_cnt;
2636 u32 tlv_header;
2637 u32 vdev_id;
2641 u32 tlv_header;
2642 u32 vdev_id;
2651 u32 ssid_len;
2652 u32 ssid[8];
2658 u32 tlv_header;
2659 u32 vdev_id;
2660 u32 requestor_id;
2661 u32 beacon_interval;
2662 u32 dtim_period;
2663 u32 flags;
2665 u32 bcn_tx_rate;
2666 u32 bcn_txpower;
2667 u32 num_noa_descriptors;
2668 u32 disable_hw_ack;
2669 u32 preferred_tx_streams;
2670 u32 preferred_rx_streams;
2671 u32 he_ops;
2672 u32 cac_duration_ms;
2673 u32 regdomain;
2674 u32 min_data_rate;
2675 u32 mbssid_flags;
2676 u32 mbssid_tx_vdev_id;
2687 u32 type_count;
2688 u32 duration;
2689 u32 interval;
2690 u32 start_time;
2696 u32 mhz;
2697 u32 half_rate:1,
2707 u32 phy_mode;
2708 u32 cfreq1;
2709 u32 cfreq2;
2810 u32 freq;
2811 u32 band_center_freq1;
2812 u32 band_center_freq2;
2821 u32 min_power;
2822 u32 max_power;
2823 u32 max_reg_power;
2824 u32 max_antenna_gain;
2829 u32 vdev_id;
2831 u32 bcn_intval;
2832 u32 dtim_period;
2834 u32 ssid_len;
2835 u32 bcn_tx_rate;
2836 u32 bcn_tx_power;
2840 u32 he_ops;
2841 u32 cac_duration_ms;
2842 u32 regdomain;
2843 u32 pref_rx_streams;
2844 u32 pref_tx_streams;
2845 u32 num_noa_descriptors;
2846 u32 min_data_rate;
2847 u32 mbssid_flags;
2848 u32 mbssid_tx_vdev_id;
2853 u32 peer_type;
2854 u32 vdev_id;
2862 u32 peer_tid_bitmap;
2870 u32 ctl_2g;
2871 u32 ctl_5g;
2873 u32 pdev_id;
2879 u32 peer_tid_bitmap;
2968 u32 param_id;
2969 u32 param_value;
2979 u32 tlv_header;
2980 u32 vdev_id;
2982 u32 peer_type;
2986 u32 tlv_header;
2987 u32 vdev_id;
2992 u32 tlv_header;
2993 u32 vdev_id;
2995 u32 tid;
2996 u32 queue_ptr_lo;
2997 u32 queue_ptr_hi;
2998 u32 queue_no;
2999 u32 ba_window_size_valid;
3000 u32 ba_window_size;
3004 u32 tlv_header;
3005 u32 vdev_id;
3007 u32 tid_mask;
3011 u32 gpio_num;
3012 u32 input;
3013 u32 pull_type;
3014 u32 intr_mode;
3038 u32 tlv_header;
3039 u32 gpio_num;
3040 u32 input;
3041 u32 pull_type;
3042 u32 intr_mode;
3046 u32 gpio_num;
3047 u32 set;
3051 u32 tlv_header;
3052 u32 gpio_num;
3053 u32 set;
3057 u32 arg;
3058 u32 value;
3062 u32 tlv_header;
3063 u32 param_id;
3064 u32 param_value;
3068 u32 tlv_header;
3069 u32 pdev_id;
3070 u32 param_id;
3071 u32 param_value;
3075 u32 tlv_header;
3076 u32 vdev_id;
3077 u32 sta_ps_mode;
3081 u32 tlv_header;
3082 u32 pdev_id;
3083 u32 suspend_opt;
3087 u32 tlv_header;
3088 u32 pdev_id;
3092 u32 tlv_header;
3094 u32 req_type;
3095 u32 pdev_id;
3099 u32 tlv_header;
3100 u32 vdev_id;
3102 u32 param;
3103 u32 value;
3107 u32 tlv_header;
3108 u32 vdev_id;
3109 u32 param;
3110 u32 value;
3114 u32 tlv_header;
3115 u32 pdev_id;
3116 u32 reg_domain;
3117 u32 reg_domain_2g;
3118 u32 reg_domain_5g;
3119 u32 conformance_test_limit_2g;
3120 u32 conformance_test_limit_5g;
3121 u32 dfs_domain;
3125 u32 tlv_header;
3126 u32 vdev_id;
3128 u32 param_id;
3129 u32 param_value;
3133 u32 tlv_header;
3134 u32 vdev_id;
3136 u32 peer_tid_bitmap;
3140 u32 tlv_header;
3141 u32 pdev_id;
3145 u32 tlv_header;
3146 u32 vdev_id;
3147 u32 bcn_ctrl_op;
3161 u32 len;
3220 u32 tlv_header;
3221 u32 scan_id;
3222 u32 scan_req_id;
3223 u32 vdev_id;
3224 u32 scan_priority;
3225 u32 notify_scan_events;
3226 u32 dwell_time_active;
3227 u32 dwell_time_passive;
3228 u32 min_rest_time;
3229 u32 max_rest_time;
3230 u32 repeat_probe_time;
3231 u32 probe_spacing_time;
3232 u32 idle_time;
3233 u32 max_scan_time;
3234 u32 probe_delay;
3235 u32 scan_ctrl_flags;
3236 u32 burst_duration;
3237 u32 num_chan;
3238 u32 num_bssid;
3239 u32 num_ssids;
3240 u32 ie_len;
3241 u32 n_probes;
3244 u32 ie_bitmap[WMI_IE_BITMAP_SIZE];
3245 u32 num_vendor_oui;
3246 u32 scan_ctrl_flags_ext;
3247 u32 dwell_time_active_2g;
3248 u32 dwell_time_active_6g;
3249 u32 dwell_time_passive_6g;
3250 u32 scan_start_offset;
3295 u32 freq_flags;
3296 u32 short_ssid;
3300 u32 freq_flags;
3305 u32 scan_id;
3306 u32 scan_req_id;
3307 u32 vdev_id;
3308 u32 pdev_id;
3312 u32 scan_ev_started:1,
3326 u32 scan_events;
3328 u32 scan_ctrl_flags_ext;
3329 u32 dwell_time_active;
3330 u32 dwell_time_active_2g;
3331 u32 dwell_time_passive;
3332 u32 dwell_time_active_6g;
3333 u32 dwell_time_passive_6g;
3334 u32 min_rest_time;
3335 u32 max_rest_time;
3336 u32 repeat_probe_time;
3337 u32 probe_spacing_time;
3338 u32 idle_time;
3339 u32 max_scan_time;
3340 u32 probe_delay;
3343 u32 scan_f_passive:1,
3369 u32 scan_flags;
3372 u32 burst_duration;
3373 u32 num_chan;
3374 u32 num_bssid;
3375 u32 num_ssids;
3376 u32 n_probes;
3377 u32 *chan_list;
3378 u32 notify_scan_events;
3384 u32 num_hint_s_ssid;
3385 u32 num_hint_bssid;
3402 u32 scan_id;
3403 u32 scan_req_id;
3404 u32 vdev_id;
3405 u32 scan_priority;
3406 u32 notify_scan_events;
3407 u32 dwell_time_active;
3408 u32 dwell_time_passive;
3409 u32 min_rest_time;
3410 u32 max_rest_time;
3411 u32 repeat_probe_time;
3412 u32 probe_spacing_time;
3413 u32 idle_time;
3414 u32 max_scan_time;
3415 u32 probe_delay;
3416 u32 scan_ctrl_flags;
3418 u32 ie_len;
3419 u32 n_channels;
3420 u32 n_ssids;
3421 u32 n_bssids;
3424 u32 channels[64];
3445 u32 requester;
3446 u32 scan_id;
3448 u32 vdev_id;
3449 u32 pdev_id;
3453 u32 tlv_header;
3454 u32 vdev_id;
3455 u32 data_len;
3457 u32 frag_ptr;
3458 u32 frag_ptr_lo;
3460 u32 frame_ctrl;
3461 u32 dtim_flag;
3462 u32 bcn_antenna;
3463 u32 frag_ptr_hi;
3490 u32 tlv_header;
3491 u32 mhz;
3492 u32 band_center_freq1;
3493 u32 band_center_freq2;
3494 u32 info;
3495 u32 reg_info_1;
3496 u32 reg_info_2;
3526 u32 tlv_header;
3527 u32 type;
3528 u32 delay_time_ms;
3532 u32 tlv_header;
3533 u32 vdev_id;
3534 u32 param_id;
3535 u32 param_value;
3556 u32 tlv_header;
3558 u32 vdev_id;
3560 u32 pdev_id;
3564 u32 tlv_header;
3565 u32 param;
3566 u32 pdev_id;
3570 u32 len;
3571 u32 msgref;
3572 u32 segmentinfo;
3573 u32 pdev_id;
3577 u32 tlv_header;
3594 u32 tlv_header;
3595 u32 vdev_id;
3596 u32 tim_ie_offset;
3597 u32 buf_len;
3598 u32 csa_switch_count_offset;
3599 u32 ext_csa_switch_count_offset;
3600 u32 csa_event_bitmap;
3601 u32 mbssid_ie_offset;
3602 u32 esp_ie_offset;
3603 u32 csc_switch_count_offset;
3604 u32 csc_event_bitmap;
3605 u32 mu_edca_ie_offset;
3606 u32 feature_enable_bitmap;
3607 u32 ema_params;
3611 u32 key_seq_counter_l;
3612 u32 key_seq_counter_h;
3616 u32 tlv_header;
3617 u32 vdev_id;
3619 u32 key_idx;
3620 u32 key_flags;
3621 u32 key_cipher;
3627 u32 key_len;
3628 u32 key_txmic_len;
3629 u32 key_rxmic_len;
3630 u32 is_group_key_id_valid;
3631 u32 group_key_id;
3639 u32 vdev_id;
3641 u32 key_idx;
3642 u32 key_flags;
3643 u32 key_cipher;
3644 u32 key_len;
3645 u32 key_txmic_len;
3646 u32 key_rxmic_len;
3659 u32 num_rates;
3665 u32 vdev_id;
3666 u32 peer_new_assoc;
3667 u32 peer_associd;
3668 u32 peer_flags;
3669 u32 peer_caps;
3670 u32 peer_listen_intval;
3671 u32 peer_ht_caps;
3672 u32 peer_max_mpdu;
3673 u32 peer_mpdu_density;
3674 u32 peer_rate_caps;
3675 u32 peer_nss;
3676 u32 peer_vht_caps;
3677 u32 peer_phymode;
3678 u32 peer_ht_info[2];
3681 u32 rx_max_rate;
3682 u32 rx_mcs_set;
3683 u32 tx_max_rate;
3684 u32 tx_mcs_set;
3687 u32 tx_max_mcs_nss;
3688 u32 peer_bw_rxnss_override;
3713 u32 peer_he_cap_macinfo[2];
3714 u32 peer_he_cap_macinfo_internal;
3715 u32 peer_he_caps_6ghz;
3716 u32 peer_he_ops;
3717 u32 peer_he_cap_phyinfo[WMI_HOST_MAX_HECAP_PHY_SIZE];
3718 u32 peer_he_mcs_count;
3719 u32 peer_he_rx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];
3720 u32 peer_he_tx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];
3728 u32 tlv_header;
3730 u32 vdev_id;
3731 u32 peer_new_assoc;
3732 u32 peer_associd;
3733 u32 peer_flags;
3734 u32 peer_caps;
3735 u32 peer_listen_intval;
3736 u32 peer_ht_caps;
3737 u32 peer_max_mpdu;
3738 u32 peer_mpdu_density;
3739 u32 peer_rate_caps;
3740 u32 peer_nss;
3741 u32 peer_vht_caps;
3742 u32 peer_phymode;
3743 u32 peer_ht_info[2];
3744 u32 num_peer_legacy_rates;
3745 u32 num_peer_ht_rates;
3746 u32 peer_bw_rxnss_override;
3748 u32 peer_he_cap_info;
3749 u32 peer_he_ops;
3750 u32 peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE];
3751 u32 peer_he_mcs;
3752 u32 peer_he_cap_info_ext;
3753 u32 peer_he_cap_info_internal;
3754 u32 min_data_rate;
3755 u32 peer_he_caps_6ghz;
3759 u32 tlv_header;
3760 u32 requestor;
3761 u32 scan_id;
3762 u32 req_type;
3763 u32 vdev_id;
3764 u32 pdev_id;
3768 u32 pdev_id;
3774 u32 tlv_header;
3775 u32 num_scan_chans;
3776 u32 flags;
3777 u32 pdev_id;
3781 u32 tlv_header;
3782 u32 prob_req_oui;
3799 u32 tlv_header;
3800 u32 tx_params_dword0;
3801 u32 tx_params_dword1;
3805 u32 tlv_header;
3806 u32 vdev_id;
3807 u32 desc_id;
3808 u32 chanfreq;
3809 u32 paddr_lo;
3810 u32 paddr_hi;
3811 u32 frame_len;
3812 u32 buf_len;
3813 u32 tx_params_valid;
3821 u32 tlv_header;
3822 u32 vdev_id;
3823 u32 sta_ps_mode;
3827 u32 tlv_header;
3828 u32 vdev_id;
3829 u32 forced_mode;
3833 u32 tlv_header;
3834 u32 vdev_id;
3835 u32 param;
3836 u32 value;
3840 u32 tlv_header;
3841 u32 caps;
3842 u32 erp;
3851 u32 value;
3855 u32 tlv_header;
3856 u32 pdev_id;
3857 u32 enable;
3861 u32 vdev_id;
3862 u32 param;
3863 u32 value;
3867 u32 if_id;
3868 u32 param_id;
3869 u32 param_value;
3873 u32 stats_id;
3874 u32 vdev_id;
3875 u32 pdev_id;
3883 u32 tlv_header;
3884 u32 pdev_id;
3885 u32 new_alpha2;
3911 u32 tlv_header;
3912 u32 pdev_id;
3913 u32 init_cc_type;
3915 u32 country_code;
3916 u32 regdom_id;
3917 u32 alpha2;
3922 u32 vdev_id;
3923 u32 scan_period_msec;
3924 u32 start_interval_msec;
3928 u32 tlv_header;
3929 u32 vdev_id;
3930 u32 scan_period_msec;
3931 u32 start_interval_msec;
3935 u32 tlv_header;
3936 u32 vdev_id;
3940 u32 new_alpha2;
3945 u32 tmplwm;
3946 u32 tmphwm;
3947 u32 dcoffpercent;
3948 u32 priority;
3952 u32 pdev_id;
3953 u32 enable;
3954 u32 dc;
3955 u32 dc_per_event;
3960 u32 tlv_header;
3961 u32 pdev_id;
3962 u32 enable;
3963 u32 dc;
3964 u32 dc_per_event;
3965 u32 therm_throt_levels;
3969 u32 tlv_header;
3970 u32 temp_lwm;
3971 u32 temp_hwm;
3972 u32 dc_off_percent;
3973 u32 prio;
3977 u32 tlv_header;
3978 u32 vdev_id;
3980 u32 tid;
3981 u32 initiator;
3982 u32 reasoncode;
3986 u32 tlv_header;
3987 u32 vdev_id;
3989 u32 tid;
3990 u32 statuscode;
3994 u32 tlv_header;
3995 u32 vdev_id;
3997 u32 tid;
3998 u32 buffersize;
4002 u32 tlv_header;
4003 u32 vdev_id;
4008 u32 tlv_header;
4013 u32 tlv_header;
4014 u32 pdev_id;
4015 u32 enable;
4016 u32 filter_type;
4017 u32 num_mac;
4026 u32 tlv_header;
4027 u32 pdev_id;
4028 u32 evlist; /* WMI_PKTLOG_EVENT */
4029 u32 enable;
4033 u32 tlv_header;
4034 u32 pdev_id;
4049 u32 cmd_id;
4050 u32 pdev_id;
4051 u32 radar_param;
4055 u32 tlv_header;
4056 u32 vdev_id;
4057 u32 module_id;
4058 u32 num_args;
4059 u32 diag_token;
4092 u32 tim_ie_offset;
4093 u32 tmpl_len;
4094 u32 tmpl_len_aligned;
4095 u32 csa_switch_count_offset;
4096 u32 ext_csa_switch_count_offset;
4101 u32 num_rates;
4102 u32 rates[(MAX_SUPPORTED_RATES / 4) + 1];
4106 u32 tlv_header;
4107 u32 rx_max_rate;
4108 u32 rx_mcs_set;
4109 u32 tx_max_rate;
4110 u32 tx_mcs_set;
4111 u32 tx_max_mcs_nss;
4115 u32 tlv_header;
4118 u32 rx_mcs_set;
4121 u32 tx_mcs_set;
4134 u32 vdev_id;
4135 u32 requestor_id;
4137 u32 status;
4138 u32 chain_mask;
4139 u32 smps_mode;
4141 u32 mac_id;
4142 u32 pdev_id;
4144 u32 cfgd_tx_streams;
4145 u32 cfgd_rx_streams;
4398 u32 dfs_region;
4399 u32 phybitmap;
4400 u32 min_bw_2ghz;
4401 u32 max_bw_2ghz;
4402 u32 min_bw_5ghz;
4403 u32 max_bw_5ghz;
4404 u32 num_2ghz_reg_rules;
4405 u32 num_5ghz_reg_rules;
4414 u32 domain_code_6ghz_super_id;
4415 u32 min_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
4416 u32 max_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
4417 u32 min_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4418 u32 max_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4419 u32 num_6ghz_rules_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
4420 u32 num_6ghz_rules_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4427 u32 status_code;
4428 u32 phy_id;
4429 u32 alpha2;
4430 u32 num_phy;
4431 u32 country_id;
4432 u32 domain_code;
4433 u32 dfs_region;
4434 u32 phybitmap;
4435 u32 min_bw_2ghz;
4436 u32 max_bw_2ghz;
4437 u32 min_bw_5ghz;
4438 u32 max_bw_5ghz;
4439 u32 num_2ghz_reg_rules;
4440 u32 num_5ghz_reg_rules;
4444 u32 tlv_header;
4445 u32 freq_info;
4446 u32 bw_pwr_info;
4447 u32 flag_info;
4453 u32 status_code;
4454 u32 phy_id;
4455 u32 alpha2;
4456 u32 num_phy;
4457 u32 country_id;
4458 u32 domain_code;
4459 u32 dfs_region;
4460 u32 phybitmap;
4461 u32 min_bw_2ghz;
4462 u32 max_bw_2ghz;
4463 u32 min_bw_5ghz;
4464 u32 max_bw_5ghz;
4465 u32 num_2ghz_reg_rules;
4466 u32 num_5ghz_reg_rules;
4467 u32 client_type;
4468 u32 rnr_tpe_usable;
4469 u32 unspecified_ap_usable;
4470 u32 domain_code_6ghz_ap_lpi;
4471 u32 domain_code_6ghz_ap_sp;
4472 u32 domain_code_6ghz_ap_vlp;
4473 u32 domain_code_6ghz_client_lpi[WMI_REG_CLIENT_MAX];
4474 u32 domain_code_6ghz_client_sp[WMI_REG_CLIENT_MAX];
4475 u32 domain_code_6ghz_client_vlp[WMI_REG_CLIENT_MAX];
4476 u32 domain_code_6ghz_super_id;
4477 u32 min_bw_6ghz_ap_sp;
4478 u32 max_bw_6ghz_ap_sp;
4479 u32 min_bw_6ghz_ap_lpi;
4480 u32 max_bw_6ghz_ap_lpi;
4481 u32 min_bw_6ghz_ap_vlp;
4482 u32 max_bw_6ghz_ap_vlp;
4483 u32 min_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX];
4484 u32 max_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX];
4485 u32 min_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX];
4486 u32 max_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX];
4487 u32 min_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX];
4488 u32 max_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX];
4489 u32 num_6ghz_reg_rules_ap_sp;
4490 u32 num_6ghz_reg_rules_ap_lpi;
4491 u32 num_6ghz_reg_rules_ap_vlp;
4492 u32 num_6ghz_reg_rules_client_sp[WMI_REG_CLIENT_MAX];
4493 u32 num_6ghz_reg_rules_client_lpi[WMI_REG_CLIENT_MAX];
4494 u32 num_6ghz_reg_rules_client_vlp[WMI_REG_CLIENT_MAX];
4498 u32 tlv_header;
4499 u32 freq_info;
4500 u32 bw_pwr_info;
4501 u32 flag_info;
4502 u32 psd_power_info;
4506 u32 vdev_id;
4510 u32 vdev_id;
4515 u32 vdev_id;
4516 u32 tx_status;
4520 u32 vdev_id;
4524 u32 freq; /* Units in MHz */
4525 u32 noise_floor; /* units are dBm */
4527 u32 rx_clear_count_low;
4528 u32 rx_clear_count_high;
4530 u32 cycle_count_low;
4531 u32 cycle_count_high;
4533 u32 tx_cycle_count_low;
4534 u32 tx_cycle_count_high;
4536 u32 rx_cycle_count_low;
4537 u32 rx_cycle_count_high;
4539 u32 rx_bss_cycle_count_low;
4540 u32 rx_bss_cycle_count_high;
4541 u32 pdev_id;
4547 u32 vdev_id;
4549 u32 key_idx;
4550 u32 key_flags;
4551 u32 status;
4555 u32 vdev_id;
4557 u32 key_idx;
4558 u32 key_flags;
4559 u32 status;
4563 u32 vdev_id;
4568 u32 vdev_id;
4573 u32 vdev_id;
4574 u32 fils_tt;
4575 u32 tbtt;
4579 u32 vdev_id;
4580 u32 tx_status;
4588 u32 tx_frame_count; /* Cycles spent transmitting frames */
4589 u32 rx_frame_count; /* Cycles spent receiving frames */
4590 u32 rx_clear_count; /* Total channel busy time, evidently */
4591 u32 cycle_count; /* Total on-channel time */
4592 u32 phy_err_count;
4593 u32 chan_tx_pwr;
4597 u32 ack_rx_bad;
4598 u32 rts_bad;
4599 u32 rts_good;
4600 u32 fcs_bad;
4601 u32 no_beacons;
4602 u32 mib_int_count;
4637 u32 hw_paused;
4646 u32 tx_ko;
4648 u32 tx_xretry;
4651 u32 data_rc;
4654 u32 self_triggers;
4657 u32 sw_retry_failure;
4660 u32 illgl_rate_phy_err;
4663 u32 pdev_cont_xretry;
4666 u32 pdev_tx_timeout;
4669 u32 pdev_resets;
4672 u32 stateless_tid_alloc_failure;
4675 u32 phy_underrun;
4678 u32 txop_ovf;
4681 u32 seq_posted;
4684 u32 seq_failed_queueing;
4687 u32 seq_completed;
4690 u32 seq_restarted;
4693 u32 mu_seq_posted;
4763 u32 vdev_id;
4764 u32 beacon_snr;
4765 u32 data_snr;
4766 u32 num_tx_frames[WLAN_MAX_AC];
4767 u32 num_rx_frames;
4768 u32 num_tx_frames_retries[WLAN_MAX_AC];
4769 u32 num_tx_frames_failures[WLAN_MAX_AC];
4770 u32 num_rts_fail;
4771 u32 num_rts_success;
4772 u32 num_rx_err;
4773 u32 num_rx_discard;
4774 u32 num_tx_not_acked;
4775 u32 tx_rate_history[MAX_TX_RATE_VALUES];
4776 u32 beacon_rssi_history[MAX_TX_RATE_VALUES];
4780 u32 vdev_id;
4781 u32 tx_bcn_succ_cnt;
4782 u32 tx_bcn_outage_cnt;
4786 u32 stats_id;
4787 u32 num_pdev_stats;
4788 u32 num_vdev_stats;
4789 u32 num_peer_stats;
4790 u32 num_bcnflt_stats;
4791 u32 num_chan_stats;
4792 u32 num_mib_stats;
4793 u32 pdev_id;
4794 u32 num_bcn_stats;
4795 u32 num_peer_extd_stats;
4796 u32 num_peer_extd2_stats;
4800 u32 vdev_id;
4801 u32 rssi_avg_beacon[WMI_MAX_CHAINS];
4802 u32 rssi_avg_data[WMI_MAX_CHAINS];
4807 u32 num_per_chain_rssi_stats;
4811 u32 pdev_id;
4812 u32 ctl_failsafe_status;
4816 u32 pdev_id;
4817 u32 current_switch_count;
4818 u32 num_vdevs;
4822 u32 pdev_id;
4823 u32 detection_mode;
4824 u32 chan_freq;
4825 u32 chan_width;
4826 u32 detector_id;
4827 u32 segment_id;
4828 u32 timestamp;
4829 u32 is_chirp;
4837 u32 pdev_id;
4849 u32 chan_freq;
4850 u32 channel;
4851 u32 snr;
4853 u32 rate;
4855 u32 buf_len;
4857 u32 flags;
4859 u32 tsf_delta;
4866 u32 channel;
4867 u32 snr;
4868 u32 rate;
4869 u32 phy_mode;
4870 u32 buf_len;
4871 u32 status;
4872 u32 rssi_ctl[ATH_MAX_ANTENNA];
4873 u32 flags;
4875 u32 tsf_delta;
4876 u32 rx_tsf_l32;
4877 u32 rx_tsf_u32;
4878 u32 pdev_id;
4879 u32 chan_freq;
4885 u32 tlv_header;
4886 u32 rssi_ctl_ext[MAX_ANTENNA_EIGHT - ATH_MAX_ANTENNA];
4890 u32 desc_id;
4891 u32 status;
4892 u32 pdev_id;
4893 u32 ppdu_id;
4894 u32 ack_rssi;
4898 u32 event_type; /* %WMI_SCAN_EVENT_ */
4899 u32 reason; /* %WMI_SCAN_REASON_ */
4900 u32 channel_freq; /* only valid for WMI_SCAN_EVENT_FOREIGN_CHANNEL */
4901 u32 scan_req_id;
4902 u32 scan_id;
4903 u32 vdev_id;
4909 u32 tsf_timestamp;
4932 u32 vdev_id;
4933 u32 reason;
4934 u32 rssi;
4941 u32 err_code;
4942 u32 freq;
4943 u32 cmd_flags;
4944 u32 noise_floor;
4945 u32 rx_clear_count;
4946 u32 cycle_count;
4947 u32 chan_tx_pwr_range;
4948 u32 chan_tx_pwr_tp;
4949 u32 rx_frame_count;
4950 u32 my_bss_rx_cycle_count;
4951 u32 rx_11b_mode_data_duration;
4952 u32 tx_frame_cnt;
4953 u32 mac_clk_mhz;
4954 u32 vdev_id;
4958 u32 phy_capability;
4959 u32 max_frag_entry;
4960 u32 num_rf_chains;
4961 u32 ht_cap_info;
4962 u32 vht_cap_info;
4963 u32 vht_supp_mcs;
4964 u32 hw_min_tx_power;
4965 u32 hw_max_tx_power;
4966 u32 sys_cap_info;
4967 u32 min_pkt_size_enable;
4968 u32 max_bcn_ie_size;
4969 u32 max_num_scan_channels;
4970 u32 max_supported_macs;
4971 u32 wmi_fw_sub_feat_caps;
4972 u32 txrx_chainmask;
4973 u32 default_dbs_hw_mode_index;
4974 u32 num_msdu_desc;
5023 u32 wmm_ac;
5024 u32 user_priority;
5025 u32 service_interval;
5026 u32 suspend_interval;
5027 u32 delay_interval;
5031 u32 vdev_id;
5033 u32 num_ac;
5037 u32 wmm_ac;
5038 u32 user_priority;
5039 u32 service_interval;
5040 u32 suspend_interval;
5041 u32 delay_interval;
5205 u32 eeprom_rd;
5206 u32 eeprom_rd_ext;
5207 u32 regcap1;
5208 u32 regcap2;
5209 u32 wireless_modes;
5210 u32 low_2ghz_chan;
5211 u32 high_2ghz_chan;
5212 u32 low_5ghz_chan;
5213 u32 high_5ghz_chan;
5219 u32 len;
5220 u32 req_id;
5240 u32 tlv_header;
5241 u32 cwmin;
5242 u32 cwmax;
5243 u32 aifs;
5244 u32 txoplimit;
5245 u32 acm;
5246 u32 no_ack;
5259 u32 tlv_header;
5260 u32 vdev_id;
5262 u32 wmm_param_type;
5289 u32 sta_cong_timer_ms;
5290 u32 mbss_support;
5291 u32 default_slot_size;
5292 u32 congestion_thresh_setup;
5293 u32 congestion_thresh_teardown;
5294 u32 congestion_thresh_critical;
5295 u32 interference_thresh_teardown;
5296 u32 interference_thresh_setup;
5297 u32 min_no_sta_setup;
5298 u32 min_no_sta_teardown;
5299 u32 no_of_bcast_mcast_slots;
5300 u32 min_no_twt_slots;
5301 u32 max_no_sta_twt;
5302 u32 mode_check_interval;
5303 u32 add_sta_slot_interval;
5304 u32 remove_sta_slot_interval;
5308 u32 tlv_header;
5309 u32 pdev_id;
5310 u32 sta_cong_timer_ms;
5311 u32 mbss_support;
5312 u32 default_slot_size;
5313 u32 congestion_thresh_setup;
5314 u32 congestion_thresh_teardown;
5315 u32 congestion_thresh_critical;
5316 u32 interference_thresh_teardown;
5317 u32 interference_thresh_setup;
5318 u32 min_no_sta_setup;
5319 u32 min_no_sta_teardown;
5320 u32 no_of_bcast_mcast_slots;
5321 u32 min_no_twt_slots;
5322 u32 max_no_sta_twt;
5323 u32 mode_check_interval;
5324 u32 add_sta_slot_interval;
5325 u32 remove_sta_slot_interval;
5329 u32 tlv_header;
5330 u32 pdev_id;
5350 u32 tlv_header;
5351 u32 vdev_id;
5353 u32 dialog_id;
5354 u32 wake_intvl_us;
5355 u32 wake_intvl_mantis;
5356 u32 wake_dura_us;
5357 u32 sp_offset_us;
5358 u32 flags;
5362 u32 vdev_id;
5364 u32 dialog_id;
5365 u32 wake_intvl_us;
5366 u32 wake_intvl_mantis;
5367 u32 wake_dura_us;
5368 u32 sp_offset_us;
5390 u32 vdev_id;
5392 u32 dialog_id;
5393 u32 status;
5397 u32 vdev_id;
5399 u32 dialog_id;
5403 u32 tlv_header;
5404 u32 vdev_id;
5406 u32 dialog_id;
5410 u32 vdev_id;
5412 u32 dialog_id;
5416 u32 tlv_header;
5417 u32 vdev_id;
5419 u32 dialog_id;
5423 u32 vdev_id;
5425 u32 dialog_id;
5426 u32 sp_offset_us;
5427 u32 next_twt_size;
5431 u32 tlv_header;
5432 u32 vdev_id;
5434 u32 dialog_id;
5435 u32 sp_offset_us;
5436 u32 next_twt_size;
5440 u32 tlv_header;
5441 u32 pdev_id;
5442 u32 enable;
5445 u32 vdev_id;
5449 u32 tlv_header;
5450 u32 pdev_id;
5451 u32 bitmap[2];
5469 u32 tlv_header;
5470 u32 vdev_id;
5471 u32 flags;
5472 u32 evt_type;
5473 u32 current_bss_color;
5474 u32 detection_period_ms;
5475 u32 scan_period_ms;
5476 u32 free_slot_expiry_time_ms;
5480 u32 tlv_header;
5481 u32 vdev_id;
5482 u32 enable;
5486 u32 vdev_id;
5487 u32 evt_type;
5495 u32 tlv_header;
5496 u32 lro_enable;
5497 u32 res;
5498 u32 th_4[ATH11K_IPV4_TH_SEED_SIZE];
5499 u32 th_6[ATH11K_IPV6_TH_SEED_SIZE];
5500 u32 pdev_id;
5523 u32 vdev_id;
5524 u32 scan_count;
5525 u32 scan_period;
5526 u32 scan_priority;
5527 u32 scan_fft_size;
5528 u32 scan_gc_ena;
5529 u32 scan_restart_ena;
5530 u32 scan_noise_floor_ref;
5531 u32 scan_init_delay;
5532 u32 scan_nb_tone_thr;
5533 u32 scan_str_bin_thr;
5534 u32 scan_wb_rpt_mode;
5535 u32 scan_rssi_rpt_mode;
5536 u32 scan_rssi_thr;
5537 u32 scan_pwr_format;
5538 u32 scan_rpt_mode;
5539 u32 scan_bin_scale;
5540 u32 scan_dbm_adj;
5541 u32 scan_chn_mask;
5545 u32 tlv_header;
5555 u32 tlv_header;
5556 u32 vdev_id;
5557 u32 trigger_cmd;
5558 u32 enable_cmd;
5562 u32 tlv_header;
5563 u32 pdev_id;
5564 u32 module_id; /* see enum wmi_direct_buffer_module */
5565 u32 base_paddr_lo;
5566 u32 base_paddr_hi;
5567 u32 head_idx_paddr_lo;
5568 u32 head_idx_paddr_hi;
5569 u32 tail_idx_paddr_lo;
5570 u32 tail_idx_paddr_hi;
5571 u32 num_elems; /* Number of elems in the ring */
5572 u32 buf_size; /* size of allocated buffer in bytes */
5575 u32 num_resp_per_event;
5580 u32 event_timeout_ms;
5584 u32 pdev_id;
5585 u32 module_id;
5586 u32 num_buf_release_entry;
5587 u32 num_meta_data_entry;
5591 u32 tlv_header;
5592 u32 paddr_lo;
5597 u32 paddr_hi;
5606 u32 tlv_header;
5608 u32 reset_delay;
5609 u32 freq1;
5610 u32 freq2;
5611 u32 ch_width;
5620 u32 tlv_header;
5621 u32 vdev_id;
5622 u32 interval;
5623 u32 config; /* enum wmi_fils_discovery_cmd_type */
5627 u32 tlv_header;
5628 u32 vdev_id;
5629 u32 buf_len;
5633 u32 tlv_header;
5634 u32 vdev_id;
5635 u32 buf_len;
5639 u32 num_vdevs;
5640 u32 num_peers;
5641 u32 num_active_peers;
5642 u32 num_offload_peers;
5643 u32 num_offload_reorder_buffs;
5644 u32 num_peer_keys;
5645 u32 num_tids;
5646 u32 ast_skid_limit;
5647 u32 tx_chain_mask;
5648 u32 rx_chain_mask;
5649 u32 rx_timeout_pri[4];
5650 u32 rx_decap_mode;
5651 u32 scan_max_pending_req;
5652 u32 bmiss_offload_max_vdev;
5653 u32 roam_offload_max_vdev;
5654 u32 roam_offload_max_ap_profiles;
5655 u32 num_mcast_groups;
5656 u32 num_mcast_table_elems;
5657 u32 mcast2ucast_mode;
5658 u32 tx_dbg_log_size;
5659 u32 num_wds_entries;
5660 u32 dma_burst_size;
5661 u32 mac_aggr_delim;
5662 u32 rx_skip_defrag_timeout_dup_detection_check;
5663 u32 vow_config;
5664 u32 gtk_offload_max_vdev;
5665 u32 num_msdu_desc;
5666 u32 max_frag_entries;
5667 u32 max_peer_ext_stats;
5668 u32 smart_ant_cap;
5669 u32 bk_minfree;
5670 u32 be_minfree;
5671 u32 vi_minfree;
5672 u32 vo_minfree;
5673 u32 rx_batchmode;
5674 u32 tt_support;
5675 u32 flag1;
5676 u32 iphdr_pad_config;
5677 u32 qwrap_config:16,
5679 u32 num_tdls_vdevs;
5680 u32 num_tdls_conn_table_entries;
5681 u32 beacon_tx_offload_max_vdev;
5682 u32 num_multicast_filter_entries;
5683 u32 num_wow_filters;
5684 u32 num_keep_alive_pattern;
5685 u32 keep_alive_pattern_size;
5686 u32 max_tdls_concurrent_sleep_sta;
5687 u32 max_tdls_concurrent_buffer_sta;
5688 u32 wmi_send_separate;
5689 u32 num_ocb_vdevs;
5690 u32 num_ocb_channels;
5691 u32 num_ocb_schedules;
5692 u32 num_ns_ext_tuples_cfg;
5693 u32 bpf_instruction_size;
5694 u32 max_bssid_rx_filters;
5695 u32 use_pdev_id;
5696 u32 peer_map_unmap_v2_support;
5697 u32 sched_params;
5698 u32 twt_ap_pdev_count;
5699 u32 twt_ap_sta_count;
5701 u32 ema_max_vap_cnt;
5702 u32 ema_max_profile_period;
5715 u32 tlv_header;
5716 u32 dbg_log_param;
5717 u32 value;
5741 u32 peer_ps_state;
5742 u32 ps_supported_bitmap;
5743 u32 peer_ps_valid;
5744 u32 peer_ps_timestamp;
5751 u32 max_msg_len[MAX_RADIOS];
5758 u32 num_mem_chunks;
5759 u32 rx_decap_mode;
5775 u32 tlv_header;
5776 u32 vdev_id;
5777 u32 enable;
5778 u32 hw_filter_bitmap;
5926 u32 vdev_id;
5927 u32 flag;
5929 u32 data_len;
5958 u32 tlv_header;
5959 u32 vdev_id;
5960 u32 is_add;
5961 u32 event_bitmap;
5965 u32 tlv_header;
5966 u32 enable;
5967 u32 pause_iface_config;
5968 u32 flags;
5972 u32 tlv_header;
5973 u32 reserved;
5977 u32 vdev_id;
5978 u32 flag;
5979 u32 wake_reason;
5980 u32 data_len;
5984 u32 tlv_header;
5987 u32 pattern_offset;
5988 u32 pattern_len;
5989 u32 bitmask_len;
5990 u32 pattern_id;
5994 u32 tlv_header;
5995 u32 vdev_id;
5996 u32 pattern_id;
5997 u32 pattern_type;
6001 u32 tlv_header;
6002 u32 vdev_id;
6003 u32 pattern_id;
6004 u32 pattern_type;
6053 u32 valid;
6058 u32 valid;
6059 u32 enc_type;
6063 u32 valid;
6064 u32 auth_type;
6068 u32 valid;
6069 u32 bcast_nw_type;
6073 u32 valid;
6079 u32 tlv_header;
6091 u32 authentication;
6092 u32 encryption;
6093 u32 bcast_nw_type;
6104 u32 fast_scan_period;
6105 u32 slow_scan_period;
6110 u32 delay_start_time;
6111 u32 active_min_time;
6112 u32 active_max_time;
6113 u32 passive_min_time;
6114 u32 passive_max_time;
6117 u32 enable_pno_scan_randomization;
6123 u32 tlv_header;
6124 u32 flags;
6125 u32 vdev_id;
6126 u32 fast_scan_max_cycles;
6127 u32 active_dwell_time;
6128 u32 passive_dwell_time;
6129 u32 probe_bundle_size;
6132 u32 rest_time;
6135 u32 max_rest_time;
6138 u32 scan_backoff_multiplier;
6141 u32 fast_scan_period;
6144 u32 slow_scan_period;
6146 u32 no_of_ssids;
6148 u32 num_of_channels;
6151 u32 delay_start_time;
6160 u32 ie_bitmap[8];
6163 u32 num_vendor_oui;
6166 u32 num_cnlo_band_pref;
6182 u32 tlv_header;
6183 u32 flags;
6197 u32 tlv_header;
6198 u32 flags;
6206 u32 tlv_header;
6207 u32 flags;
6208 u32 vdev_id;
6209 u32 num_ns_ext_tuples;
6232 u32 word0;
6233 u32 word1;
6239 u32 vdev_id;
6240 u32 flags;
6241 u32 refresh_cnt;
6254 u32 tlv_header;
6255 u32 vdev_id;
6256 u32 flags;
6267 u32 tlv_header;
6268 u32 pdev_id;
6269 u32 sar_len;
6270 u32 rsvd_len;
6274 u32 tlv_header;
6275 u32 pdev_id;
6276 u32 rsvd_len;
6280 u32 tlv_header;
6281 u32 vdev_id;
6282 u32 enabled;
6285 u32 method;
6288 u32 interval;
6296 u32 tlv_header;
6297 u32 src_ip4_addr;
6298 u32 dest_ip4_addr;
6303 u32 vdev_id;
6304 u32 enabled;
6305 u32 method;
6306 u32 interval;
6307 u32 src_ip4_addr;
6308 u32 dest_ip4_addr;
6326 u32 cmd_id);
6327 struct sk_buff *ath11k_wmi_alloc_skb(struct ath11k_wmi_base *wmi_sc, u32 len);
6328 int ath11k_wmi_mgmt_send(struct ath11k *ar, u32 vdev_id, u32 buf_id,
6330 int ath11k_wmi_bcn_tmpl(struct ath11k *ar, u32 vdev_id,
6332 struct sk_buff *bcn, u32 ema_param);
6334 int ath11k_wmi_vdev_up(struct ath11k *ar, u32 vdev_id, u32 aid,
6335 const u8 *bssid, u8 *tx_bssid, u32 nontx_profile_idx,
6336 u32 nontx_profile_cnt);
6341 u32 vdev_id, u32 param_id, u32 param_val);
6342 int ath11k_wmi_pdev_set_param(struct ath11k *ar, u32 param_id,
6343 u32 param_value, u8 pdev_id);
6359 u32 ba_window_size);
6362 int ath11k_wmi_vdev_set_param_cmd(struct ath11k *ar, u32 vdev_id,
6363 u32 param_id, u32 param_value);
6365 int ath11k_wmi_set_sta_ps_param(struct ath11k *ar, u32 vdev_id,
6366 u32 param, u32 param_value);
6367 int ath11k_wmi_force_fw_hang_cmd(struct ath11k *ar, u32 type, u32 delay_time_ms);
6376 int ath11k_wmi_send_wmm_update_cmd_tlv(struct ath11k *ar, u32 vdev_id,
6378 int ath11k_wmi_pdev_suspend(struct ath11k *ar, u32 suspend_opt,
6379 u32 pdev_id);
6380 int ath11k_wmi_pdev_resume(struct ath11k *ar, u32 pdev_id);
6399 u32 pdev_id);
6400 int ath11k_wmi_addba_clear_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac);
6401 int ath11k_wmi_addba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac,
6402 u32 tid, u32 buf_size);
6403 int ath11k_wmi_addba_set_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac,
6404 u32 tid, u32 status);
6405 int ath11k_wmi_delba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac,
6406 u32 tid, u32 initiator, u32 reason);
6408 u32 vdev_id, u32 bcn_ctrl_op);
6417 int ath11k_wmi_send_11d_scan_stop_cmd(struct ath11k *ar, u32 vdev_id);
6422 int ath11k_wmi_pdev_pktlog_enable(struct ath11k *ar, u32 pktlog_filter);
6433 struct ath11k_fw_stats *fw_stats, u32 stats_id,
6437 int ath11k_wmi_send_twt_enable_cmd(struct ath11k *ar, u32 pdev_id,
6439 int ath11k_wmi_send_twt_disable_cmd(struct ath11k *ar, u32 pdev_id);
6448 int ath11k_wmi_send_obss_spr_cmd(struct ath11k *ar, u32 vdev_id,
6450 int ath11k_wmi_pdev_set_srg_bss_color_bitmap(struct ath11k *ar, u32 *bitmap);
6451 int ath11k_wmi_pdev_set_srg_patial_bssid_bitmap(struct ath11k *ar, u32 *bitmap);
6453 u32 *bitmap);
6455 u32 *bitmap);
6457 u32 *bitmap);
6459 u32 *bitmap);
6460 int ath11k_wmi_send_obss_color_collision_cfg_cmd(struct ath11k *ar, u32 vdev_id,
6461 u8 bss_color, u32 period,
6463 int ath11k_wmi_send_bss_color_change_enable_cmd(struct ath11k *ar, u32 vdev_id,
6468 int ath11k_wmi_vdev_spectral_enable(struct ath11k *ar, u32 vdev_id,
6469 u32 trigger, u32 enable);
6472 int ath11k_wmi_fils_discovery_tmpl(struct ath11k *ar, u32 vdev_id,
6474 int ath11k_wmi_fils_discovery(struct ath11k *ar, u32 vdev_id, u32 interval,
6476 int ath11k_wmi_probe_resp_tmpl(struct ath11k *ar, u32 vdev_id,
6484 int ath11k_wmi_fw_dbglog_cfg(struct ath11k *ar, u32 *module_id_bitmap,
6486 int ath11k_wmi_wow_config_pno(struct ath11k *ar, u32 vdev_id,
6488 int ath11k_wmi_wow_del_pattern(struct ath11k *ar, u32 vdev_id, u32 pattern_id);
6489 int ath11k_wmi_wow_add_pattern(struct ath11k *ar, u32 vdev_id, u32 pattern_id,
6492 int ath11k_wmi_wow_add_wakeup_event(struct ath11k *ar, u32 vdev_id,
6494 u32 enable);
6495 int ath11k_wmi_hw_data_filter_cmd(struct ath11k *ar, u32 vdev_id,
6496 u32 filter_bitmap, bool enable);