31 	(offs[slice].ft1_slot_base + FT1_SLOT_SIZE * (n) + (reg))
66 	(offs[slice].ft3_slot_base + FT3_SLOT_SIZE * (n) + (reg))
74 #define RX_CLASS_N_REG(slice, n, reg)	\  argument
75 	(offs[slice].rx_class_base + RX_CLASS_EN_SIZE * (n) + (reg))
80 #define RX_CLASS_GATES_N_REG(slice, n)	\  argument
81 	(offs[slice].rx_class_gates_base + RX_CLASS_GATES_SIZE * (n))
205 static void rx_class_ft1_set_start_len(struct regmap *miig_rt, int slice,  in rx_class_ft1_set_start_len()  argument
210 	offset = offs[slice].ft1_start_len;  in rx_class_ft1_set_start_len()
215 static void rx_class_ft1_set_da(struct regmap *miig_rt, int slice,  in rx_class_ft1_set_da()  argument
220 	offset = FT1_N_REG(slice, n, FT1_DA0);  in rx_class_ft1_set_da()
223 	offset = FT1_N_REG(slice, n, FT1_DA1);  in rx_class_ft1_set_da()
227 static void rx_class_ft1_set_da_mask(struct regmap *miig_rt, int slice,  in rx_class_ft1_set_da_mask()  argument
232 	offset = FT1_N_REG(slice, n, FT1_DA0_MASK);  in rx_class_ft1_set_da_mask()
235 	offset = FT1_N_REG(slice, n, FT1_DA1_MASK);  in rx_class_ft1_set_da_mask()
239 static void rx_class_ft1_cfg_set_type(struct regmap *miig_rt, int slice, int n,  in rx_class_ft1_cfg_set_type()  argument
244 	offset = offs[slice].ft1_cfg;  in rx_class_ft1_cfg_set_type()
249 static void rx_class_sel_set_type(struct regmap *miig_rt, int slice, int n,  in rx_class_sel_set_type()  argument
254 	offset = offs[slice].rx_class_cfg1;  in rx_class_sel_set_type()
259 static void rx_class_set_and(struct regmap *miig_rt, int slice, int n,  in rx_class_set_and()  argument
264 	offset = RX_CLASS_N_REG(slice, n, RX_CLASS_AND_EN);  in rx_class_set_and()
268 static void rx_class_set_or(struct regmap *miig_rt, int slice, int n,  in rx_class_set_or()  argument
273 	offset = RX_CLASS_N_REG(slice, n, RX_CLASS_OR_EN);  in rx_class_set_or()
284 void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac)  in icssg_class_set_mac_addr()  argument
286 	regmap_write(miig_rt, offs[slice].mac0, (u32)(mac[0] | mac[1] << 8 |  in icssg_class_set_mac_addr()
288 	regmap_write(miig_rt, offs[slice].mac1, (u32)(mac[4] | mac[5] << 8));  in icssg_class_set_mac_addr()
292 void icssg_class_disable(struct regmap *miig_rt, int slice)  in icssg_class_disable()  argument
303 		rx_class_set_and(miig_rt, slice, n, 0);  in icssg_class_disable()
305 		rx_class_set_or(miig_rt, slice, n, 0);  in icssg_class_disable()
308 		rx_class_sel_set_type(miig_rt, slice, n, RX_CLASS_SEL_TYPE_OR);  in icssg_class_disable()
311 		offset = RX_CLASS_GATES_N_REG(slice, n);  in icssg_class_disable()
324 		rx_class_ft1_cfg_set_type(miig_rt, slice, n,  in icssg_class_disable()
326 		rx_class_ft1_set_da(miig_rt, slice, n, addr);  in icssg_class_disable()
327 		rx_class_ft1_set_da_mask(miig_rt, slice, n, addr);  in icssg_class_disable()
331 	regmap_write(miig_rt, offs[slice].rx_class_cfg2, 0);  in icssg_class_disable()
334 void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti)  in icssg_class_default()  argument
339 	icssg_class_disable(miig_rt, slice);  in icssg_class_default()
349 	rx_class_set_or(miig_rt, slice, 0, data);  in icssg_class_default()
352 	rx_class_sel_set_type(miig_rt, slice, 0, RX_CLASS_SEL_TYPE_OR_OR_AND);  in icssg_class_default()
355 	regmap_write(miig_rt, offs[slice].rx_class_cfg2, 0);  in icssg_class_default()
359 void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr)  in icssg_ft1_set_mac_addr()  argument
363 	rx_class_ft1_set_start_len(miig_rt, slice, 0, 6);  in icssg_ft1_set_mac_addr()
364 	rx_class_ft1_set_da(miig_rt, slice, 0, mac_addr);  in icssg_ft1_set_mac_addr()
365 	rx_class_ft1_set_da_mask(miig_rt, slice, 0, mask_addr);  in icssg_ft1_set_mac_addr()
366 	rx_class_ft1_cfg_set_type(miig_rt, slice, 0, FT1_CFG_TYPE_EQ);  in icssg_ft1_set_mac_addr()