Lines Matching refs:value
13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset() local
16 writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset()
18 return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value, in dwxgmac2_dma_reset()
19 !(value & XGMAC_SWR), 0, 100000); in dwxgmac2_dma_reset()
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init() local
28 value |= XGMAC_AAL; in dwxgmac2_dma_init()
31 value |= XGMAC_EAME; in dwxgmac2_dma_init()
33 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init()
40 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan() local
43 value |= XGMAC_PBLx8; in dwxgmac2_dma_init_chan()
45 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan()
55 u32 value; in dwxgmac2_dma_init_rx_chan() local
57 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_init_rx_chan()
58 value &= ~XGMAC_RxPBL; in dwxgmac2_dma_init_rx_chan()
59 value |= (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL; in dwxgmac2_dma_init_rx_chan()
60 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_init_rx_chan()
72 u32 value; in dwxgmac2_dma_init_tx_chan() local
74 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_init_tx_chan()
75 value &= ~XGMAC_TxPBL; in dwxgmac2_dma_init_tx_chan()
76 value |= (txpbl << XGMAC_TxPBL_SHIFT) & XGMAC_TxPBL; in dwxgmac2_dma_init_tx_chan()
77 value |= XGMAC_OSP; in dwxgmac2_dma_init_tx_chan()
78 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_init_tx_chan()
86 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_axi() local
90 value |= XGMAC_EN_LPI; in dwxgmac2_dma_axi()
92 value |= XGMAC_LPI_XIT_PKT; in dwxgmac2_dma_axi()
94 value &= ~XGMAC_WR_OSR_LMT; in dwxgmac2_dma_axi()
95 value |= (axi->axi_wr_osr_lmt << XGMAC_WR_OSR_LMT_SHIFT) & in dwxgmac2_dma_axi()
98 value &= ~XGMAC_RD_OSR_LMT; in dwxgmac2_dma_axi()
99 value |= (axi->axi_rd_osr_lmt << XGMAC_RD_OSR_LMT_SHIFT) & in dwxgmac2_dma_axi()
103 value |= XGMAC_UNDEF; in dwxgmac2_dma_axi()
105 value &= ~XGMAC_BLEN; in dwxgmac2_dma_axi()
109 value |= XGMAC_BLEN256; in dwxgmac2_dma_axi()
112 value |= XGMAC_BLEN128; in dwxgmac2_dma_axi()
115 value |= XGMAC_BLEN64; in dwxgmac2_dma_axi()
118 value |= XGMAC_BLEN32; in dwxgmac2_dma_axi()
121 value |= XGMAC_BLEN16; in dwxgmac2_dma_axi()
124 value |= XGMAC_BLEN8; in dwxgmac2_dma_axi()
127 value |= XGMAC_BLEN4; in dwxgmac2_dma_axi()
132 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_axi()
149 u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); in dwxgmac2_dma_rx_mode() local
153 value |= XGMAC_RSF; in dwxgmac2_dma_rx_mode()
155 value &= ~XGMAC_RSF; in dwxgmac2_dma_rx_mode()
156 value &= ~XGMAC_RTC; in dwxgmac2_dma_rx_mode()
159 value |= 0x0 << XGMAC_RTC_SHIFT; in dwxgmac2_dma_rx_mode()
161 value |= 0x2 << XGMAC_RTC_SHIFT; in dwxgmac2_dma_rx_mode()
163 value |= 0x3 << XGMAC_RTC_SHIFT; in dwxgmac2_dma_rx_mode()
166 value &= ~XGMAC_RQS; in dwxgmac2_dma_rx_mode()
167 value |= (rqs << XGMAC_RQS_SHIFT) & XGMAC_RQS; in dwxgmac2_dma_rx_mode()
173 value |= XGMAC_EHFC; in dwxgmac2_dma_rx_mode()
205 writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); in dwxgmac2_dma_rx_mode()
208 value = readl(ioaddr + XGMAC_MTL_QINTEN(channel)); in dwxgmac2_dma_rx_mode()
209 writel(value | XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel)); in dwxgmac2_dma_rx_mode()
215 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_dma_tx_mode() local
219 value |= XGMAC_TSF; in dwxgmac2_dma_tx_mode()
221 value &= ~XGMAC_TSF; in dwxgmac2_dma_tx_mode()
222 value &= ~XGMAC_TTC; in dwxgmac2_dma_tx_mode()
225 value |= 0x0 << XGMAC_TTC_SHIFT; in dwxgmac2_dma_tx_mode()
227 value |= 0x2 << XGMAC_TTC_SHIFT; in dwxgmac2_dma_tx_mode()
229 value |= 0x3 << XGMAC_TTC_SHIFT; in dwxgmac2_dma_tx_mode()
231 value |= 0x4 << XGMAC_TTC_SHIFT; in dwxgmac2_dma_tx_mode()
233 value |= 0x5 << XGMAC_TTC_SHIFT; in dwxgmac2_dma_tx_mode()
235 value |= 0x6 << XGMAC_TTC_SHIFT; in dwxgmac2_dma_tx_mode()
237 value |= 0x7 << XGMAC_TTC_SHIFT; in dwxgmac2_dma_tx_mode()
241 value |= (channel << XGMAC_Q2TCMAP_SHIFT) & XGMAC_Q2TCMAP; in dwxgmac2_dma_tx_mode()
243 value &= ~XGMAC_TXQEN; in dwxgmac2_dma_tx_mode()
245 value |= 0x2 << XGMAC_TXQEN_SHIFT; in dwxgmac2_dma_tx_mode()
247 value |= 0x1 << XGMAC_TXQEN_SHIFT; in dwxgmac2_dma_tx_mode()
249 value &= ~XGMAC_TQS; in dwxgmac2_dma_tx_mode()
250 value |= (tqs << XGMAC_TQS_SHIFT) & XGMAC_TQS; in dwxgmac2_dma_tx_mode()
252 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_dma_tx_mode()
259 u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_enable_dma_irq() local
262 value |= XGMAC_DMA_INT_DEFAULT_RX; in dwxgmac2_enable_dma_irq()
264 value |= XGMAC_DMA_INT_DEFAULT_TX; in dwxgmac2_enable_dma_irq()
266 writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_enable_dma_irq()
273 u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_disable_dma_irq() local
276 value &= ~XGMAC_DMA_INT_DEFAULT_RX; in dwxgmac2_disable_dma_irq()
278 value &= ~XGMAC_DMA_INT_DEFAULT_TX; in dwxgmac2_disable_dma_irq()
280 writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_disable_dma_irq()
286 u32 value; in dwxgmac2_dma_start_tx() local
288 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_start_tx()
289 value |= XGMAC_TXST; in dwxgmac2_dma_start_tx()
290 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_start_tx()
292 value = readl(ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_dma_start_tx()
293 value |= XGMAC_CONFIG_TE; in dwxgmac2_dma_start_tx()
294 writel(value, ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_dma_start_tx()
300 u32 value; in dwxgmac2_dma_stop_tx() local
302 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_stop_tx()
303 value &= ~XGMAC_TXST; in dwxgmac2_dma_stop_tx()
304 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_stop_tx()
306 value = readl(ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_dma_stop_tx()
307 value &= ~XGMAC_CONFIG_TE; in dwxgmac2_dma_stop_tx()
308 writel(value, ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_dma_stop_tx()
314 u32 value; in dwxgmac2_dma_start_rx() local
316 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_start_rx()
317 value |= XGMAC_RXST; in dwxgmac2_dma_start_rx()
318 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_start_rx()
320 value = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_dma_start_rx()
321 value |= XGMAC_CONFIG_RE; in dwxgmac2_dma_start_rx()
322 writel(value, ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_dma_start_rx()
328 u32 value; in dwxgmac2_dma_stop_rx() local
330 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_stop_rx()
331 value &= ~XGMAC_RXST; in dwxgmac2_dma_stop_rx()
332 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_stop_rx()
536 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tso() local
539 value |= XGMAC_TSE; in dwxgmac2_enable_tso()
541 value &= ~XGMAC_TSE; in dwxgmac2_enable_tso()
543 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tso()
549 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_qmode() local
552 value &= ~XGMAC_TXQEN; in dwxgmac2_qmode()
554 value |= 0x2 << XGMAC_TXQEN_SHIFT; in dwxgmac2_qmode()
557 value |= 0x1 << XGMAC_TXQEN_SHIFT; in dwxgmac2_qmode()
561 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_qmode()
567 u32 value; in dwxgmac2_set_bfsize() local
569 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_set_bfsize()
570 value &= ~XGMAC_RBSZ; in dwxgmac2_set_bfsize()
571 value |= bfsize << XGMAC_RBSZ_SHIFT; in dwxgmac2_set_bfsize()
572 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_set_bfsize()
578 u32 value = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_enable_sph() local
580 value &= ~XGMAC_CONFIG_HDSMS; in dwxgmac2_enable_sph()
581 value |= XGMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */ in dwxgmac2_enable_sph()
582 writel(value, ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_enable_sph()
584 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_enable_sph()
586 value |= XGMAC_SPH; in dwxgmac2_enable_sph()
588 value &= ~XGMAC_SPH; in dwxgmac2_enable_sph()
589 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_enable_sph()
595 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tbs() local
598 value |= XGMAC_EDSE; in dwxgmac2_enable_tbs()
600 value &= ~XGMAC_EDSE; in dwxgmac2_enable_tbs()
602 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tbs()
604 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)) & XGMAC_EDSE; in dwxgmac2_enable_tbs()
605 if (en && !value) in dwxgmac2_enable_tbs()