65 #define SMC_IO_SHIFT		(lp->io_shift)
71 		SMC_16BIT(lp) ? readw((a) + __smc_r) :			\
72 		SMC_8BIT(lp) ? SMC_inw_b(a, __smc_r) :			\
78 #define SMC_outw(lp, v, a, r)						\  argument
81 		if (SMC_16BIT(lp))					\
82 			__SMC_outw(lp, __v, a, __smc_r);		\
83 		else if (SMC_8BIT(lp))					\
111 #define __SMC_outw(lp, v, a, r)						\  argument
114 			 (lp)->cfg.pxa_u16_align4)
127 #define SMC_outw(lp, v, a, r)	outw(v, (a) + (r) - 0xa0000000)  argument
147 #define SMC_outw(lp, v, a, r)   writew(v, (a) + (r))  argument
179 #define SMC_outw(lp, v, a, r)	writew(_swapw(v), (a) + (r))  argument
196 #define SMC_IO_SHIFT		(lp->io_shift)
202 #define SMC_outw(lp, v, a, r)	iowrite16(v, (a) + (r))  argument
286 	smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
288 smc_pxa_dma_inpump(struct smc_local *lp, u_char *buf, int len)  in smc_pxa_dma_inpump()  argument
296 	dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);  in smc_pxa_dma_inpump()
297 	tx = dmaengine_prep_slave_single(lp->dma_chan, dmabuf, len,  in smc_pxa_dma_inpump()
301 		dma_async_issue_pending(lp->dma_chan);  in smc_pxa_dma_inpump()
303 			status = dmaengine_tx_status(lp->dma_chan, cookie,  in smc_pxa_dma_inpump()
308 		dmaengine_terminate_all(lp->dma_chan);  in smc_pxa_dma_inpump()
310 	dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);  in smc_pxa_dma_inpump()
314 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,  in smc_pxa_dma_insl()  argument
321 	if (!lp->dma_chan) {  in smc_pxa_dma_insl()
336 	config.src_addr = lp->physaddr + reg;  in smc_pxa_dma_insl()
337 	config.dst_addr = lp->physaddr + reg;  in smc_pxa_dma_insl()
340 	ret = dmaengine_slave_config(lp->dma_chan, &config);  in smc_pxa_dma_insl()
342 		dev_err(lp->device, "dma channel configuration failed: %d\n",  in smc_pxa_dma_insl()
348 	smc_pxa_dma_inpump(lp, buf, len);  in smc_pxa_dma_insl()
355 	smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
357 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,  in smc_pxa_dma_insw()  argument
364 	if (!lp->dma_chan) {  in smc_pxa_dma_insw()
379 	config.src_addr = lp->physaddr + reg;  in smc_pxa_dma_insw()
380 	config.dst_addr = lp->physaddr + reg;  in smc_pxa_dma_insw()
383 	ret = dmaengine_slave_config(lp->dma_chan, &config);  in smc_pxa_dma_insw()
385 		dev_err(lp->device, "dma channel configuration failed: %d\n",  in smc_pxa_dma_insw()
391 	smc_pxa_dma_inpump(lp, buf, len);  in smc_pxa_dma_insw()
419 #define SMC_outw(lp, x, ioaddr, reg)	SMC_outw_b(x, ioaddr, reg)  argument
478 #define TCR_REG(lp) 	SMC_REG(lp, 0x0000, 0)  argument
497 #define EPH_STATUS_REG(lp)	SMC_REG(lp, 0x0002, 0)  argument
516 #define RCR_REG(lp)		SMC_REG(lp, 0x0004, 0)  argument
533 #define COUNTER_REG(lp)	SMC_REG(lp, 0x0006, 0)  argument
538 #define MIR_REG(lp)		SMC_REG(lp, 0x0008, 0)  argument
543 #define RPC_REG(lp)		SMC_REG(lp, 0x000A, 0)  argument
569 #define CONFIG_REG(lp)	SMC_REG(lp, 0x0000,	1)  argument
581 #define BASE_REG(lp)	SMC_REG(lp, 0x0002, 1)  argument
586 #define ADDR0_REG(lp)	SMC_REG(lp, 0x0004, 1)  argument
587 #define ADDR1_REG(lp)	SMC_REG(lp, 0x0006, 1)  argument
588 #define ADDR2_REG(lp)	SMC_REG(lp, 0x0008, 1)  argument
593 #define GP_REG(lp)		SMC_REG(lp, 0x000A, 1)  argument
598 #define CTL_REG(lp)		SMC_REG(lp, 0x000C, 1)  argument
611 #define MMU_CMD_REG(lp)	SMC_REG(lp, 0x0000, 2)  argument
625 #define PN_REG(lp)		SMC_REG(lp, 0x0002, 2)  argument
630 #define AR_REG(lp)		SMC_REG(lp, 0x0003, 2)  argument
636 #define TXFIFO_REG(lp)	SMC_REG(lp, 0x0004, 2)  argument
641 #define RXFIFO_REG(lp)	SMC_REG(lp, 0x0005, 2)  argument
644 #define FIFO_REG(lp)	SMC_REG(lp, 0x0004, 2)  argument
648 #define PTR_REG(lp)		SMC_REG(lp, 0x0006, 2)  argument
656 #define DATA_REG(lp)	SMC_REG(lp, 0x0008, 2)  argument
661 #define INT_REG(lp)		SMC_REG(lp, 0x000C, 2)  argument
666 #define IM_REG(lp)		SMC_REG(lp, 0x000D, 2)  argument
679 #define MCAST_REG1(lp)	SMC_REG(lp, 0x0000, 3)  argument
680 #define MCAST_REG2(lp)	SMC_REG(lp, 0x0002, 3)  argument
681 #define MCAST_REG3(lp)	SMC_REG(lp, 0x0004, 3)  argument
682 #define MCAST_REG4(lp)	SMC_REG(lp, 0x0006, 3)  argument
687 #define MII_REG(lp)		SMC_REG(lp, 0x0008, 3)  argument
698 #define REV_REG(lp)		SMC_REG(lp, 0x000A, 3)  argument
704 #define ERCV_REG(lp)	SMC_REG(lp, 0x000C, 3)  argument
711 #define EXT_REG(lp)		SMC_REG(lp, 0x0000, 7)  argument
835 #define SMC_REG(lp, reg, bank)					\  argument
837 		int __b = SMC_CURRENT_BANK(lp);			\
846 #define SMC_REG(lp, reg, bank)	(reg<<SMC_IO_SHIFT)  argument
858 #define SMC_MUST_ALIGN_WRITE(lp)	SMC_32BIT(lp)  argument
860 #define SMC_GET_PN(lp)						\  argument
861 	(SMC_8BIT(lp)	? (SMC_inb(ioaddr, PN_REG(lp)))	\
862 				: (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
864 #define SMC_SET_PN(lp, x)						\  argument
866 		if (SMC_MUST_ALIGN_WRITE(lp))				\
867 			SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2));	\
868 		else if (SMC_8BIT(lp))				\
869 			SMC_outb(x, ioaddr, PN_REG(lp));		\
871 			SMC_outw(lp, x, ioaddr, PN_REG(lp));		\
874 #define SMC_GET_AR(lp)						\  argument
875 	(SMC_8BIT(lp)	? (SMC_inb(ioaddr, AR_REG(lp)))	\
876 				: (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
878 #define SMC_GET_TXFIFO(lp)						\  argument
879 	(SMC_8BIT(lp)	? (SMC_inb(ioaddr, TXFIFO_REG(lp)))	\
880 				: (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
882 #define SMC_GET_RXFIFO(lp)						\  argument
883 	(SMC_8BIT(lp)	? (SMC_inb(ioaddr, RXFIFO_REG(lp)))	\
884 				: (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
886 #define SMC_GET_INT(lp)						\  argument
887 	(SMC_8BIT(lp)	? (SMC_inb(ioaddr, INT_REG(lp)))	\
888 				: (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
890 #define SMC_ACK_INT(lp, x)						\  argument
892 		if (SMC_8BIT(lp))					\
893 			SMC_outb(x, ioaddr, INT_REG(lp));		\
898 			__mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
899 			SMC_outw(lp, __mask | (x), ioaddr, INT_REG(lp)); \
904 #define SMC_GET_INT_MASK(lp)						\  argument
905 	(SMC_8BIT(lp)	? (SMC_inb(ioaddr, IM_REG(lp)))	\
906 				: (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
908 #define SMC_SET_INT_MASK(lp, x)					\  argument
910 		if (SMC_8BIT(lp))					\
911 			SMC_outb(x, ioaddr, IM_REG(lp));		\
913 			SMC_outw(lp, (x) << 8, ioaddr, INT_REG(lp));	\
916 #define SMC_CURRENT_BANK(lp)	SMC_inw(ioaddr, BANK_SELECT)  argument
918 #define SMC_SELECT_BANK(lp, x)					\  argument
920 		if (SMC_MUST_ALIGN_WRITE(lp))				\
923 			SMC_outw(lp, x, ioaddr, BANK_SELECT);		\
926 #define SMC_GET_BASE(lp)		SMC_inw(ioaddr, BASE_REG(lp))  argument
928 #define SMC_SET_BASE(lp, x)	SMC_outw(lp, x, ioaddr, BASE_REG(lp))  argument
930 #define SMC_GET_CONFIG(lp)	SMC_inw(ioaddr, CONFIG_REG(lp))  argument
932 #define SMC_SET_CONFIG(lp, x)	SMC_outw(lp, x, ioaddr, CONFIG_REG(lp))  argument
934 #define SMC_GET_COUNTER(lp)	SMC_inw(ioaddr, COUNTER_REG(lp))  argument
936 #define SMC_GET_CTL(lp)		SMC_inw(ioaddr, CTL_REG(lp))  argument
938 #define SMC_SET_CTL(lp, x)	SMC_outw(lp, x, ioaddr, CTL_REG(lp))  argument
940 #define SMC_GET_MII(lp)		SMC_inw(ioaddr, MII_REG(lp))  argument
942 #define SMC_GET_GP(lp)		SMC_inw(ioaddr, GP_REG(lp))  argument
944 #define SMC_SET_GP(lp, x)						\  argument
946 		if (SMC_MUST_ALIGN_WRITE(lp))				\
947 			SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1));	\
949 			SMC_outw(lp, x, ioaddr, GP_REG(lp));		\
952 #define SMC_SET_MII(lp, x)	SMC_outw(lp, x, ioaddr, MII_REG(lp))  argument
954 #define SMC_GET_MIR(lp)		SMC_inw(ioaddr, MIR_REG(lp))  argument
956 #define SMC_SET_MIR(lp, x)	SMC_outw(lp, x, ioaddr, MIR_REG(lp))  argument
958 #define SMC_GET_MMU_CMD(lp)	SMC_inw(ioaddr, MMU_CMD_REG(lp))  argument
960 #define SMC_SET_MMU_CMD(lp, x)	SMC_outw(lp, x, ioaddr, MMU_CMD_REG(lp))  argument
962 #define SMC_GET_FIFO(lp)	SMC_inw(ioaddr, FIFO_REG(lp))  argument
964 #define SMC_GET_PTR(lp)		SMC_inw(ioaddr, PTR_REG(lp))  argument
966 #define SMC_SET_PTR(lp, x)						\  argument
968 		if (SMC_MUST_ALIGN_WRITE(lp))				\
969 			SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2));	\
971 			SMC_outw(lp, x, ioaddr, PTR_REG(lp));		\
974 #define SMC_GET_EPH_STATUS(lp)	SMC_inw(ioaddr, EPH_STATUS_REG(lp))  argument
976 #define SMC_GET_RCR(lp)		SMC_inw(ioaddr, RCR_REG(lp))  argument
978 #define SMC_SET_RCR(lp, x)		SMC_outw(lp, x, ioaddr, RCR_REG(lp))  argument
980 #define SMC_GET_REV(lp)		SMC_inw(ioaddr, REV_REG(lp))  argument
982 #define SMC_GET_RPC(lp)		SMC_inw(ioaddr, RPC_REG(lp))  argument
984 #define SMC_SET_RPC(lp, x)						\  argument
986 		if (SMC_MUST_ALIGN_WRITE(lp))				\
987 			SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0));	\
989 			SMC_outw(lp, x, ioaddr, RPC_REG(lp));		\
992 #define SMC_GET_TCR(lp)		SMC_inw(ioaddr, TCR_REG(lp))  argument
994 #define SMC_SET_TCR(lp, x)	SMC_outw(lp, x, ioaddr, TCR_REG(lp))  argument
997 #define SMC_GET_MAC_ADDR(lp, addr)					\  argument
1000 		__v = SMC_inw(ioaddr, ADDR0_REG(lp));			\
1002 		__v = SMC_inw(ioaddr, ADDR1_REG(lp));			\
1004 		__v = SMC_inw(ioaddr, ADDR2_REG(lp));			\
1009 #define SMC_SET_MAC_ADDR(lp, addr)					\  argument
1011 		SMC_outw(lp, addr[0] | (addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1012 		SMC_outw(lp, addr[2] | (addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1013 		SMC_outw(lp, addr[4] | (addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1016 #define SMC_SET_MCAST(lp, x)						\  argument
1019 		SMC_outw(lp, mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1020 		SMC_outw(lp, mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1021 		SMC_outw(lp, mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1022 		SMC_outw(lp, mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1025 #define SMC_PUT_PKT_HDR(lp, status, length)				\  argument
1027 		if (SMC_32BIT(lp))					\
1029 				 DATA_REG(lp));			\
1031 			SMC_outw(lp, status, ioaddr, DATA_REG(lp));	\
1032 			SMC_outw(lp, length, ioaddr, DATA_REG(lp));	\
1036 #define SMC_GET_PKT_HDR(lp, status, length)				\  argument
1038 		if (SMC_32BIT(lp)) {				\
1039 			unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1043 			(status) = SMC_inw(ioaddr, DATA_REG(lp));	\
1044 			(length) = SMC_inw(ioaddr, DATA_REG(lp));	\
1048 #define SMC_PUSH_DATA(lp, p, l)					\  argument
1050 		if (SMC_32BIT(lp)) {				\
1056 				SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1059 			if (SMC_CAN_USE_DATACS && lp->datacs)		\
1060 				__ioaddr = lp->datacs;			\
1061 			SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1064 				SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1066 		} else if (SMC_16BIT(lp))				\
1067 			SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1);	\
1068 		else if (SMC_8BIT(lp))				\
1069 			SMC_outsb(ioaddr, DATA_REG(lp), p, l);	\
1072 #define SMC_PULL_DATA(lp, p, l)					\  argument
1074 		if (SMC_32BIT(lp)) {				\
1094 				SMC_SET_PTR(lp,			\
1097 			if (SMC_CAN_USE_DATACS && lp->datacs)		\
1098 				__ioaddr = lp->datacs;			\
1100 			SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1101 		} else if (SMC_16BIT(lp))				\
1102 			SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1);	\
1103 		else if (SMC_8BIT(lp))				\
1104 			SMC_insb(ioaddr, DATA_REG(lp), p, l);		\