Lines Matching refs:hw
9 static void i40e_resume_aq(struct i40e_hw *hw);
17 static void i40e_adminq_init_regs(struct i40e_hw *hw) in i40e_adminq_init_regs() argument
20 if (i40e_is_vf(hw)) { in i40e_adminq_init_regs()
21 hw->aq.asq.tail = I40E_VF_ATQT1; in i40e_adminq_init_regs()
22 hw->aq.asq.head = I40E_VF_ATQH1; in i40e_adminq_init_regs()
23 hw->aq.asq.len = I40E_VF_ATQLEN1; in i40e_adminq_init_regs()
24 hw->aq.asq.bal = I40E_VF_ATQBAL1; in i40e_adminq_init_regs()
25 hw->aq.asq.bah = I40E_VF_ATQBAH1; in i40e_adminq_init_regs()
26 hw->aq.arq.tail = I40E_VF_ARQT1; in i40e_adminq_init_regs()
27 hw->aq.arq.head = I40E_VF_ARQH1; in i40e_adminq_init_regs()
28 hw->aq.arq.len = I40E_VF_ARQLEN1; in i40e_adminq_init_regs()
29 hw->aq.arq.bal = I40E_VF_ARQBAL1; in i40e_adminq_init_regs()
30 hw->aq.arq.bah = I40E_VF_ARQBAH1; in i40e_adminq_init_regs()
32 hw->aq.asq.tail = I40E_PF_ATQT; in i40e_adminq_init_regs()
33 hw->aq.asq.head = I40E_PF_ATQH; in i40e_adminq_init_regs()
34 hw->aq.asq.len = I40E_PF_ATQLEN; in i40e_adminq_init_regs()
35 hw->aq.asq.bal = I40E_PF_ATQBAL; in i40e_adminq_init_regs()
36 hw->aq.asq.bah = I40E_PF_ATQBAH; in i40e_adminq_init_regs()
37 hw->aq.arq.tail = I40E_PF_ARQT; in i40e_adminq_init_regs()
38 hw->aq.arq.head = I40E_PF_ARQH; in i40e_adminq_init_regs()
39 hw->aq.arq.len = I40E_PF_ARQLEN; in i40e_adminq_init_regs()
40 hw->aq.arq.bal = I40E_PF_ARQBAL; in i40e_adminq_init_regs()
41 hw->aq.arq.bah = I40E_PF_ARQBAH; in i40e_adminq_init_regs()
49 static int i40e_alloc_adminq_asq_ring(struct i40e_hw *hw) in i40e_alloc_adminq_asq_ring() argument
53 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf, in i40e_alloc_adminq_asq_ring()
55 (hw->aq.num_asq_entries * in i40e_alloc_adminq_asq_ring()
61 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf, in i40e_alloc_adminq_asq_ring()
62 (hw->aq.num_asq_entries * in i40e_alloc_adminq_asq_ring()
65 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); in i40e_alloc_adminq_asq_ring()
76 static int i40e_alloc_adminq_arq_ring(struct i40e_hw *hw) in i40e_alloc_adminq_arq_ring() argument
80 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf, in i40e_alloc_adminq_arq_ring()
82 (hw->aq.num_arq_entries * in i40e_alloc_adminq_arq_ring()
96 static void i40e_free_adminq_asq(struct i40e_hw *hw) in i40e_free_adminq_asq() argument
98 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); in i40e_free_adminq_asq()
108 static void i40e_free_adminq_arq(struct i40e_hw *hw) in i40e_free_adminq_arq() argument
110 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); in i40e_free_adminq_arq()
117 static int i40e_alloc_arq_bufs(struct i40e_hw *hw) in i40e_alloc_arq_bufs() argument
129 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head, in i40e_alloc_arq_bufs()
130 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem))); in i40e_alloc_arq_bufs()
133 hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va; in i40e_alloc_arq_bufs()
136 for (i = 0; i < hw->aq.num_arq_entries; i++) { in i40e_alloc_arq_bufs()
137 bi = &hw->aq.arq.r.arq_bi[i]; in i40e_alloc_arq_bufs()
138 ret_code = i40e_allocate_dma_mem(hw, bi, in i40e_alloc_arq_bufs()
140 hw->aq.arq_buf_size, in i40e_alloc_arq_bufs()
146 desc = I40E_ADMINQ_DESC(hw->aq.arq, i); in i40e_alloc_arq_bufs()
149 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) in i40e_alloc_arq_bufs()
174 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); in i40e_alloc_arq_bufs()
175 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); in i40e_alloc_arq_bufs()
184 static int i40e_alloc_asq_bufs(struct i40e_hw *hw) in i40e_alloc_asq_bufs() argument
191 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head, in i40e_alloc_asq_bufs()
192 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem))); in i40e_alloc_asq_bufs()
195 hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va; in i40e_alloc_asq_bufs()
198 for (i = 0; i < hw->aq.num_asq_entries; i++) { in i40e_alloc_asq_bufs()
199 bi = &hw->aq.asq.r.asq_bi[i]; in i40e_alloc_asq_bufs()
200 ret_code = i40e_allocate_dma_mem(hw, bi, in i40e_alloc_asq_bufs()
202 hw->aq.asq_buf_size, in i40e_alloc_asq_bufs()
214 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); in i40e_alloc_asq_bufs()
215 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); in i40e_alloc_asq_bufs()
224 static void i40e_free_arq_bufs(struct i40e_hw *hw) in i40e_free_arq_bufs() argument
229 for (i = 0; i < hw->aq.num_arq_entries; i++) in i40e_free_arq_bufs()
230 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); in i40e_free_arq_bufs()
233 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); in i40e_free_arq_bufs()
236 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); in i40e_free_arq_bufs()
243 static void i40e_free_asq_bufs(struct i40e_hw *hw) in i40e_free_asq_bufs() argument
248 for (i = 0; i < hw->aq.num_asq_entries; i++) in i40e_free_asq_bufs()
249 if (hw->aq.asq.r.asq_bi[i].pa) in i40e_free_asq_bufs()
250 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); in i40e_free_asq_bufs()
253 i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf); in i40e_free_asq_bufs()
256 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); in i40e_free_asq_bufs()
259 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); in i40e_free_asq_bufs()
268 static int i40e_config_asq_regs(struct i40e_hw *hw) in i40e_config_asq_regs() argument
274 wr32(hw, hw->aq.asq.head, 0); in i40e_config_asq_regs()
275 wr32(hw, hw->aq.asq.tail, 0); in i40e_config_asq_regs()
278 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in i40e_config_asq_regs()
280 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa)); in i40e_config_asq_regs()
281 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa)); in i40e_config_asq_regs()
284 reg = rd32(hw, hw->aq.asq.bal); in i40e_config_asq_regs()
285 if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa)) in i40e_config_asq_regs()
297 static int i40e_config_arq_regs(struct i40e_hw *hw) in i40e_config_arq_regs() argument
303 wr32(hw, hw->aq.arq.head, 0); in i40e_config_arq_regs()
304 wr32(hw, hw->aq.arq.tail, 0); in i40e_config_arq_regs()
307 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in i40e_config_arq_regs()
309 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa)); in i40e_config_arq_regs()
310 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa)); in i40e_config_arq_regs()
313 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); in i40e_config_arq_regs()
316 reg = rd32(hw, hw->aq.arq.bal); in i40e_config_arq_regs()
317 if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa)) in i40e_config_arq_regs()
336 static int i40e_init_asq(struct i40e_hw *hw) in i40e_init_asq() argument
340 if (hw->aq.asq.count > 0) { in i40e_init_asq()
347 if ((hw->aq.num_asq_entries == 0) || in i40e_init_asq()
348 (hw->aq.asq_buf_size == 0)) { in i40e_init_asq()
353 hw->aq.asq.next_to_use = 0; in i40e_init_asq()
354 hw->aq.asq.next_to_clean = 0; in i40e_init_asq()
357 ret_code = i40e_alloc_adminq_asq_ring(hw); in i40e_init_asq()
362 ret_code = i40e_alloc_asq_bufs(hw); in i40e_init_asq()
367 ret_code = i40e_config_asq_regs(hw); in i40e_init_asq()
372 hw->aq.asq.count = hw->aq.num_asq_entries; in i40e_init_asq()
376 i40e_free_adminq_asq(hw); in i40e_init_asq()
395 static int i40e_init_arq(struct i40e_hw *hw) in i40e_init_arq() argument
399 if (hw->aq.arq.count > 0) { in i40e_init_arq()
406 if ((hw->aq.num_arq_entries == 0) || in i40e_init_arq()
407 (hw->aq.arq_buf_size == 0)) { in i40e_init_arq()
412 hw->aq.arq.next_to_use = 0; in i40e_init_arq()
413 hw->aq.arq.next_to_clean = 0; in i40e_init_arq()
416 ret_code = i40e_alloc_adminq_arq_ring(hw); in i40e_init_arq()
421 ret_code = i40e_alloc_arq_bufs(hw); in i40e_init_arq()
426 ret_code = i40e_config_arq_regs(hw); in i40e_init_arq()
431 hw->aq.arq.count = hw->aq.num_arq_entries; in i40e_init_arq()
435 i40e_free_adminq_arq(hw); in i40e_init_arq()
447 static int i40e_shutdown_asq(struct i40e_hw *hw) in i40e_shutdown_asq() argument
451 mutex_lock(&hw->aq.asq_mutex); in i40e_shutdown_asq()
453 if (hw->aq.asq.count == 0) { in i40e_shutdown_asq()
459 wr32(hw, hw->aq.asq.head, 0); in i40e_shutdown_asq()
460 wr32(hw, hw->aq.asq.tail, 0); in i40e_shutdown_asq()
461 wr32(hw, hw->aq.asq.len, 0); in i40e_shutdown_asq()
462 wr32(hw, hw->aq.asq.bal, 0); in i40e_shutdown_asq()
463 wr32(hw, hw->aq.asq.bah, 0); in i40e_shutdown_asq()
465 hw->aq.asq.count = 0; /* to indicate uninitialized queue */ in i40e_shutdown_asq()
468 i40e_free_asq_bufs(hw); in i40e_shutdown_asq()
471 mutex_unlock(&hw->aq.asq_mutex); in i40e_shutdown_asq()
481 static int i40e_shutdown_arq(struct i40e_hw *hw) in i40e_shutdown_arq() argument
485 mutex_lock(&hw->aq.arq_mutex); in i40e_shutdown_arq()
487 if (hw->aq.arq.count == 0) { in i40e_shutdown_arq()
493 wr32(hw, hw->aq.arq.head, 0); in i40e_shutdown_arq()
494 wr32(hw, hw->aq.arq.tail, 0); in i40e_shutdown_arq()
495 wr32(hw, hw->aq.arq.len, 0); in i40e_shutdown_arq()
496 wr32(hw, hw->aq.arq.bal, 0); in i40e_shutdown_arq()
497 wr32(hw, hw->aq.arq.bah, 0); in i40e_shutdown_arq()
499 hw->aq.arq.count = 0; /* to indicate uninitialized queue */ in i40e_shutdown_arq()
502 i40e_free_arq_bufs(hw); in i40e_shutdown_arq()
505 mutex_unlock(&hw->aq.arq_mutex); in i40e_shutdown_arq()
513 static void i40e_set_hw_flags(struct i40e_hw *hw) in i40e_set_hw_flags() argument
515 struct i40e_adminq_info *aq = &hw->aq; in i40e_set_hw_flags()
517 hw->flags = 0; in i40e_set_hw_flags()
519 switch (hw->mac.type) { in i40e_set_hw_flags()
524 hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE; in i40e_set_hw_flags()
525 hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE; in i40e_set_hw_flags()
527 hw->flags |= I40E_HW_FLAG_802_1AD_CAPABLE; in i40e_set_hw_flags()
531 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE | in i40e_set_hw_flags()
537 hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE; in i40e_set_hw_flags()
542 hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE; in i40e_set_hw_flags()
547 hw->flags |= I40E_HW_FLAG_X722_FEC_REQUEST_CAPABLE; in i40e_set_hw_flags()
558 hw->flags |= I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK; in i40e_set_hw_flags()
563 hw->flags |= I40E_HW_FLAG_FW_LLDP_PERSISTENT; in i40e_set_hw_flags()
564 hw->flags |= I40E_HW_FLAG_DROP_MODE; in i40e_set_hw_flags()
570 hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED; in i40e_set_hw_flags()
584 int i40e_init_adminq(struct i40e_hw *hw) in i40e_init_adminq() argument
592 if ((hw->aq.num_arq_entries == 0) || in i40e_init_adminq()
593 (hw->aq.num_asq_entries == 0) || in i40e_init_adminq()
594 (hw->aq.arq_buf_size == 0) || in i40e_init_adminq()
595 (hw->aq.asq_buf_size == 0)) { in i40e_init_adminq()
601 i40e_adminq_init_regs(hw); in i40e_init_adminq()
604 hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT; in i40e_init_adminq()
607 ret_code = i40e_init_asq(hw); in i40e_init_adminq()
612 ret_code = i40e_init_arq(hw); in i40e_init_adminq()
621 ret_code = i40e_aq_get_firmware_version(hw, in i40e_init_adminq()
622 &hw->aq.fw_maj_ver, in i40e_init_adminq()
623 &hw->aq.fw_min_ver, in i40e_init_adminq()
624 &hw->aq.fw_build, in i40e_init_adminq()
625 &hw->aq.api_maj_ver, in i40e_init_adminq()
626 &hw->aq.api_min_ver, in i40e_init_adminq()
632 i40e_resume_aq(hw); in i40e_init_adminq()
640 i40e_set_hw_flags(hw); in i40e_init_adminq()
643 i40e_read_nvm_word(hw, I40E_SR_NVM_DEV_STARTER_VERSION, in i40e_init_adminq()
644 &hw->nvm.version); in i40e_init_adminq()
645 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo); in i40e_init_adminq()
646 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi); in i40e_init_adminq()
647 hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo; in i40e_init_adminq()
648 i40e_read_nvm_word(hw, I40E_SR_BOOT_CONFIG_PTR, &cfg_ptr); in i40e_init_adminq()
649 i40e_read_nvm_word(hw, (cfg_ptr + I40E_NVM_OEM_VER_OFF), in i40e_init_adminq()
651 i40e_read_nvm_word(hw, (cfg_ptr + (I40E_NVM_OEM_VER_OFF + 1)), in i40e_init_adminq()
653 hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo; in i40e_init_adminq()
655 if (hw->mac.type == I40E_MAC_XL710 && in i40e_init_adminq()
656 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && in i40e_init_adminq()
657 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { in i40e_init_adminq()
658 hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE; in i40e_init_adminq()
659 hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE; in i40e_init_adminq()
661 if (hw->mac.type == I40E_MAC_X722 && in i40e_init_adminq()
662 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && in i40e_init_adminq()
663 hw->aq.api_min_ver >= I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722) { in i40e_init_adminq()
664 hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE; in i40e_init_adminq()
668 if (hw->aq.api_maj_ver > 1 || in i40e_init_adminq()
669 (hw->aq.api_maj_ver == 1 && in i40e_init_adminq()
670 hw->aq.api_min_ver >= 7)) in i40e_init_adminq()
671 hw->flags |= I40E_HW_FLAG_802_1AD_CAPABLE; in i40e_init_adminq()
673 if (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) { in i40e_init_adminq()
679 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL); in i40e_init_adminq()
680 hw->nvm_release_on_done = false; in i40e_init_adminq()
681 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; in i40e_init_adminq()
689 i40e_shutdown_arq(hw); in i40e_init_adminq()
691 i40e_shutdown_asq(hw); in i40e_init_adminq()
702 void i40e_shutdown_adminq(struct i40e_hw *hw) in i40e_shutdown_adminq() argument
704 if (i40e_check_asq_alive(hw)) in i40e_shutdown_adminq()
705 i40e_aq_queue_shutdown(hw, true); in i40e_shutdown_adminq()
707 i40e_shutdown_asq(hw); in i40e_shutdown_adminq()
708 i40e_shutdown_arq(hw); in i40e_shutdown_adminq()
710 if (hw->nvm_buff.va) in i40e_shutdown_adminq()
711 i40e_free_virt_mem(hw, &hw->nvm_buff); in i40e_shutdown_adminq()
720 static u16 i40e_clean_asq(struct i40e_hw *hw) in i40e_clean_asq() argument
722 struct i40e_adminq_ring *asq = &(hw->aq.asq); in i40e_clean_asq()
730 while (rd32(hw, hw->aq.asq.head) != ntc) { in i40e_clean_asq()
731 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, in i40e_clean_asq()
732 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); in i40e_clean_asq()
738 cb_func(hw, &desc_cb); in i40e_clean_asq()
761 static bool i40e_asq_done(struct i40e_hw *hw) in i40e_asq_done() argument
766 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; in i40e_asq_done()
783 i40e_asq_send_command_atomic_exec(struct i40e_hw *hw, in i40e_asq_send_command_atomic_exec() argument
798 if (hw->aq.asq.count == 0) { in i40e_asq_send_command_atomic_exec()
799 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, in i40e_asq_send_command_atomic_exec()
805 hw->aq.asq_last_status = I40E_AQ_RC_OK; in i40e_asq_send_command_atomic_exec()
807 val = rd32(hw, hw->aq.asq.head); in i40e_asq_send_command_atomic_exec()
808 if (val >= hw->aq.num_asq_entries) { in i40e_asq_send_command_atomic_exec()
809 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, in i40e_asq_send_command_atomic_exec()
815 details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use); in i40e_asq_send_command_atomic_exec()
837 if (buff_size > hw->aq.asq_buf_size) { in i40e_asq_send_command_atomic_exec()
838 i40e_debug(hw, in i40e_asq_send_command_atomic_exec()
847 i40e_debug(hw, in i40e_asq_send_command_atomic_exec()
861 if (i40e_clean_asq(hw) == 0) { in i40e_asq_send_command_atomic_exec()
862 i40e_debug(hw, in i40e_asq_send_command_atomic_exec()
870 desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use); in i40e_asq_send_command_atomic_exec()
877 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]); in i40e_asq_send_command_atomic_exec()
892 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, "AQTX: desc and buffer:\n"); in i40e_asq_send_command_atomic_exec()
893 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, in i40e_asq_send_command_atomic_exec()
895 (hw->aq.asq.next_to_use)++; in i40e_asq_send_command_atomic_exec()
896 if (hw->aq.asq.next_to_use == hw->aq.asq.count) in i40e_asq_send_command_atomic_exec()
897 hw->aq.asq.next_to_use = 0; in i40e_asq_send_command_atomic_exec()
899 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use); in i40e_asq_send_command_atomic_exec()
911 if (i40e_asq_done(hw)) in i40e_asq_send_command_atomic_exec()
920 } while (total_delay < hw->aq.asq_cmd_timeout); in i40e_asq_send_command_atomic_exec()
924 if (i40e_asq_done(hw)) { in i40e_asq_send_command_atomic_exec()
930 i40e_debug(hw, in i40e_asq_send_command_atomic_exec()
945 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval; in i40e_asq_send_command_atomic_exec()
948 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, in i40e_asq_send_command_atomic_exec()
950 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size); in i40e_asq_send_command_atomic_exec()
959 if (rd32(hw, hw->aq.asq.len) & I40E_GL_ATQLEN_ATQCRIT_MASK) { in i40e_asq_send_command_atomic_exec()
960 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, in i40e_asq_send_command_atomic_exec()
964 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, in i40e_asq_send_command_atomic_exec()
987 i40e_asq_send_command_atomic(struct i40e_hw *hw, in i40e_asq_send_command_atomic() argument
996 mutex_lock(&hw->aq.asq_mutex); in i40e_asq_send_command_atomic()
997 status = i40e_asq_send_command_atomic_exec(hw, desc, buff, buff_size, in i40e_asq_send_command_atomic()
1001 mutex_unlock(&hw->aq.asq_mutex); in i40e_asq_send_command_atomic()
1006 i40e_asq_send_command(struct i40e_hw *hw, struct i40e_aq_desc *desc, in i40e_asq_send_command() argument
1010 return i40e_asq_send_command_atomic(hw, desc, buff, buff_size, in i40e_asq_send_command()
1029 i40e_asq_send_command_atomic_v2(struct i40e_hw *hw, in i40e_asq_send_command_atomic_v2() argument
1039 mutex_lock(&hw->aq.asq_mutex); in i40e_asq_send_command_atomic_v2()
1040 status = i40e_asq_send_command_atomic_exec(hw, desc, buff, in i40e_asq_send_command_atomic_v2()
1045 *aq_status = hw->aq.asq_last_status; in i40e_asq_send_command_atomic_v2()
1046 mutex_unlock(&hw->aq.asq_mutex); in i40e_asq_send_command_atomic_v2()
1051 i40e_asq_send_command_v2(struct i40e_hw *hw, struct i40e_aq_desc *desc, in i40e_asq_send_command_v2() argument
1056 return i40e_asq_send_command_atomic_v2(hw, desc, buff, buff_size, in i40e_asq_send_command_v2()
1086 int i40e_clean_arq_element(struct i40e_hw *hw, in i40e_clean_arq_element() argument
1090 u16 ntc = hw->aq.arq.next_to_clean; in i40e_clean_arq_element()
1103 mutex_lock(&hw->aq.arq_mutex); in i40e_clean_arq_element()
1105 if (hw->aq.arq.count == 0) { in i40e_clean_arq_element()
1106 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, in i40e_clean_arq_element()
1113 ntu = rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK; in i40e_clean_arq_element()
1121 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc); in i40e_clean_arq_element()
1124 hw->aq.arq_last_status = in i40e_clean_arq_element()
1129 i40e_debug(hw, in i40e_clean_arq_element()
1132 hw->aq.arq_last_status); in i40e_clean_arq_element()
1139 memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va, in i40e_clean_arq_element()
1142 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, "AQRX: desc and buffer:\n"); in i40e_clean_arq_element()
1143 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf, in i40e_clean_arq_element()
1144 hw->aq.arq_buf_size); in i40e_clean_arq_element()
1150 bi = &hw->aq.arq.r.arq_bi[ntc]; in i40e_clean_arq_element()
1154 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) in i40e_clean_arq_element()
1161 wr32(hw, hw->aq.arq.tail, ntc); in i40e_clean_arq_element()
1164 if (ntc == hw->aq.num_arq_entries) in i40e_clean_arq_element()
1166 hw->aq.arq.next_to_clean = ntc; in i40e_clean_arq_element()
1167 hw->aq.arq.next_to_use = ntu; in i40e_clean_arq_element()
1169 i40e_nvmupd_check_wait_event(hw, le16_to_cpu(e->desc.opcode), &e->desc); in i40e_clean_arq_element()
1173 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc); in i40e_clean_arq_element()
1175 mutex_unlock(&hw->aq.arq_mutex); in i40e_clean_arq_element()
1180 static void i40e_resume_aq(struct i40e_hw *hw) in i40e_resume_aq() argument
1183 hw->aq.asq.next_to_use = 0; in i40e_resume_aq()
1184 hw->aq.asq.next_to_clean = 0; in i40e_resume_aq()
1186 i40e_config_asq_regs(hw); in i40e_resume_aq()
1188 hw->aq.arq.next_to_use = 0; in i40e_resume_aq()
1189 hw->aq.arq.next_to_clean = 0; in i40e_resume_aq()
1191 i40e_config_arq_regs(hw); in i40e_resume_aq()