85 static int pmread(struct cmac *cmac, u32 reg, u32 * data32)  in pmread()  argument
87 	t1_tpi_read(cmac->adapter, OFFSET(reg), data32);  in pmread()
91 static int pmwrite(struct cmac *cmac, u32 reg, u32 data32)  in pmwrite()  argument
93 	t1_tpi_write(cmac->adapter, OFFSET(reg), data32);  in pmwrite()
98 static int pm3393_reset(struct cmac *cmac)  in pm3393_reset()  argument
111 static int pm3393_interrupt_enable(struct cmac *cmac)  in pm3393_interrupt_enable()  argument
117 	pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0xffff);  in pm3393_interrupt_enable()
118 	pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0xffff);  in pm3393_interrupt_enable()
119 	pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0xffff);  in pm3393_interrupt_enable()
120 	pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0xffff);  in pm3393_interrupt_enable()
123 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);  in pm3393_interrupt_enable()
124 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);  in pm3393_interrupt_enable()
125 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);  in pm3393_interrupt_enable()
126 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);  in pm3393_interrupt_enable()
128 	pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0xffff);  in pm3393_interrupt_enable()
129 	pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0xffff);  in pm3393_interrupt_enable()
130 	pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0xffff);  in pm3393_interrupt_enable()
131 	pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0xffff);  in pm3393_interrupt_enable()
132 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0xffff);  in pm3393_interrupt_enable()
133 	pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0xffff);  in pm3393_interrupt_enable()
134 	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0xffff);  in pm3393_interrupt_enable()
135 	pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0xffff);  in pm3393_interrupt_enable()
136 	pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0xffff);  in pm3393_interrupt_enable()
141 	pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE,  in pm3393_interrupt_enable()
145 	pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE);  in pm3393_interrupt_enable()
147 	writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE);  in pm3393_interrupt_enable()
151 static int pm3393_interrupt_disable(struct cmac *cmac)  in pm3393_interrupt_disable()  argument
156 	pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0);  in pm3393_interrupt_disable()
157 	pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0);  in pm3393_interrupt_disable()
158 	pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0);  in pm3393_interrupt_disable()
159 	pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0);  in pm3393_interrupt_disable()
160 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);  in pm3393_interrupt_disable()
161 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);  in pm3393_interrupt_disable()
162 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);  in pm3393_interrupt_disable()
163 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);  in pm3393_interrupt_disable()
164 	pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0);  in pm3393_interrupt_disable()
165 	pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0);  in pm3393_interrupt_disable()
166 	pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0);  in pm3393_interrupt_disable()
167 	pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0);  in pm3393_interrupt_disable()
168 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0);  in pm3393_interrupt_disable()
169 	pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0);  in pm3393_interrupt_disable()
170 	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0);  in pm3393_interrupt_disable()
171 	pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0);  in pm3393_interrupt_disable()
172 	pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0);  in pm3393_interrupt_disable()
175 	pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, 0);  in pm3393_interrupt_disable()
178 	t1_tpi_read(cmac->adapter, A_ELMER0_INT_ENABLE, &elmer);  in pm3393_interrupt_disable()
180 	t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer);  in pm3393_interrupt_disable()
190 static int pm3393_interrupt_clear(struct cmac *cmac)  in pm3393_interrupt_clear()  argument
199 	pmread(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS, &val32);  in pm3393_interrupt_clear()
200 	pmread(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS, &val32);  in pm3393_interrupt_clear()
201 	pmread(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS, &val32);  in pm3393_interrupt_clear()
202 	pmread(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS, &val32);  in pm3393_interrupt_clear()
203 	pmread(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT, &val32);  in pm3393_interrupt_clear()
204 	pmread(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS, &val32);  in pm3393_interrupt_clear()
205 	pmread(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT, &val32);  in pm3393_interrupt_clear()
206 	pmread(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS, &val32);  in pm3393_interrupt_clear()
207 	pmread(cmac, SUNI1x10GEXP_REG_RXXG_INTERRUPT, &val32);  in pm3393_interrupt_clear()
208 	pmread(cmac, SUNI1x10GEXP_REG_TXXG_INTERRUPT, &val32);  in pm3393_interrupt_clear()
209 	pmread(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT, &val32);  in pm3393_interrupt_clear()
210 	pmread(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION,  in pm3393_interrupt_clear()
212 	pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS, &val32);  in pm3393_interrupt_clear()
213 	pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE, &val32);  in pm3393_interrupt_clear()
217 	pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS, &val32);  in pm3393_interrupt_clear()
221 	t1_tpi_read(cmac->adapter, A_ELMER0_INT_CAUSE, &elmer);  in pm3393_interrupt_clear()
223 	t1_tpi_write(cmac->adapter, A_ELMER0_INT_CAUSE, elmer);  in pm3393_interrupt_clear()
227 	pl_intr = readl(cmac->adapter->regs + A_PL_CAUSE);  in pm3393_interrupt_clear()
229 	writel(pl_intr, cmac->adapter->regs + A_PL_CAUSE);  in pm3393_interrupt_clear()
235 static int pm3393_interrupt_handler(struct cmac *cmac)  in pm3393_interrupt_handler()  argument
240 	pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS,  in pm3393_interrupt_handler()
242 	if (netif_msg_intr(cmac->adapter))  in pm3393_interrupt_handler()
243 		dev_dbg(&cmac->adapter->pdev->dev, "PM3393 intr cause 0x%x\n",  in pm3393_interrupt_handler()
247 	pm3393_interrupt_clear(cmac);  in pm3393_interrupt_handler()
252 static int pm3393_enable(struct cmac *cmac, int which)  in pm3393_enable()  argument
255 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1,  in pm3393_enable()
261 		if (cmac->instance->fc & PAUSE_RX)  in pm3393_enable()
263 		if (cmac->instance->fc & PAUSE_TX)  in pm3393_enable()
265 		pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, val);  in pm3393_enable()
268 	cmac->instance->enabled |= which;  in pm3393_enable()
272 static int pm3393_enable_port(struct cmac *cmac, int which)  in pm3393_enable_port()  argument
275 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_CONTROL,  in pm3393_enable_port()
278 	memset(&cmac->stats, 0, sizeof(struct cmac_statistics));  in pm3393_enable_port()
280 	pm3393_enable(cmac, which);  in pm3393_enable_port()
287 	t1_link_changed(cmac->adapter, 0);  in pm3393_enable_port()
291 static int pm3393_disable(struct cmac *cmac, int which)  in pm3393_disable()  argument
294 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1, RXXG_CONF1_VAL);  in pm3393_disable()
296 		pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, TXXG_CONF1_VAL);  in pm3393_disable()
304 	cmac->instance->enabled &= ~which;  in pm3393_disable()
308 static int pm3393_loopback_enable(struct cmac *cmac)  in pm3393_loopback_enable()  argument
313 static int pm3393_loopback_disable(struct cmac *cmac)  in pm3393_loopback_disable()  argument
318 static int pm3393_set_mtu(struct cmac *cmac, int mtu)  in pm3393_set_mtu()  argument
320 	int enabled = cmac->instance->enabled;  in pm3393_set_mtu()
326 		pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);  in pm3393_set_mtu()
328 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH, mtu);  in pm3393_set_mtu()
329 	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE, mtu);  in pm3393_set_mtu()
332 		pm3393_enable(cmac, enabled);  in pm3393_set_mtu()
336 static int pm3393_set_rx_mode(struct cmac *cmac, struct t1_rx_mode *rm)  in pm3393_set_rx_mode()  argument
338 	int enabled = cmac->instance->enabled & MAC_DIRECTION_RX;  in pm3393_set_rx_mode()
343 		pm3393_disable(cmac, MAC_DIRECTION_RX);  in pm3393_set_rx_mode()
345 	pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, &rx_mode);  in pm3393_set_rx_mode()
348 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2,  in pm3393_set_rx_mode()
357 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, 0xffff);  in pm3393_set_rx_mode()
358 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, 0xffff);  in pm3393_set_rx_mode()
359 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, 0xffff);  in pm3393_set_rx_mode()
360 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, 0xffff);  in pm3393_set_rx_mode()
373 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, mc_filter[0]);  in pm3393_set_rx_mode()
374 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, mc_filter[1]);  in pm3393_set_rx_mode()
375 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, mc_filter[2]);  in pm3393_set_rx_mode()
376 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, mc_filter[3]);  in pm3393_set_rx_mode()
380 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, (u16)rx_mode);  in pm3393_set_rx_mode()
383 		pm3393_enable(cmac, MAC_DIRECTION_RX);  in pm3393_set_rx_mode()
388 static int pm3393_get_speed_duplex_fc(struct cmac *cmac, int *speed,  in pm3393_get_speed_duplex_fc()  argument
396 		*fc = cmac->instance->fc;  in pm3393_get_speed_duplex_fc()
400 static int pm3393_set_speed_duplex_fc(struct cmac *cmac, int speed, int duplex,  in pm3393_set_speed_duplex_fc()  argument
410 	if (fc != cmac->instance->fc) {  in pm3393_set_speed_duplex_fc()
411 		cmac->instance->fc = (u8) fc;  in pm3393_set_speed_duplex_fc()
412 		if (cmac->instance->enabled & MAC_DIRECTION_TX)  in pm3393_set_speed_duplex_fc()
413 			pm3393_enable(cmac, MAC_DIRECTION_TX);  in pm3393_set_speed_duplex_fc()
433 static const struct cmac_statistics *pm3393_update_statistics(struct cmac *mac,  in pm3393_update_statistics()
484 static int pm3393_macaddress_get(struct cmac *cmac, u8 mac_addr[6])  in pm3393_macaddress_get()  argument
486 	memcpy(mac_addr, cmac->instance->mac_addr, ETH_ALEN);  in pm3393_macaddress_get()
490 static int pm3393_macaddress_set(struct cmac *cmac, const u8 ma[6])  in pm3393_macaddress_set()  argument
492 	u32 val, lo, mid, hi, enabled = cmac->instance->enabled;  in pm3393_macaddress_set()
513 	memcpy(cmac->instance->mac_addr, ma, ETH_ALEN);  in pm3393_macaddress_set()
521 		pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);  in pm3393_macaddress_set()
524 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_15_0, lo);  in pm3393_macaddress_set()
525 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_31_16, mid);  in pm3393_macaddress_set()
526 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_47_32, hi);  in pm3393_macaddress_set()
529 	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_15_0, lo);  in pm3393_macaddress_set()
530 	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_31_16, mid);  in pm3393_macaddress_set()
531 	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_47_32, hi);  in pm3393_macaddress_set()
537 	pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, &val);  in pm3393_macaddress_set()
539 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);  in pm3393_macaddress_set()
541 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW, lo);  in pm3393_macaddress_set()
542 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID, mid);  in pm3393_macaddress_set()
543 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH, hi);  in pm3393_macaddress_set()
546 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);  in pm3393_macaddress_set()
549 		pm3393_enable(cmac, enabled);  in pm3393_macaddress_set()
553 static void pm3393_destroy(struct cmac *cmac)  in pm3393_destroy()  argument
555 	kfree(cmac);  in pm3393_destroy()
578 static struct cmac *pm3393_mac_create(adapter_t *adapter, int index)  in pm3393_mac_create()
580 	struct cmac *cmac;  in pm3393_mac_create()  local
582 	cmac = kzalloc(sizeof(*cmac) + sizeof(cmac_instance), GFP_KERNEL);  in pm3393_mac_create()
583 	if (!cmac)  in pm3393_mac_create()
586 	cmac->ops = &pm3393_ops;  in pm3393_mac_create()
587 	cmac->instance = (cmac_instance *) (cmac + 1);  in pm3393_mac_create()
588 	cmac->adapter = adapter;  in pm3393_mac_create()
589 	cmac->instance->fc = PAUSE_TX | PAUSE_RX;  in pm3393_mac_create()
672 	return cmac;  in pm3393_mac_create()