1414 			       u32 emac_base)  in bnx2x_set_mdio_clk()  argument
1421 	cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);  in bnx2x_set_mdio_clk()
1439 	REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);  in bnx2x_set_mdio_clk()
1473 	u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;  in bnx2x_emac_init()  local
1485 	val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);  in bnx2x_emac_init()
1490 		val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);  in bnx2x_emac_init()
1809 	u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;  in bnx2x_emac_enable()  local
1839 	bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,  in bnx2x_emac_enable()
1841 	bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,  in bnx2x_emac_enable()
1845 	bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,  in bnx2x_emac_enable()
1848 	bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,  in bnx2x_emac_enable()
1854 			bnx2x_bits_en(bp, emac_base +  in bnx2x_emac_enable()
1859 			bnx2x_bits_en(bp, emac_base +  in bnx2x_emac_enable()
1864 		bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,  in bnx2x_emac_enable()
1868 	val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);  in bnx2x_emac_enable()
1897 	val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);  in bnx2x_emac_enable()
2556 	u32 emac_base = 0;  in bnx2x_get_emac_base()  local
2562 			emac_base = GRCBASE_EMAC1;  in bnx2x_get_emac_base()
2564 			emac_base = GRCBASE_EMAC0;  in bnx2x_get_emac_base()
2568 			emac_base = GRCBASE_EMAC0;  in bnx2x_get_emac_base()
2570 			emac_base = GRCBASE_EMAC1;  in bnx2x_get_emac_base()
2573 		emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;  in bnx2x_get_emac_base()
2576 		emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;  in bnx2x_get_emac_base()
2581 	return emac_base;  in bnx2x_get_emac_base()
3314 	u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;  in bnx2x_set_serdes_access()  local
3318 	REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);  in bnx2x_set_serdes_access()
3320 	REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);  in bnx2x_set_serdes_access()
6306 	u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;  in bnx2x_set_led()  local