269 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);  in bnx2_reg_rd_ind()
281 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);  in bnx2_reg_wr_ind()
282 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val);  in bnx2_reg_wr_ind()
308 		BNX2_WR(bp, BNX2_CTX_CTX_DATA, val);  in bnx2_ctx_wr()
309 		BNX2_WR(bp, BNX2_CTX_CTX_CTRL,  in bnx2_ctx_wr()
318 		BNX2_WR(bp, BNX2_CTX_DATA_ADR, offset);  in bnx2_ctx_wr()
319 		BNX2_WR(bp, BNX2_CTX_DATA, val);  in bnx2_ctx_wr()
495 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_read_phy()
504 	BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);  in bnx2_read_phy()
533 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_read_phy()
552 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_write_phy()
561 	BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);  in bnx2_write_phy()
582 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_write_phy()
599 		BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_disable_int()
614 		BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_enable_int()
619 		BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_enable_int()
623 	BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);  in bnx2_enable_int()
1319 	BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);  in bnx2_set_mac_link()
1322 		BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);  in bnx2_set_mac_link()
1358 	BNX2_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_set_mac_link()
1365 	BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);  in bnx2_set_mac_link()
1373 	BNX2_WR(bp, BNX2_EMAC_TX_MODE, val);  in bnx2_set_mac_link()
1376 	BNX2_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);  in bnx2_set_mac_link()
1967 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);  in bnx2_send_heart_beat()
1968 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);  in bnx2_send_heart_beat()
2296 		BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);  in bnx2_init_5706s_phy()
2401 	BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);  in bnx2_init_phy()
2438 	BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);  in bnx2_set_mac_loopback()
2470 	BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);  in bnx2_set_phy_loopback()
2573 	BNX2_WR(bp, BNX2_CTX_COMMAND, val);  in bnx2_init_5709_context()
2591 		BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,  in bnx2_init_5709_context()
2594 		BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,  in bnx2_init_5709_context()
2596 		BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |  in bnx2_init_5709_context()
2646 			BNX2_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);  in bnx2_init_context()
2647 			BNX2_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);  in bnx2_init_context()
2667 	BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_alloc_bad_rbuf()
2712 	BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);  in bnx2_set_mac_addr()
2717 	BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);  in bnx2_set_mac_addr()
2805 			BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);  in bnx2_phy_event_is_set()
2807 			BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);  in bnx2_phy_event_is_set()
3298 	BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);  in bnx2_rx_int()
3314 	BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_msi()
3362 	BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_interrupt()
3430 			BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &  in bnx2_chk_missed_msi()
3432 			BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);  in bnx2_chk_missed_msi()
3471 		BNX2_WR(bp, BNX2_HC_COMMAND,  in bnx2_poll_link()
3510 			BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_poll_msix()
3548 				BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3553 			BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3558 			BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3598 			BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_set_rx_mode()
3621 			BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_set_rx_mode()
3647 		BNX2_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);  in bnx2_set_rx_mode()
3650 	BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);  in bnx2_set_rx_mode()
3651 	BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);  in bnx2_set_rx_mode()
3652 	BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);  in bnx2_set_rx_mode()
3793 		BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));  in load_rv2p_fw()
3795 		BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));  in load_rv2p_fw()
3799 		BNX2_WR(bp, addr, val);  in load_rv2p_fw()
3809 			BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, code);  in load_rv2p_fw()
3812 			BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, code);  in load_rv2p_fw()
3815 			BNX2_WR(bp, addr, val);  in load_rv2p_fw()
3821 		BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);  in load_rv2p_fw()
3824 		BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);  in load_rv2p_fw()
3974 		BNX2_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_setup_wol()
3978 			BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_setup_wol()
3981 		BNX2_WR(bp, BNX2_EMAC_RX_MODE, BNX2_EMAC_RX_MODE_SORT_MODE);  in bnx2_setup_wol()
3984 		BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);  in bnx2_setup_wol()
3985 		BNX2_WR(bp, BNX2_RPM_SORT_USER0, val);  in bnx2_setup_wol()
3986 		BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | BNX2_RPM_SORT_USER0_ENA);  in bnx2_setup_wol()
3989 		BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_setup_wol()
3996 		BNX2_WR(bp, BNX2_RPM_CONFIG, val);  in bnx2_setup_wol()
4036 		BNX2_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_set_power_state()
4040 		BNX2_WR(bp, BNX2_RPM_CONFIG, val);  in bnx2_set_power_state()
4086 	BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);  in bnx2_acquire_nvram_lock()
4108 	BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);  in bnx2_release_nvram_lock()
4131 	BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);  in bnx2_enable_nvram_write()
4136 		BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_enable_nvram_write()
4137 		BNX2_WR(bp, BNX2_NVM_COMMAND,  in bnx2_enable_nvram_write()
4160 	BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);  in bnx2_disable_nvram_write()
4171 	BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,  in bnx2_enable_nvram_access()
4182 	BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,  in bnx2_disable_nvram_access()
4202 	BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_erase_page()
4205 	BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_erase_page()
4208 	BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_erase_page()
4244 	BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_read_dword()
4247 	BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_read_dword()
4250 	BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_read_dword()
4290 	BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_write_dword()
4295 	BNX2_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));  in bnx2_nvram_write_dword()
4298 	BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_write_dword()
4301 	BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_write_dword()
4368 				BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1);  in bnx2_init_nvram()
4369 				BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2);  in bnx2_init_nvram()
4370 				BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3);  in bnx2_init_nvram()
4371 				BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1);  in bnx2_init_nvram()
4732 	BNX2_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);  in bnx2_setup_msix_tbl()
4734 	BNX2_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);  in bnx2_setup_msix_tbl()
4735 	BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);  in bnx2_setup_msix_tbl()
4750 		BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,  in bnx2_wait_dma_complete()
4760 		BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);  in bnx2_wait_dma_complete()
4799 		BNX2_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);  in bnx2_reset_chip()
4806 		BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);  in bnx2_reset_chip()
4814 		BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);  in bnx2_reset_chip()
4863 		BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);  in bnx2_reset_chip()
4872 		BNX2_WR(bp, BNX2_MISC_ECO_HW_CTL,  in bnx2_reset_chip()
4886 	BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);  in bnx2_init_chip()
4907 	BNX2_WR(bp, BNX2_DMA_CONFIG, val);  in bnx2_init_chip()
4912 		BNX2_WR(bp, BNX2_TDMA_CONFIG, val);  in bnx2_init_chip()
4924 	BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_init_chip()
4953 	BNX2_WR(bp, BNX2_MQ_CONFIG, val);  in bnx2_init_chip()
4956 	BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);  in bnx2_init_chip()
4957 	BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val);  in bnx2_init_chip()
4960 	BNX2_WR(bp, BNX2_RV2P_CONFIG, val);  in bnx2_init_chip()
4966 	BNX2_WR(bp, BNX2_TBDR_CONFIG, val);  in bnx2_init_chip()
4974 	BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);  in bnx2_init_chip()
4981 	BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);  in bnx2_init_chip()
4997 	BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);  in bnx2_init_chip()
4999 	BNX2_WR(bp, BNX2_HC_STATUS_ADDR_L,  in bnx2_init_chip()
5001 	BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);  in bnx2_init_chip()
5003 	BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_L,  in bnx2_init_chip()
5005 	BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_H,  in bnx2_init_chip()
5008 	BNX2_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,  in bnx2_init_chip()
5011 	BNX2_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,  in bnx2_init_chip()
5014 	BNX2_WR(bp, BNX2_HC_COMP_PROD_TRIP,  in bnx2_init_chip()
5017 	BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);  in bnx2_init_chip()
5019 	BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);  in bnx2_init_chip()
5021 	BNX2_WR(bp, BNX2_HC_COM_TICKS,  in bnx2_init_chip()
5024 	BNX2_WR(bp, BNX2_HC_CMD_TICKS,  in bnx2_init_chip()
5028 		BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0);  in bnx2_init_chip()
5030 		BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);  in bnx2_init_chip()
5031 	BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */  in bnx2_init_chip()
5041 		BNX2_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,  in bnx2_init_chip()
5050 	BNX2_WR(bp, BNX2_HC_CONFIG, val);  in bnx2_init_chip()
5061 		BNX2_WR(bp, base,  in bnx2_init_chip()
5066 		BNX2_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,  in bnx2_init_chip()
5070 		BNX2_WR(bp, base + BNX2_HC_TX_TICKS_OFF,  in bnx2_init_chip()
5073 		BNX2_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,  in bnx2_init_chip()
5077 		BNX2_WR(bp, base + BNX2_HC_RX_TICKS_OFF,  in bnx2_init_chip()
5082 	BNX2_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);  in bnx2_init_chip()
5084 	BNX2_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);  in bnx2_init_chip()
5092 		BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);  in bnx2_init_chip()
5097 	BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);  in bnx2_init_chip()
5239 		BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);  in bnx2_init_rx_ring()
5259 			BNX2_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);  in bnx2_init_rx_ring()
5299 	BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);  in bnx2_init_rx_ring()
5310 	BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0);  in bnx2_init_all_rings()
5315 		BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |  in bnx2_init_all_rings()
5318 	BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);  in bnx2_init_all_rings()
5332 				BNX2_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);  in bnx2_init_all_rings()
5333 				BNX2_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |  in bnx2_init_all_rings()
5344 		BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val);  in bnx2_init_all_rings()
5836 	BNX2_WR(bp, BNX2_HC_COMMAND,  in bnx2_run_loopback()
5858 	BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);  in bnx2_run_loopback()
5862 	BNX2_WR(bp, BNX2_HC_COMMAND,  in bnx2_run_loopback()
6017 	BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);  in bnx2_test_intr()
6184 		BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |  in bnx2_timer()
6257 	BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);  in bnx2_enable_msix()
6258 	BNX2_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);  in bnx2_enable_msix()
6259 	BNX2_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);  in bnx2_enable_msix()
6513 		BNX2_WR(bp, BNX2_TBDC_BD_ADDR, i);  in bnx2_dump_ftq()
6514 		BNX2_WR(bp, BNX2_TBDC_CAM_OPCODE,  in bnx2_dump_ftq()
6516 		BNX2_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB);  in bnx2_dump_ftq()
6701 	BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);  in bnx2_start_xmit()
7709 		BNX2_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);  in bnx2_set_phys_id()
7713 		BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |  in bnx2_set_phys_id()
7722 		BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);  in bnx2_set_phys_id()
7726 		BNX2_WR(bp, BNX2_EMAC_LED, 0);  in bnx2_set_phys_id()
7727 		BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save);  in bnx2_set_phys_id()
8146 	BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG,  in bnx2_init_board()
8211 		BNX2_WR(bp, PCI_COMMAND, reg);  in bnx2_init_board()