Lines Matching refs:ctrl
317 struct brcmnand_controller *ctrl; member
628 static inline bool brcmnand_non_mmio_ops(struct brcmnand_controller *ctrl) in brcmnand_non_mmio_ops() argument
637 static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs) in nand_readreg() argument
639 if (brcmnand_non_mmio_ops(ctrl)) in nand_readreg()
640 return brcmnand_soc_read(ctrl->soc, offs); in nand_readreg()
641 return brcmnand_readl(ctrl->nand_base + offs); in nand_readreg()
644 static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs, in nand_writereg() argument
647 if (brcmnand_non_mmio_ops(ctrl)) in nand_writereg()
648 brcmnand_soc_write(ctrl->soc, val, offs); in nand_writereg()
650 brcmnand_writel(val, ctrl->nand_base + offs); in nand_writereg()
653 static int brcmnand_revision_init(struct brcmnand_controller *ctrl) in brcmnand_revision_init() argument
663 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff; in brcmnand_revision_init()
666 if (ctrl->nand_version < 0x0201) { in brcmnand_revision_init()
667 dev_err(ctrl->dev, "version %#x not supported\n", in brcmnand_revision_init()
668 ctrl->nand_version); in brcmnand_revision_init()
673 if (ctrl->nand_version >= 0x0702) in brcmnand_revision_init()
674 ctrl->reg_offsets = brcmnand_regs_v72; in brcmnand_revision_init()
675 else if (ctrl->nand_version == 0x0701) in brcmnand_revision_init()
676 ctrl->reg_offsets = brcmnand_regs_v71; in brcmnand_revision_init()
677 else if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
678 ctrl->reg_offsets = brcmnand_regs_v60; in brcmnand_revision_init()
679 else if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
680 ctrl->reg_offsets = brcmnand_regs_v50; in brcmnand_revision_init()
681 else if (ctrl->nand_version >= 0x0303) in brcmnand_revision_init()
682 ctrl->reg_offsets = brcmnand_regs_v33; in brcmnand_revision_init()
683 else if (ctrl->nand_version >= 0x0201) in brcmnand_revision_init()
684 ctrl->reg_offsets = brcmnand_regs_v21; in brcmnand_revision_init()
687 if (ctrl->nand_version >= 0x0701) in brcmnand_revision_init()
688 ctrl->reg_spacing = 0x14; in brcmnand_revision_init()
690 ctrl->reg_spacing = 0x10; in brcmnand_revision_init()
693 if (ctrl->nand_version >= 0x0701) { in brcmnand_revision_init()
694 ctrl->cs_offsets = brcmnand_cs_offsets_v71; in brcmnand_revision_init()
696 ctrl->cs_offsets = brcmnand_cs_offsets; in brcmnand_revision_init()
699 if (ctrl->nand_version >= 0x0303 && in brcmnand_revision_init()
700 ctrl->nand_version <= 0x0500) in brcmnand_revision_init()
701 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0; in brcmnand_revision_init()
705 if (ctrl->nand_version >= 0x0701) { in brcmnand_revision_init()
707 ctrl->max_page_size = 16 * 1024; in brcmnand_revision_init()
708 ctrl->max_block_size = 2 * 1024 * 1024; in brcmnand_revision_init()
710 if (ctrl->nand_version >= 0x0304) in brcmnand_revision_init()
711 ctrl->page_sizes = page_sizes_v3_4; in brcmnand_revision_init()
712 else if (ctrl->nand_version >= 0x0202) in brcmnand_revision_init()
713 ctrl->page_sizes = page_sizes_v2_2; in brcmnand_revision_init()
715 ctrl->page_sizes = page_sizes_v2_1; in brcmnand_revision_init()
717 if (ctrl->nand_version >= 0x0202) in brcmnand_revision_init()
718 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT; in brcmnand_revision_init()
720 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT_v2_1; in brcmnand_revision_init()
722 if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
723 ctrl->block_sizes = block_sizes_v6; in brcmnand_revision_init()
724 else if (ctrl->nand_version >= 0x0400) in brcmnand_revision_init()
725 ctrl->block_sizes = block_sizes_v4; in brcmnand_revision_init()
726 else if (ctrl->nand_version >= 0x0202) in brcmnand_revision_init()
727 ctrl->block_sizes = block_sizes_v2_2; in brcmnand_revision_init()
729 ctrl->block_sizes = block_sizes_v2_1; in brcmnand_revision_init()
731 if (ctrl->nand_version < 0x0400) { in brcmnand_revision_init()
732 if (ctrl->nand_version < 0x0202) in brcmnand_revision_init()
733 ctrl->max_page_size = 2048; in brcmnand_revision_init()
735 ctrl->max_page_size = 4096; in brcmnand_revision_init()
736 ctrl->max_block_size = 512 * 1024; in brcmnand_revision_init()
741 if (ctrl->nand_version == 0x0702) in brcmnand_revision_init()
742 ctrl->max_oob = 128; in brcmnand_revision_init()
743 else if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
744 ctrl->max_oob = 64; in brcmnand_revision_init()
745 else if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
746 ctrl->max_oob = 32; in brcmnand_revision_init()
748 ctrl->max_oob = 16; in brcmnand_revision_init()
751 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601) in brcmnand_revision_init()
752 ctrl->features |= BRCMNAND_HAS_PREFETCH; in brcmnand_revision_init()
758 if (ctrl->nand_version >= 0x0700) in brcmnand_revision_init()
759 ctrl->features |= BRCMNAND_HAS_CACHE_MODE; in brcmnand_revision_init()
761 if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
762 ctrl->features |= BRCMNAND_HAS_1K_SECTORS; in brcmnand_revision_init()
764 if (ctrl->nand_version >= 0x0700) in brcmnand_revision_init()
765 ctrl->features |= BRCMNAND_HAS_WP; in brcmnand_revision_init()
766 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp")) in brcmnand_revision_init()
767 ctrl->features |= BRCMNAND_HAS_WP; in brcmnand_revision_init()
770 if (ctrl->nand_version == 0x0702) in brcmnand_revision_init()
771 ctrl->ecc_level_shift = ACC_CONTROL_ECC_EXT_SHIFT; in brcmnand_revision_init()
773 ctrl->ecc_level_shift = ACC_CONTROL_ECC_SHIFT; in brcmnand_revision_init()
778 static void brcmnand_flash_dma_revision_init(struct brcmnand_controller *ctrl) in brcmnand_flash_dma_revision_init() argument
781 if (ctrl->nand_version >= 0x0703) in brcmnand_flash_dma_revision_init()
782 ctrl->flash_dma_offsets = flash_dma_regs_v4; in brcmnand_flash_dma_revision_init()
783 else if (ctrl->nand_version == 0x0602) in brcmnand_flash_dma_revision_init()
784 ctrl->flash_dma_offsets = flash_dma_regs_v0; in brcmnand_flash_dma_revision_init()
786 ctrl->flash_dma_offsets = flash_dma_regs_v1; in brcmnand_flash_dma_revision_init()
789 static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl, in brcmnand_read_reg() argument
792 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_read_reg()
795 return nand_readreg(ctrl, offs); in brcmnand_read_reg()
800 static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl, in brcmnand_write_reg() argument
803 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_write_reg()
806 nand_writereg(ctrl, offs, val); in brcmnand_write_reg()
809 static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl, in brcmnand_rmw_reg() argument
813 u32 tmp = brcmnand_read_reg(ctrl, reg); in brcmnand_rmw_reg()
817 brcmnand_write_reg(ctrl, reg, tmp); in brcmnand_rmw_reg()
820 static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word) in brcmnand_read_fc() argument
822 if (brcmnand_non_mmio_ops(ctrl)) in brcmnand_read_fc()
823 return brcmnand_soc_read(ctrl->soc, BRCMNAND_NON_MMIO_FC_ADDR); in brcmnand_read_fc()
824 return __raw_readl(ctrl->nand_fc + word * 4); in brcmnand_read_fc()
827 static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl, in brcmnand_write_fc() argument
830 if (brcmnand_non_mmio_ops(ctrl)) in brcmnand_write_fc()
831 brcmnand_soc_write(ctrl->soc, val, BRCMNAND_NON_MMIO_FC_ADDR); in brcmnand_write_fc()
833 __raw_writel(val, ctrl->nand_fc + word * 4); in brcmnand_write_fc()
836 static inline void edu_writel(struct brcmnand_controller *ctrl, in edu_writel() argument
839 u16 offs = ctrl->edu_offsets[reg]; in edu_writel()
841 brcmnand_writel(val, ctrl->edu_base + offs); in edu_writel()
844 static inline u32 edu_readl(struct brcmnand_controller *ctrl, in edu_readl() argument
847 u16 offs = ctrl->edu_offsets[reg]; in edu_readl()
849 return brcmnand_readl(ctrl->edu_base + offs); in edu_readl()
852 static void brcmnand_clear_ecc_addr(struct brcmnand_controller *ctrl) in brcmnand_clear_ecc_addr() argument
856 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0); in brcmnand_clear_ecc_addr()
857 brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0); in brcmnand_clear_ecc_addr()
858 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0); in brcmnand_clear_ecc_addr()
859 brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0); in brcmnand_clear_ecc_addr()
862 static u64 brcmnand_get_uncorrecc_addr(struct brcmnand_controller *ctrl) in brcmnand_get_uncorrecc_addr() argument
866 err_addr = brcmnand_read_reg(ctrl, BRCMNAND_UNCORR_ADDR); in brcmnand_get_uncorrecc_addr()
867 err_addr |= ((u64)(brcmnand_read_reg(ctrl, in brcmnand_get_uncorrecc_addr()
874 static u64 brcmnand_get_correcc_addr(struct brcmnand_controller *ctrl) in brcmnand_get_correcc_addr() argument
878 err_addr = brcmnand_read_reg(ctrl, BRCMNAND_CORR_ADDR); in brcmnand_get_correcc_addr()
879 err_addr |= ((u64)(brcmnand_read_reg(ctrl, in brcmnand_get_correcc_addr()
890 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_cmd_addr() local
892 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS, in brcmnand_set_cmd_addr()
894 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS); in brcmnand_set_cmd_addr()
895 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, in brcmnand_set_cmd_addr()
897 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); in brcmnand_set_cmd_addr()
900 static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs, in brcmnand_cs_offset() argument
903 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE]; in brcmnand_cs_offset()
904 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE]; in brcmnand_cs_offset()
907 if (cs == 0 && ctrl->cs0_offsets) in brcmnand_cs_offset()
908 cs_offs = ctrl->cs0_offsets[reg]; in brcmnand_cs_offset()
910 cs_offs = ctrl->cs_offsets[reg]; in brcmnand_cs_offset()
913 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs; in brcmnand_cs_offset()
915 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs; in brcmnand_cs_offset()
918 static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl) in brcmnand_count_corrected() argument
920 if (ctrl->nand_version < 0x0600) in brcmnand_count_corrected()
922 return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT); in brcmnand_count_corrected()
927 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_wr_corr_thresh() local
932 if (!ctrl->reg_offsets[reg]) in brcmnand_wr_corr_thresh()
935 if (ctrl->nand_version == 0x0702) in brcmnand_wr_corr_thresh()
937 else if (ctrl->nand_version >= 0x0600) in brcmnand_wr_corr_thresh()
939 else if (ctrl->nand_version >= 0x0500) in brcmnand_wr_corr_thresh()
944 if (ctrl->nand_version >= 0x0702) { in brcmnand_wr_corr_thresh()
948 } else if (ctrl->nand_version >= 0x0600) { in brcmnand_wr_corr_thresh()
953 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val); in brcmnand_wr_corr_thresh()
956 static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl) in brcmnand_cmd_shift() argument
961 if (ctrl->nand_version == 0x0304 && brcmnand_non_mmio_ops(ctrl)) in brcmnand_cmd_shift()
964 if (ctrl->nand_version < 0x0602) in brcmnand_cmd_shift()
969 static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl) in brcmnand_spare_area_mask() argument
971 if (ctrl->nand_version == 0x0702) in brcmnand_spare_area_mask()
973 else if (ctrl->nand_version >= 0x0600) in brcmnand_spare_area_mask()
975 else if (ctrl->nand_version >= 0x0303) in brcmnand_spare_area_mask()
981 static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl) in brcmnand_ecc_level_mask() argument
983 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f; in brcmnand_ecc_level_mask()
988 if (ctrl->nand_version == 0x0702) in brcmnand_ecc_level_mask()
996 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_ecc_enabled() local
997 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); in brcmnand_set_ecc_enabled()
998 u32 acc_control = nand_readreg(ctrl, offs); in brcmnand_set_ecc_enabled()
1003 acc_control &= ~brcmnand_ecc_level_mask(ctrl); in brcmnand_set_ecc_enabled()
1004 acc_control |= host->hwcfg.ecc_level << ctrl->ecc_level_shift; in brcmnand_set_ecc_enabled()
1007 acc_control &= ~brcmnand_ecc_level_mask(ctrl); in brcmnand_set_ecc_enabled()
1010 nand_writereg(ctrl, offs, acc_control); in brcmnand_set_ecc_enabled()
1013 static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl) in brcmnand_sector_1k_shift() argument
1015 if (ctrl->nand_version >= 0x0702) in brcmnand_sector_1k_shift()
1017 else if (ctrl->nand_version >= 0x0600) in brcmnand_sector_1k_shift()
1019 else if (ctrl->nand_version >= 0x0500) in brcmnand_sector_1k_shift()
1027 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_get_sector_size_1k() local
1028 int shift = brcmnand_sector_1k_shift(ctrl); in brcmnand_get_sector_size_1k()
1029 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_get_sector_size_1k()
1035 return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1; in brcmnand_get_sector_size_1k()
1040 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_sector_size_1k() local
1041 int shift = brcmnand_sector_1k_shift(ctrl); in brcmnand_set_sector_size_1k()
1042 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_sector_size_1k()
1049 tmp = nand_readreg(ctrl, acc_control_offs); in brcmnand_set_sector_size_1k()
1052 nand_writereg(ctrl, acc_control_offs, tmp); in brcmnand_set_sector_size_1k()
1064 static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl, in bcmnand_ctrl_poll_status() argument
1076 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); in bcmnand_ctrl_poll_status()
1087 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); in bcmnand_ctrl_poll_status()
1091 dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n", in bcmnand_ctrl_poll_status()
1097 static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en) in brcmnand_set_wp() argument
1101 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val); in brcmnand_set_wp()
1108 static inline bool has_flash_dma(struct brcmnand_controller *ctrl) in has_flash_dma() argument
1110 return ctrl->flash_dma_base; in has_flash_dma()
1113 static inline bool has_edu(struct brcmnand_controller *ctrl) in has_edu() argument
1115 return ctrl->edu_base; in has_edu()
1118 static inline bool use_dma(struct brcmnand_controller *ctrl) in use_dma() argument
1120 return has_flash_dma(ctrl) || has_edu(ctrl); in use_dma()
1123 static inline void disable_ctrl_irqs(struct brcmnand_controller *ctrl) in disable_ctrl_irqs() argument
1125 if (ctrl->pio_poll_mode) in disable_ctrl_irqs()
1128 if (has_flash_dma(ctrl)) { in disable_ctrl_irqs()
1129 ctrl->flash_dma_base = NULL; in disable_ctrl_irqs()
1130 disable_irq(ctrl->dma_irq); in disable_ctrl_irqs()
1133 disable_irq(ctrl->irq); in disable_ctrl_irqs()
1134 ctrl->pio_poll_mode = true; in disable_ctrl_irqs()
1143 static inline void flash_dma_writel(struct brcmnand_controller *ctrl, in flash_dma_writel() argument
1146 u16 offs = ctrl->flash_dma_offsets[dma_reg]; in flash_dma_writel()
1148 brcmnand_writel(val, ctrl->flash_dma_base + offs); in flash_dma_writel()
1151 static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, in flash_dma_readl() argument
1154 u16 offs = ctrl->flash_dma_offsets[dma_reg]; in flash_dma_readl()
1156 return brcmnand_readl(ctrl->flash_dma_base + offs); in flash_dma_readl()
1171 static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl, in is_hamming_ecc() argument
1174 if (ctrl->nand_version <= 0x0701) in is_hamming_ecc()
1335 if (is_hamming_ecc(host->ctrl, p)) { in brcmstb_choose_ecc_layout()
1367 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_wp() local
1369 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) { in brcmnand_wp()
1374 dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off"); in brcmnand_wp()
1382 ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY | in brcmnand_wp()
1389 brcmnand_set_wp(ctrl, wp); in brcmnand_wp()
1392 ret = bcmnand_ctrl_poll_status(ctrl, in brcmnand_wp()
1408 static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs) in oob_reg_read() argument
1412 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE]; in oob_reg_read()
1413 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE]; in oob_reg_read()
1415 if (offs >= ctrl->max_oob) in oob_reg_read()
1423 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3)); in oob_reg_read()
1426 static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs, in oob_reg_write() argument
1431 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE]; in oob_reg_write()
1432 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE]; in oob_reg_write()
1434 if (offs >= ctrl->max_oob) in oob_reg_write()
1442 nand_writereg(ctrl, reg_offs, data); in oob_reg_write()
1453 static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob, in read_oob_from_regs() argument
1461 tbytes = max(0, tbytes - (int)ctrl->max_oob); in read_oob_from_regs()
1462 tbytes = min_t(int, tbytes, ctrl->max_oob); in read_oob_from_regs()
1465 oob[j] = oob_reg_read(ctrl, j); in read_oob_from_regs()
1476 static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i, in write_oob_to_regs() argument
1486 tbytes = max(0, tbytes - (int)ctrl->max_oob); in write_oob_to_regs()
1487 tbytes = min_t(int, tbytes, ctrl->max_oob); in write_oob_to_regs()
1494 oob_reg_write(ctrl, j, in write_oob_to_regs()
1505 oob_reg_write(ctrl, (tbytes & ~0x3), (__force u32)cpu_to_be32(last)); in write_oob_to_regs()
1510 static void brcmnand_edu_init(struct brcmnand_controller *ctrl) in brcmnand_edu_init() argument
1513 edu_writel(ctrl, EDU_ERR_STATUS, 0); in brcmnand_edu_init()
1514 edu_readl(ctrl, EDU_ERR_STATUS); in brcmnand_edu_init()
1515 edu_writel(ctrl, EDU_DONE, 0); in brcmnand_edu_init()
1516 edu_writel(ctrl, EDU_DONE, 0); in brcmnand_edu_init()
1517 edu_writel(ctrl, EDU_DONE, 0); in brcmnand_edu_init()
1518 edu_writel(ctrl, EDU_DONE, 0); in brcmnand_edu_init()
1519 edu_readl(ctrl, EDU_DONE); in brcmnand_edu_init()
1525 struct brcmnand_controller *ctrl = data; in brcmnand_edu_irq() local
1527 if (ctrl->edu_count) { in brcmnand_edu_irq()
1528 ctrl->edu_count--; in brcmnand_edu_irq()
1529 while (!(edu_readl(ctrl, EDU_DONE) & EDU_DONE_MASK)) in brcmnand_edu_irq()
1531 edu_writel(ctrl, EDU_DONE, 0); in brcmnand_edu_irq()
1532 edu_readl(ctrl, EDU_DONE); in brcmnand_edu_irq()
1535 if (ctrl->edu_count) { in brcmnand_edu_irq()
1536 ctrl->edu_dram_addr += FC_BYTES; in brcmnand_edu_irq()
1537 ctrl->edu_ext_addr += FC_BYTES; in brcmnand_edu_irq()
1539 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr); in brcmnand_edu_irq()
1540 edu_readl(ctrl, EDU_DRAM_ADDR); in brcmnand_edu_irq()
1541 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr); in brcmnand_edu_irq()
1542 edu_readl(ctrl, EDU_EXT_ADDR); in brcmnand_edu_irq()
1544 if (ctrl->oob) { in brcmnand_edu_irq()
1545 if (ctrl->edu_cmd == EDU_CMD_READ) { in brcmnand_edu_irq()
1546 ctrl->oob += read_oob_from_regs(ctrl, in brcmnand_edu_irq()
1547 ctrl->edu_count + 1, in brcmnand_edu_irq()
1548 ctrl->oob, ctrl->sas, in brcmnand_edu_irq()
1549 ctrl->sector_size_1k); in brcmnand_edu_irq()
1551 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, in brcmnand_edu_irq()
1552 ctrl->edu_ext_addr); in brcmnand_edu_irq()
1553 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); in brcmnand_edu_irq()
1554 ctrl->oob += write_oob_to_regs(ctrl, in brcmnand_edu_irq()
1555 ctrl->edu_count, in brcmnand_edu_irq()
1556 ctrl->oob, ctrl->sas, in brcmnand_edu_irq()
1557 ctrl->sector_size_1k); in brcmnand_edu_irq()
1562 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd); in brcmnand_edu_irq()
1563 edu_readl(ctrl, EDU_CMD); in brcmnand_edu_irq()
1568 complete(&ctrl->edu_done); in brcmnand_edu_irq()
1575 struct brcmnand_controller *ctrl = data; in brcmnand_ctlrdy_irq() local
1578 if (ctrl->dma_pending) in brcmnand_ctlrdy_irq()
1582 if (ctrl->edu_pending) { in brcmnand_ctlrdy_irq()
1583 if (irq == ctrl->irq && ((int)ctrl->edu_irq >= 0)) in brcmnand_ctlrdy_irq()
1591 complete(&ctrl->done); in brcmnand_ctlrdy_irq()
1598 struct brcmnand_controller *ctrl = data; in brcmnand_irq() local
1600 if (ctrl->soc->ctlrdy_ack(ctrl->soc)) in brcmnand_irq()
1608 struct brcmnand_controller *ctrl = data; in brcmnand_dma_irq() local
1610 complete(&ctrl->dma_done); in brcmnand_dma_irq()
1617 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_send_cmd() local
1621 cmd_addr = brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); in brcmnand_send_cmd()
1623 dev_dbg(ctrl->dev, "send native cmd %d addr 0x%llx\n", cmd, cmd_addr); in brcmnand_send_cmd()
1631 if (ctrl->cmd_pending && in brcmnand_send_cmd()
1632 bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0)) in brcmnand_send_cmd()
1635 BUG_ON(ctrl->cmd_pending != 0); in brcmnand_send_cmd()
1636 ctrl->cmd_pending = cmd; in brcmnand_send_cmd()
1638 ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0); in brcmnand_send_cmd()
1642 brcmnand_write_reg(ctrl, BRCMNAND_CMD_START, in brcmnand_send_cmd()
1643 cmd << brcmnand_cmd_shift(ctrl)); in brcmnand_send_cmd()
1651 unsigned int ctrl) in brcmnand_cmd_ctrl() argument
1659 struct brcmnand_controller *ctrl = host->ctrl; in brcmstb_nand_wait_for_completion() local
1664 if (mtd->oops_panic_write || ctrl->irq < 0) { in brcmstb_nand_wait_for_completion()
1666 disable_ctrl_irqs(ctrl); in brcmstb_nand_wait_for_completion()
1667 sts = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, in brcmstb_nand_wait_for_completion()
1674 sts = wait_for_completion_timeout(&ctrl->done, timeo); in brcmstb_nand_wait_for_completion()
1684 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_waitfunc() local
1687 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending); in brcmnand_waitfunc()
1688 if (ctrl->cmd_pending) in brcmnand_waitfunc()
1691 ctrl->cmd_pending = 0; in brcmnand_waitfunc()
1693 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START) in brcmnand_waitfunc()
1694 >> brcmnand_cmd_shift(ctrl); in brcmnand_waitfunc()
1696 dev_err_ratelimited(ctrl->dev, in brcmnand_waitfunc()
1698 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n", in brcmnand_waitfunc()
1699 brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS)); in brcmnand_waitfunc()
1702 return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & in brcmnand_waitfunc()
1721 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_low_level_op() local
1746 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp); in brcmnand_low_level_op()
1748 brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp); in brcmnand_low_level_op()
1749 (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP); in brcmnand_low_level_op()
1760 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_cmdfunc() local
1771 dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command, in brcmnand_cmdfunc()
1828 u32 *flash_cache = (u32 *)ctrl->flash_cache; in brcmnand_cmdfunc()
1831 brcmnand_soc_data_bus_prepare(ctrl->soc, true); in brcmnand_cmdfunc()
1842 flash_cache[i] = be32_to_cpu(brcmnand_read_fc(ctrl, i)); in brcmnand_cmdfunc()
1844 brcmnand_soc_data_bus_unprepare(ctrl->soc, true); in brcmnand_cmdfunc()
1860 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read_byte() local
1867 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >> in brcmnand_read_byte()
1870 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >> in brcmnand_read_byte()
1875 ret = oob_reg_read(ctrl, host->last_byte); in brcmnand_read_byte()
1879 ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & in brcmnand_read_byte()
1894 ret = ctrl->flash_cache[offs]; in brcmnand_read_byte()
1903 ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff; in brcmnand_read_byte()
1907 dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret); in brcmnand_read_byte()
1945 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_edu_trans() local
1954 dev_dbg(ctrl->dev, "EDU %s %p:%p\n", ((edu_cmd == EDU_CMD_READ) ? in brcmnand_edu_trans()
1957 pa = dma_map_single(ctrl->dev, buf, len, dir); in brcmnand_edu_trans()
1958 if (dma_mapping_error(ctrl->dev, pa)) { in brcmnand_edu_trans()
1959 dev_err(ctrl->dev, "unable to map buffer for EDU DMA\n"); in brcmnand_edu_trans()
1963 ctrl->edu_pending = true; in brcmnand_edu_trans()
1964 ctrl->edu_dram_addr = pa; in brcmnand_edu_trans()
1965 ctrl->edu_ext_addr = addr; in brcmnand_edu_trans()
1966 ctrl->edu_cmd = edu_cmd; in brcmnand_edu_trans()
1967 ctrl->edu_count = trans; in brcmnand_edu_trans()
1968 ctrl->sas = cfg->spare_area_size; in brcmnand_edu_trans()
1969 ctrl->oob = oob; in brcmnand_edu_trans()
1971 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr); in brcmnand_edu_trans()
1972 edu_readl(ctrl, EDU_DRAM_ADDR); in brcmnand_edu_trans()
1973 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr); in brcmnand_edu_trans()
1974 edu_readl(ctrl, EDU_EXT_ADDR); in brcmnand_edu_trans()
1975 edu_writel(ctrl, EDU_LENGTH, FC_BYTES); in brcmnand_edu_trans()
1976 edu_readl(ctrl, EDU_LENGTH); in brcmnand_edu_trans()
1978 if (ctrl->oob && (ctrl->edu_cmd == EDU_CMD_WRITE)) { in brcmnand_edu_trans()
1979 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, in brcmnand_edu_trans()
1980 ctrl->edu_ext_addr); in brcmnand_edu_trans()
1981 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); in brcmnand_edu_trans()
1982 ctrl->oob += write_oob_to_regs(ctrl, in brcmnand_edu_trans()
1984 ctrl->oob, ctrl->sas, in brcmnand_edu_trans()
1985 ctrl->sector_size_1k); in brcmnand_edu_trans()
1990 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd); in brcmnand_edu_trans()
1991 edu_readl(ctrl, EDU_CMD); in brcmnand_edu_trans()
1993 if (wait_for_completion_timeout(&ctrl->edu_done, timeo) <= 0) { in brcmnand_edu_trans()
1994 dev_err(ctrl->dev, in brcmnand_edu_trans()
1996 edu_readl(ctrl, EDU_STATUS), in brcmnand_edu_trans()
1997 edu_readl(ctrl, EDU_ERR_STATUS)); in brcmnand_edu_trans()
2000 dma_unmap_single(ctrl->dev, pa, len, dir); in brcmnand_edu_trans()
2003 if (ctrl->oob && (ctrl->edu_cmd == EDU_CMD_READ)) { in brcmnand_edu_trans()
2004 ctrl->oob += read_oob_from_regs(ctrl, in brcmnand_edu_trans()
2006 ctrl->oob, ctrl->sas, in brcmnand_edu_trans()
2007 ctrl->sector_size_1k); in brcmnand_edu_trans()
2011 if (((brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & in brcmnand_edu_trans()
2014 dev_info(ctrl->dev, "program failed at %llx\n", in brcmnand_edu_trans()
2020 if (edu_readl(ctrl, EDU_STATUS) & EDU_STATUS_ACTIVE) in brcmnand_edu_trans()
2021 dev_warn(ctrl->dev, "EDU still active: %#x\n", in brcmnand_edu_trans()
2022 edu_readl(ctrl, EDU_STATUS)); in brcmnand_edu_trans()
2024 if (unlikely(edu_readl(ctrl, EDU_ERR_STATUS) & EDU_ERR_STATUS_ERRACK)) { in brcmnand_edu_trans()
2025 dev_warn(ctrl->dev, "EDU RBUS error at addr %llx\n", in brcmnand_edu_trans()
2030 ctrl->edu_pending = false; in brcmnand_edu_trans()
2031 brcmnand_edu_init(ctrl); in brcmnand_edu_trans()
2032 edu_writel(ctrl, EDU_STOP, 0); /* force stop */ in brcmnand_edu_trans()
2033 edu_readl(ctrl, EDU_STOP); in brcmnand_edu_trans()
2042 err_addr = brcmnand_get_uncorrecc_addr(ctrl); in brcmnand_edu_trans()
2044 err_addr = brcmnand_get_correcc_addr(ctrl); in brcmnand_edu_trans()
2092 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_dma_run() local
2095 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc)); in brcmnand_dma_run()
2096 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC); in brcmnand_dma_run()
2097 if (ctrl->nand_version > 0x0602) { in brcmnand_dma_run()
2098 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, in brcmnand_dma_run()
2100 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT); in brcmnand_dma_run()
2104 ctrl->dma_pending = true; in brcmnand_dma_run()
2106 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */ in brcmnand_dma_run()
2108 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) { in brcmnand_dma_run()
2109 dev_err(ctrl->dev, in brcmnand_dma_run()
2111 flash_dma_readl(ctrl, FLASH_DMA_STATUS), in brcmnand_dma_run()
2112 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS)); in brcmnand_dma_run()
2114 ctrl->dma_pending = false; in brcmnand_dma_run()
2115 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */ in brcmnand_dma_run()
2121 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_dma_trans() local
2125 buf_pa = dma_map_single(ctrl->dev, buf, len, dir); in brcmnand_dma_trans()
2126 if (dma_mapping_error(ctrl->dev, buf_pa)) { in brcmnand_dma_trans()
2127 dev_err(ctrl->dev, "unable to map buffer for DMA\n"); in brcmnand_dma_trans()
2131 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len, in brcmnand_dma_trans()
2134 brcmnand_dma_run(host, ctrl->dma_pa); in brcmnand_dma_trans()
2136 dma_unmap_single(ctrl->dev, buf_pa, len, dir); in brcmnand_dma_trans()
2138 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR) in brcmnand_dma_trans()
2140 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR) in brcmnand_dma_trans()
2154 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read_by_pio() local
2157 brcmnand_clear_ecc_addr(ctrl); in brcmnand_read_by_pio()
2166 brcmnand_soc_data_bus_prepare(ctrl->soc, false); in brcmnand_read_by_pio()
2169 *buf = brcmnand_read_fc(ctrl, j); in brcmnand_read_by_pio()
2171 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); in brcmnand_read_by_pio()
2175 oob += read_oob_from_regs(ctrl, i, oob, in brcmnand_read_by_pio()
2180 *err_addr = brcmnand_get_uncorrecc_addr(ctrl); in brcmnand_read_by_pio()
2187 *err_addr = brcmnand_get_correcc_addr(ctrl); in brcmnand_read_by_pio()
2253 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read() local
2259 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf); in brcmnand_read()
2262 brcmnand_clear_ecc_addr(ctrl); in brcmnand_read()
2264 if (ctrl->dma_trans && (has_edu(ctrl) || !oob) && in brcmnand_read()
2266 err = ctrl->dma_trans(host, addr, buf, oob, in brcmnand_read()
2277 if (has_edu(ctrl) && err_addr) in brcmnand_read()
2297 if ((ctrl->nand_version == 0x0700) || in brcmnand_read()
2298 (ctrl->nand_version == 0x0701)) { in brcmnand_read()
2309 if (ctrl->nand_version < 0x0702) { in brcmnand_read()
2317 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n", in brcmnand_read()
2325 unsigned int corrected = brcmnand_count_corrected(ctrl); in brcmnand_read()
2332 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n", in brcmnand_read()
2398 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_write() local
2402 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf); in brcmnand_write()
2405 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf); in brcmnand_write()
2411 for (i = 0; i < ctrl->max_oob; i += 4) in brcmnand_write()
2412 oob_reg_write(ctrl, i, 0xffffffff); in brcmnand_write()
2416 disable_ctrl_irqs(ctrl); in brcmnand_write()
2418 if (use_dma(ctrl) && (has_edu(ctrl) || !oob) && flash_dma_buf_ok(buf)) { in brcmnand_write()
2419 if (ctrl->dma_trans(host, addr, (u32 *)buf, oob, mtd->writesize, in brcmnand_write()
2432 brcmnand_soc_data_bus_prepare(ctrl->soc, false); in brcmnand_write()
2435 brcmnand_write_fc(ctrl, j, *buf); in brcmnand_write()
2437 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); in brcmnand_write()
2440 brcmnand_write_fc(ctrl, j, 0xffffffff); in brcmnand_write()
2444 oob += write_oob_to_regs(ctrl, i, oob, in brcmnand_write()
2454 dev_info(ctrl->dev, "program failed at %llx\n", in brcmnand_write()
2521 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_cfg() local
2523 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_set_cfg()
2524 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_cfg()
2526 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_cfg()
2531 if (ctrl->block_sizes) { in brcmnand_set_cfg()
2534 for (i = 0, found = 0; ctrl->block_sizes[i]; i++) in brcmnand_set_cfg()
2535 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) { in brcmnand_set_cfg()
2540 dev_warn(ctrl->dev, "invalid block size %u\n", in brcmnand_set_cfg()
2548 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size && in brcmnand_set_cfg()
2549 cfg->block_size > ctrl->max_block_size)) { in brcmnand_set_cfg()
2550 dev_warn(ctrl->dev, "invalid block size %u\n", in brcmnand_set_cfg()
2555 if (ctrl->page_sizes) { in brcmnand_set_cfg()
2558 for (i = 0, found = 0; ctrl->page_sizes[i]; i++) in brcmnand_set_cfg()
2559 if (ctrl->page_sizes[i] == cfg->page_size) { in brcmnand_set_cfg()
2564 dev_warn(ctrl->dev, "invalid page size %u\n", in brcmnand_set_cfg()
2572 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size && in brcmnand_set_cfg()
2573 cfg->page_size > ctrl->max_page_size)) { in brcmnand_set_cfg()
2574 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size); in brcmnand_set_cfg()
2579 dev_warn(ctrl->dev, "invalid device size 0x%llx\n", in brcmnand_set_cfg()
2591 tmp |= (page_size << ctrl->page_size_shift) | in brcmnand_set_cfg()
2593 nand_writereg(ctrl, cfg_offs, tmp); in brcmnand_set_cfg()
2595 nand_writereg(ctrl, cfg_offs, tmp); in brcmnand_set_cfg()
2598 nand_writereg(ctrl, cfg_ext_offs, tmp); in brcmnand_set_cfg()
2601 tmp = nand_readreg(ctrl, acc_control_offs); in brcmnand_set_cfg()
2602 tmp &= ~brcmnand_ecc_level_mask(ctrl); in brcmnand_set_cfg()
2603 tmp &= ~brcmnand_spare_area_mask(ctrl); in brcmnand_set_cfg()
2604 if (ctrl->nand_version >= 0x0302) { in brcmnand_set_cfg()
2605 tmp |= cfg->ecc_level << ctrl->ecc_level_shift; in brcmnand_set_cfg()
2608 nand_writereg(ctrl, acc_control_offs, tmp); in brcmnand_set_cfg()
2630 if (is_hamming_ecc(host->ctrl, cfg)) in brcmnand_print_cfg()
2658 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_setup_dev() local
2676 if (cfg->spare_area_size > ctrl->max_oob) in brcmnand_setup_dev()
2677 cfg->spare_area_size = ctrl->max_oob; in brcmnand_setup_dev()
2693 dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n", in brcmnand_setup_dev()
2709 dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n", in brcmnand_setup_dev()
2720 dev_info(ctrl->dev, "Using ECC step-size %d, strength %d\n", in brcmnand_setup_dev()
2734 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) { in brcmnand_setup_dev()
2735 dev_err(ctrl->dev, "1KB sectors not supported\n"); in brcmnand_setup_dev()
2739 dev_err(ctrl->dev, in brcmnand_setup_dev()
2748 dev_err(ctrl->dev, "unsupported ECC size: %d\n", in brcmnand_setup_dev()
2766 dev_info(ctrl->dev, "detected %s\n", msg); in brcmnand_setup_dev()
2769 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); in brcmnand_setup_dev()
2770 tmp = nand_readreg(ctrl, offs); in brcmnand_setup_dev()
2775 if (ctrl->nand_version >= 0x0702) in brcmnand_setup_dev()
2778 if (ctrl->features & BRCMNAND_HAS_PREFETCH) in brcmnand_setup_dev()
2781 nand_writereg(ctrl, offs, tmp); in brcmnand_setup_dev()
2814 if (is_hamming_ecc(host->ctrl, &host->hwcfg)) { in brcmnand_attach_chip()
2829 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_init_cs() local
2830 struct device *dev = ctrl->dev; in brcmnand_init_cs()
2865 chip->controller = &ctrl->controller; in brcmnand_init_cs()
2872 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_init_cs()
2873 nand_writereg(ctrl, cfg_offs, in brcmnand_init_cs()
2874 nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH); in brcmnand_init_cs()
2890 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_save_restore_cs_config() local
2891 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_save_restore_cs_config()
2892 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_save_restore_cs_config()
2894 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_save_restore_cs_config()
2896 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1); in brcmnand_save_restore_cs_config()
2897 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2); in brcmnand_save_restore_cs_config()
2900 nand_writereg(ctrl, cfg_offs, host->hwcfg.config); in brcmnand_save_restore_cs_config()
2902 nand_writereg(ctrl, cfg_ext_offs, in brcmnand_save_restore_cs_config()
2904 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control); in brcmnand_save_restore_cs_config()
2905 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1); in brcmnand_save_restore_cs_config()
2906 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2); in brcmnand_save_restore_cs_config()
2908 host->hwcfg.config = nand_readreg(ctrl, cfg_offs); in brcmnand_save_restore_cs_config()
2911 nand_readreg(ctrl, cfg_ext_offs); in brcmnand_save_restore_cs_config()
2912 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs); in brcmnand_save_restore_cs_config()
2913 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs); in brcmnand_save_restore_cs_config()
2914 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs); in brcmnand_save_restore_cs_config()
2920 struct brcmnand_controller *ctrl = dev_get_drvdata(dev); in brcmnand_suspend() local
2923 list_for_each_entry(host, &ctrl->host_list, node) in brcmnand_suspend()
2926 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT); in brcmnand_suspend()
2927 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR); in brcmnand_suspend()
2928 ctrl->corr_stat_threshold = in brcmnand_suspend()
2929 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD); in brcmnand_suspend()
2931 if (has_flash_dma(ctrl)) in brcmnand_suspend()
2932 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE); in brcmnand_suspend()
2933 else if (has_edu(ctrl)) in brcmnand_suspend()
2934 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG); in brcmnand_suspend()
2941 struct brcmnand_controller *ctrl = dev_get_drvdata(dev); in brcmnand_resume() local
2944 if (has_flash_dma(ctrl)) { in brcmnand_resume()
2945 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode); in brcmnand_resume()
2946 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0); in brcmnand_resume()
2949 if (has_edu(ctrl)) { in brcmnand_resume()
2950 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG); in brcmnand_resume()
2951 edu_writel(ctrl, EDU_CONFIG, ctrl->edu_config); in brcmnand_resume()
2952 edu_readl(ctrl, EDU_CONFIG); in brcmnand_resume()
2953 brcmnand_edu_init(ctrl); in brcmnand_resume()
2956 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select); in brcmnand_resume()
2957 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor); in brcmnand_resume()
2958 brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD, in brcmnand_resume()
2959 ctrl->corr_stat_threshold); in brcmnand_resume()
2960 if (ctrl->soc) { in brcmnand_resume()
2962 ctrl->soc->ctlrdy_ack(ctrl->soc); in brcmnand_resume()
2963 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); in brcmnand_resume()
2966 list_for_each_entry(host, &ctrl->host_list, node) { in brcmnand_resume()
3006 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); in brcmnand_edu_setup() local
3012 ctrl->edu_base = devm_ioremap_resource(dev, res); in brcmnand_edu_setup()
3013 if (IS_ERR(ctrl->edu_base)) in brcmnand_edu_setup()
3014 return PTR_ERR(ctrl->edu_base); in brcmnand_edu_setup()
3016 ctrl->edu_offsets = edu_regs; in brcmnand_edu_setup()
3018 edu_writel(ctrl, EDU_CONFIG, EDU_CONFIG_MODE_NAND | in brcmnand_edu_setup()
3020 edu_readl(ctrl, EDU_CONFIG); in brcmnand_edu_setup()
3023 brcmnand_edu_init(ctrl); in brcmnand_edu_setup()
3025 ctrl->edu_irq = platform_get_irq_optional(pdev, 1); in brcmnand_edu_setup()
3026 if (ctrl->edu_irq < 0) { in brcmnand_edu_setup()
3030 ret = devm_request_irq(dev, ctrl->edu_irq, in brcmnand_edu_setup()
3032 "brcmnand-edu", ctrl); in brcmnand_edu_setup()
3034 dev_err(ctrl->dev, "can't allocate IRQ %d: error %d\n", in brcmnand_edu_setup()
3035 ctrl->edu_irq, ret); in brcmnand_edu_setup()
3040 ctrl->edu_irq); in brcmnand_edu_setup()
3052 struct brcmnand_controller *ctrl; in brcmnand_probe() local
3060 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); in brcmnand_probe()
3061 if (!ctrl) in brcmnand_probe()
3064 dev_set_drvdata(dev, ctrl); in brcmnand_probe()
3065 ctrl->dev = dev; in brcmnand_probe()
3066 ctrl->soc = soc; in brcmnand_probe()
3071 if (brcmnand_soc_has_ops(ctrl->soc)) in brcmnand_probe()
3074 init_completion(&ctrl->done); in brcmnand_probe()
3075 init_completion(&ctrl->dma_done); in brcmnand_probe()
3076 init_completion(&ctrl->edu_done); in brcmnand_probe()
3077 nand_controller_init(&ctrl->controller); in brcmnand_probe()
3078 ctrl->controller.ops = &brcmnand_controller_ops; in brcmnand_probe()
3079 INIT_LIST_HEAD(&ctrl->host_list); in brcmnand_probe()
3083 ctrl->nand_base = devm_ioremap_resource(dev, res); in brcmnand_probe()
3084 if (IS_ERR(ctrl->nand_base) && !brcmnand_soc_has_ops(soc)) in brcmnand_probe()
3085 return PTR_ERR(ctrl->nand_base); in brcmnand_probe()
3088 ctrl->clk = devm_clk_get(dev, "nand"); in brcmnand_probe()
3089 if (!IS_ERR(ctrl->clk)) { in brcmnand_probe()
3090 ret = clk_prepare_enable(ctrl->clk); in brcmnand_probe()
3094 ret = PTR_ERR(ctrl->clk); in brcmnand_probe()
3098 ctrl->clk = NULL; in brcmnand_probe()
3102 ret = brcmnand_revision_init(ctrl); in brcmnand_probe()
3112 ctrl->nand_fc = devm_ioremap_resource(dev, res); in brcmnand_probe()
3113 if (IS_ERR(ctrl->nand_fc)) { in brcmnand_probe()
3114 ret = PTR_ERR(ctrl->nand_fc); in brcmnand_probe()
3118 ctrl->nand_fc = ctrl->nand_base + in brcmnand_probe()
3119 ctrl->reg_offsets[BRCMNAND_FC_BASE]; in brcmnand_probe()
3125 ctrl->flash_dma_base = devm_ioremap_resource(dev, res); in brcmnand_probe()
3126 if (IS_ERR(ctrl->flash_dma_base)) { in brcmnand_probe()
3127 ret = PTR_ERR(ctrl->flash_dma_base); in brcmnand_probe()
3132 brcmnand_flash_dma_revision_init(ctrl); in brcmnand_probe()
3135 if (ctrl->nand_version >= 0x0700) in brcmnand_probe()
3145 flash_dma_writel(ctrl, FLASH_DMA_MODE, FLASH_DMA_MODE_MASK); in brcmnand_probe()
3146 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0); in brcmnand_probe()
3149 ctrl->dma_desc = dmam_alloc_coherent(dev, in brcmnand_probe()
3150 sizeof(*ctrl->dma_desc), in brcmnand_probe()
3151 &ctrl->dma_pa, GFP_KERNEL); in brcmnand_probe()
3152 if (!ctrl->dma_desc) { in brcmnand_probe()
3157 ctrl->dma_irq = platform_get_irq(pdev, 1); in brcmnand_probe()
3158 if ((int)ctrl->dma_irq < 0) { in brcmnand_probe()
3164 ret = devm_request_irq(dev, ctrl->dma_irq, in brcmnand_probe()
3166 ctrl); in brcmnand_probe()
3169 ctrl->dma_irq, ret); in brcmnand_probe()
3175 ctrl->dma_trans = brcmnand_dma_trans; in brcmnand_probe()
3181 if (has_edu(ctrl)) in brcmnand_probe()
3183 ctrl->dma_trans = brcmnand_edu_trans; in brcmnand_probe()
3187 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, in brcmnand_probe()
3190 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0); in brcmnand_probe()
3192 if (ctrl->features & BRCMNAND_HAS_WP) { in brcmnand_probe()
3195 brcmnand_set_wp(ctrl, false); in brcmnand_probe()
3201 ctrl->irq = platform_get_irq_optional(pdev, 0); in brcmnand_probe()
3202 if (ctrl->irq > 0) { in brcmnand_probe()
3208 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0, in brcmnand_probe()
3209 DRV_NAME, ctrl); in brcmnand_probe()
3212 ctrl->soc->ctlrdy_ack(ctrl->soc); in brcmnand_probe()
3213 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); in brcmnand_probe()
3216 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0, in brcmnand_probe()
3217 DRV_NAME, ctrl); in brcmnand_probe()
3221 ctrl->irq, ret); in brcmnand_probe()
3236 host->ctrl = ctrl; in brcmnand_probe()
3257 list_add_tail(&host->node, &ctrl->host_list); in brcmnand_probe()
3261 if (!list_empty(&ctrl->host_list)) in brcmnand_probe()
3276 host->ctrl = ctrl; in brcmnand_probe()
3285 list_add_tail(&host->node, &ctrl->host_list); in brcmnand_probe()
3288 if (list_empty(&ctrl->host_list)) { in brcmnand_probe()
3296 clk_disable_unprepare(ctrl->clk); in brcmnand_probe()
3304 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); in brcmnand_remove() local
3309 list_for_each_entry(host, &ctrl->host_list, node) { in brcmnand_remove()
3316 clk_disable_unprepare(ctrl->clk); in brcmnand_remove()