Lines Matching refs:dev
59 static inline u32 mei_me_mecbrw_read(const struct mei_device *dev) in mei_me_mecbrw_read() argument
61 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW); in mei_me_mecbrw_read()
70 static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data) in mei_me_hcbww_write() argument
72 mei_me_reg_write(to_me_hw(dev), H_CB_WW, data); in mei_me_hcbww_write()
82 static inline u32 mei_me_mecsr_read(const struct mei_device *dev) in mei_me_mecsr_read() argument
86 reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA); in mei_me_mecsr_read()
87 trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg); in mei_me_mecsr_read()
99 static inline u32 mei_hcsr_read(const struct mei_device *dev) in mei_hcsr_read() argument
103 reg = mei_me_reg_read(to_me_hw(dev), H_CSR); in mei_hcsr_read()
104 trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg); in mei_hcsr_read()
115 static inline void mei_hcsr_write(struct mei_device *dev, u32 reg) in mei_hcsr_write() argument
117 trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg); in mei_hcsr_write()
118 mei_me_reg_write(to_me_hw(dev), H_CSR, reg); in mei_hcsr_write()
128 static inline void mei_hcsr_set(struct mei_device *dev, u32 reg) in mei_hcsr_set() argument
131 mei_hcsr_write(dev, reg); in mei_hcsr_set()
139 static inline void mei_hcsr_set_hig(struct mei_device *dev) in mei_hcsr_set_hig() argument
143 hcsr = mei_hcsr_read(dev) | H_IG; in mei_hcsr_set_hig()
144 mei_hcsr_set(dev, hcsr); in mei_hcsr_set_hig()
154 static inline u32 mei_me_d0i3c_read(const struct mei_device *dev) in mei_me_d0i3c_read() argument
158 reg = mei_me_reg_read(to_me_hw(dev), H_D0I3C); in mei_me_d0i3c_read()
159 trace_mei_reg_read(dev->dev, "H_D0I3C", H_D0I3C, reg); in mei_me_d0i3c_read()
170 static inline void mei_me_d0i3c_write(struct mei_device *dev, u32 reg) in mei_me_d0i3c_write() argument
172 trace_mei_reg_write(dev->dev, "H_D0I3C", H_D0I3C, reg); in mei_me_d0i3c_write()
173 mei_me_reg_write(to_me_hw(dev), H_D0I3C, reg); in mei_me_d0i3c_write()
184 static int mei_me_trc_status(struct mei_device *dev, u32 *trc) in mei_me_trc_status() argument
186 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_trc_status()
192 trace_mei_reg_read(dev->dev, "ME_TRC", ME_TRC, *trc); in mei_me_trc_status()
205 static int mei_me_fw_status(struct mei_device *dev, in mei_me_fw_status() argument
208 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_fw_status()
218 ret = hw->read_fws(dev, fw_src->status[i], in mei_me_fw_status()
220 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_X", in mei_me_fw_status()
240 static int mei_me_hw_config(struct mei_device *dev) in mei_me_hw_config() argument
242 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_hw_config()
249 hcsr = mei_hcsr_read(dev); in mei_me_hw_config()
253 hw->read_fws(dev, PCI_CFG_HFS_1, ®); in mei_me_hw_config()
254 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg); in mei_me_hw_config()
260 reg = mei_me_d0i3c_read(dev); in mei_me_hw_config()
276 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev) in mei_me_pg_state() argument
278 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_state()
295 static inline void me_intr_disable(struct mei_device *dev, u32 hcsr) in me_intr_disable() argument
298 mei_hcsr_set(dev, hcsr); in me_intr_disable()
307 static inline void me_intr_clear(struct mei_device *dev, u32 hcsr) in me_intr_clear() argument
310 mei_hcsr_write(dev, hcsr); in me_intr_clear()
318 static void mei_me_intr_clear(struct mei_device *dev) in mei_me_intr_clear() argument
320 u32 hcsr = mei_hcsr_read(dev); in mei_me_intr_clear()
322 me_intr_clear(dev, hcsr); in mei_me_intr_clear()
329 static void mei_me_intr_enable(struct mei_device *dev) in mei_me_intr_enable() argument
333 if (mei_me_hw_use_polling(to_me_hw(dev))) in mei_me_intr_enable()
336 hcsr = mei_hcsr_read(dev) | H_CSR_IE_MASK; in mei_me_intr_enable()
337 mei_hcsr_set(dev, hcsr); in mei_me_intr_enable()
345 static void mei_me_intr_disable(struct mei_device *dev) in mei_me_intr_disable() argument
347 u32 hcsr = mei_hcsr_read(dev); in mei_me_intr_disable()
349 me_intr_disable(dev, hcsr); in mei_me_intr_disable()
357 static void mei_me_synchronize_irq(struct mei_device *dev) in mei_me_synchronize_irq() argument
359 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_synchronize_irq()
372 static void mei_me_hw_reset_release(struct mei_device *dev) in mei_me_hw_reset_release() argument
374 u32 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset_release()
378 mei_hcsr_set(dev, hcsr); in mei_me_hw_reset_release()
386 static void mei_me_host_set_ready(struct mei_device *dev) in mei_me_host_set_ready() argument
388 u32 hcsr = mei_hcsr_read(dev); in mei_me_host_set_ready()
390 if (!mei_me_hw_use_polling(to_me_hw(dev))) in mei_me_host_set_ready()
394 mei_hcsr_set(dev, hcsr); in mei_me_host_set_ready()
403 static bool mei_me_host_is_ready(struct mei_device *dev) in mei_me_host_is_ready() argument
405 u32 hcsr = mei_hcsr_read(dev); in mei_me_host_is_ready()
416 static bool mei_me_hw_is_ready(struct mei_device *dev) in mei_me_hw_is_ready() argument
418 u32 mecsr = mei_me_mecsr_read(dev); in mei_me_hw_is_ready()
429 static bool mei_me_hw_is_resetting(struct mei_device *dev) in mei_me_hw_is_resetting() argument
431 u32 mecsr = mei_me_mecsr_read(dev); in mei_me_hw_is_resetting()
441 static void mei_gsc_pxp_check(struct mei_device *dev) in mei_gsc_pxp_check() argument
443 struct mei_me_hw *hw = to_me_hw(dev); in mei_gsc_pxp_check()
446 if (dev->pxp_mode == MEI_DEV_PXP_DEFAULT) in mei_gsc_pxp_check()
449 hw->read_fws(dev, PCI_CFG_HFS_5, &fwsts5); in mei_gsc_pxp_check()
450 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_5", PCI_CFG_HFS_5, fwsts5); in mei_gsc_pxp_check()
452 dev_dbg(dev->dev, "pxp mode is ready 0x%08x\n", fwsts5); in mei_gsc_pxp_check()
453 dev->pxp_mode = MEI_DEV_PXP_READY; in mei_gsc_pxp_check()
455 dev_dbg(dev->dev, "pxp mode is not ready 0x%08x\n", fwsts5); in mei_gsc_pxp_check()
466 static int mei_me_hw_ready_wait(struct mei_device *dev) in mei_me_hw_ready_wait() argument
468 mutex_unlock(&dev->device_lock); in mei_me_hw_ready_wait()
469 wait_event_timeout(dev->wait_hw_ready, in mei_me_hw_ready_wait()
470 dev->recvd_hw_ready, in mei_me_hw_ready_wait()
471 dev->timeouts.hw_ready); in mei_me_hw_ready_wait()
472 mutex_lock(&dev->device_lock); in mei_me_hw_ready_wait()
473 if (!dev->recvd_hw_ready) { in mei_me_hw_ready_wait()
474 dev_err(dev->dev, "wait hw ready failed\n"); in mei_me_hw_ready_wait()
478 mei_gsc_pxp_check(dev); in mei_me_hw_ready_wait()
480 mei_me_hw_reset_release(dev); in mei_me_hw_ready_wait()
481 dev->recvd_hw_ready = false; in mei_me_hw_ready_wait()
491 static int mei_me_hw_start(struct mei_device *dev) in mei_me_hw_start() argument
493 int ret = mei_me_hw_ready_wait(dev); in mei_me_hw_start()
497 dev_dbg(dev->dev, "hw is ready\n"); in mei_me_hw_start()
499 mei_me_host_set_ready(dev); in mei_me_hw_start()
511 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev) in mei_hbuf_filled_slots() argument
516 hcsr = mei_hcsr_read(dev); in mei_hbuf_filled_slots()
531 static bool mei_me_hbuf_is_empty(struct mei_device *dev) in mei_me_hbuf_is_empty() argument
533 return mei_hbuf_filled_slots(dev) == 0; in mei_me_hbuf_is_empty()
543 static int mei_me_hbuf_empty_slots(struct mei_device *dev) in mei_me_hbuf_empty_slots() argument
545 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_hbuf_empty_slots()
548 filled_slots = mei_hbuf_filled_slots(dev); in mei_me_hbuf_empty_slots()
565 static u32 mei_me_hbuf_depth(const struct mei_device *dev) in mei_me_hbuf_depth() argument
567 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_hbuf_depth()
583 static int mei_me_hbuf_write(struct mei_device *dev, in mei_me_hbuf_write() argument
597 dev_err(dev->dev, "wrong parameters null data with data_len = %zu\n", data_len); in mei_me_hbuf_write()
601 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM((struct mei_msg_hdr *)hdr)); in mei_me_hbuf_write()
603 empty_slots = mei_hbuf_empty_slots(dev); in mei_me_hbuf_write()
604 dev_dbg(dev->dev, "empty slots = %d.\n", empty_slots); in mei_me_hbuf_write()
615 mei_me_hcbww_write(dev, reg_buf[i]); in mei_me_hbuf_write()
619 mei_me_hcbww_write(dev, reg_buf[i]); in mei_me_hbuf_write()
626 mei_me_hcbww_write(dev, reg); in mei_me_hbuf_write()
629 mei_hcsr_set_hig(dev); in mei_me_hbuf_write()
630 if (!mei_me_hw_is_ready(dev)) in mei_me_hbuf_write()
643 static int mei_me_count_full_read_slots(struct mei_device *dev) in mei_me_count_full_read_slots() argument
649 me_csr = mei_me_mecsr_read(dev); in mei_me_count_full_read_slots()
659 dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots); in mei_me_count_full_read_slots()
672 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer, in mei_me_read_slots() argument
678 *reg_buf++ = mei_me_mecbrw_read(dev); in mei_me_read_slots()
681 u32 reg = mei_me_mecbrw_read(dev); in mei_me_read_slots()
686 mei_hcsr_set_hig(dev); in mei_me_read_slots()
695 static void mei_me_pg_set(struct mei_device *dev) in mei_me_pg_set() argument
697 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_set()
701 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_set()
705 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_set()
714 static void mei_me_pg_unset(struct mei_device *dev) in mei_me_pg_unset() argument
716 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_unset()
720 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_unset()
726 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_unset()
737 static int mei_me_pg_legacy_enter_sync(struct mei_device *dev) in mei_me_pg_legacy_enter_sync() argument
739 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_legacy_enter_sync()
742 dev->pg_event = MEI_PG_EVENT_WAIT; in mei_me_pg_legacy_enter_sync()
744 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); in mei_me_pg_legacy_enter_sync()
748 mutex_unlock(&dev->device_lock); in mei_me_pg_legacy_enter_sync()
749 wait_event_timeout(dev->wait_pg, in mei_me_pg_legacy_enter_sync()
750 dev->pg_event == MEI_PG_EVENT_RECEIVED, in mei_me_pg_legacy_enter_sync()
751 dev->timeouts.pgi); in mei_me_pg_legacy_enter_sync()
752 mutex_lock(&dev->device_lock); in mei_me_pg_legacy_enter_sync()
754 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) { in mei_me_pg_legacy_enter_sync()
755 mei_me_pg_set(dev); in mei_me_pg_legacy_enter_sync()
761 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_pg_legacy_enter_sync()
774 static int mei_me_pg_legacy_exit_sync(struct mei_device *dev) in mei_me_pg_legacy_exit_sync() argument
776 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_legacy_exit_sync()
779 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) in mei_me_pg_legacy_exit_sync()
782 dev->pg_event = MEI_PG_EVENT_WAIT; in mei_me_pg_legacy_exit_sync()
784 mei_me_pg_unset(dev); in mei_me_pg_legacy_exit_sync()
786 mutex_unlock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
787 wait_event_timeout(dev->wait_pg, in mei_me_pg_legacy_exit_sync()
788 dev->pg_event == MEI_PG_EVENT_RECEIVED, in mei_me_pg_legacy_exit_sync()
789 dev->timeouts.pgi); in mei_me_pg_legacy_exit_sync()
790 mutex_lock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
793 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) { in mei_me_pg_legacy_exit_sync()
798 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; in mei_me_pg_legacy_exit_sync()
799 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD); in mei_me_pg_legacy_exit_sync()
803 mutex_unlock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
804 wait_event_timeout(dev->wait_pg, in mei_me_pg_legacy_exit_sync()
805 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, in mei_me_pg_legacy_exit_sync()
806 dev->timeouts.pgi); in mei_me_pg_legacy_exit_sync()
807 mutex_lock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
809 if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED) in mei_me_pg_legacy_exit_sync()
815 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_pg_legacy_exit_sync()
828 static bool mei_me_pg_in_transition(struct mei_device *dev) in mei_me_pg_in_transition() argument
830 return dev->pg_event >= MEI_PG_EVENT_WAIT && in mei_me_pg_in_transition()
831 dev->pg_event <= MEI_PG_EVENT_INTR_WAIT; in mei_me_pg_in_transition()
841 static bool mei_me_pg_is_enabled(struct mei_device *dev) in mei_me_pg_is_enabled() argument
843 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_is_enabled()
844 u32 reg = mei_me_mecsr_read(dev); in mei_me_pg_is_enabled()
852 if (!dev->hbm_f_pg_supported) in mei_me_pg_is_enabled()
858 dev_dbg(dev->dev, "pg: not supported: d0i3 = %d HGP = %d hbm version %d.%d ?= %d.%d\n", in mei_me_pg_is_enabled()
861 dev->version.major_version, in mei_me_pg_is_enabled()
862 dev->version.minor_version, in mei_me_pg_is_enabled()
877 static u32 mei_me_d0i3_set(struct mei_device *dev, bool intr) in mei_me_d0i3_set() argument
879 u32 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_set()
886 mei_me_d0i3c_write(dev, reg); in mei_me_d0i3_set()
888 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_set()
899 static u32 mei_me_d0i3_unset(struct mei_device *dev) in mei_me_d0i3_unset() argument
901 u32 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_unset()
905 mei_me_d0i3c_write(dev, reg); in mei_me_d0i3_unset()
907 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_unset()
918 static int mei_me_d0i3_enter_sync(struct mei_device *dev) in mei_me_d0i3_enter_sync() argument
920 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_enter_sync()
924 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_enter_sync()
927 dev_dbg(dev->dev, "d0i3 set not needed\n"); in mei_me_d0i3_enter_sync()
933 dev->pg_event = MEI_PG_EVENT_WAIT; in mei_me_d0i3_enter_sync()
935 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); in mei_me_d0i3_enter_sync()
940 mutex_unlock(&dev->device_lock); in mei_me_d0i3_enter_sync()
941 wait_event_timeout(dev->wait_pg, in mei_me_d0i3_enter_sync()
942 dev->pg_event == MEI_PG_EVENT_RECEIVED, in mei_me_d0i3_enter_sync()
943 dev->timeouts.pgi); in mei_me_d0i3_enter_sync()
944 mutex_lock(&dev->device_lock); in mei_me_d0i3_enter_sync()
946 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) { in mei_me_d0i3_enter_sync()
952 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; in mei_me_d0i3_enter_sync()
954 reg = mei_me_d0i3_set(dev, true); in mei_me_d0i3_enter_sync()
956 dev_dbg(dev->dev, "d0i3 enter wait not needed\n"); in mei_me_d0i3_enter_sync()
961 mutex_unlock(&dev->device_lock); in mei_me_d0i3_enter_sync()
962 wait_event_timeout(dev->wait_pg, in mei_me_d0i3_enter_sync()
963 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, in mei_me_d0i3_enter_sync()
964 dev->timeouts.d0i3); in mei_me_d0i3_enter_sync()
965 mutex_lock(&dev->device_lock); in mei_me_d0i3_enter_sync()
967 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) { in mei_me_d0i3_enter_sync()
968 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_enter_sync()
979 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_d0i3_enter_sync()
980 dev_dbg(dev->dev, "d0i3 enter ret = %d\n", ret); in mei_me_d0i3_enter_sync()
994 static int mei_me_d0i3_enter(struct mei_device *dev) in mei_me_d0i3_enter() argument
996 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_enter()
999 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_enter()
1002 dev_dbg(dev->dev, "already d0i3 : set not needed\n"); in mei_me_d0i3_enter()
1006 mei_me_d0i3_set(dev, false); in mei_me_d0i3_enter()
1009 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_d0i3_enter()
1010 dev_dbg(dev->dev, "d0i3 enter\n"); in mei_me_d0i3_enter()
1021 static int mei_me_d0i3_exit_sync(struct mei_device *dev) in mei_me_d0i3_exit_sync() argument
1023 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_exit_sync()
1027 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; in mei_me_d0i3_exit_sync()
1029 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_exit_sync()
1032 dev_dbg(dev->dev, "d0i3 exit not needed\n"); in mei_me_d0i3_exit_sync()
1037 reg = mei_me_d0i3_unset(dev); in mei_me_d0i3_exit_sync()
1039 dev_dbg(dev->dev, "d0i3 exit wait not needed\n"); in mei_me_d0i3_exit_sync()
1044 mutex_unlock(&dev->device_lock); in mei_me_d0i3_exit_sync()
1045 wait_event_timeout(dev->wait_pg, in mei_me_d0i3_exit_sync()
1046 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, in mei_me_d0i3_exit_sync()
1047 dev->timeouts.d0i3); in mei_me_d0i3_exit_sync()
1048 mutex_lock(&dev->device_lock); in mei_me_d0i3_exit_sync()
1050 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) { in mei_me_d0i3_exit_sync()
1051 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_exit_sync()
1062 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_d0i3_exit_sync()
1064 dev_dbg(dev->dev, "d0i3 exit ret = %d\n", ret); in mei_me_d0i3_exit_sync()
1074 static void mei_me_pg_legacy_intr(struct mei_device *dev) in mei_me_pg_legacy_intr() argument
1076 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_legacy_intr()
1078 if (dev->pg_event != MEI_PG_EVENT_INTR_WAIT) in mei_me_pg_legacy_intr()
1081 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED; in mei_me_pg_legacy_intr()
1083 if (waitqueue_active(&dev->wait_pg)) in mei_me_pg_legacy_intr()
1084 wake_up(&dev->wait_pg); in mei_me_pg_legacy_intr()
1093 static void mei_me_d0i3_intr(struct mei_device *dev, u32 intr_source) in mei_me_d0i3_intr() argument
1095 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_intr()
1097 if (dev->pg_event == MEI_PG_EVENT_INTR_WAIT && in mei_me_d0i3_intr()
1099 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED; in mei_me_d0i3_intr()
1102 if (dev->hbm_state != MEI_HBM_IDLE) { in mei_me_d0i3_intr()
1107 dev_dbg(dev->dev, "d0i3 set host ready\n"); in mei_me_d0i3_intr()
1108 mei_me_host_set_ready(dev); in mei_me_d0i3_intr()
1114 wake_up(&dev->wait_pg); in mei_me_d0i3_intr()
1123 dev_dbg(dev->dev, "d0i3 want resume\n"); in mei_me_d0i3_intr()
1124 mei_hbm_pg_resume(dev); in mei_me_d0i3_intr()
1134 static void mei_me_pg_intr(struct mei_device *dev, u32 intr_source) in mei_me_pg_intr() argument
1136 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_intr()
1139 mei_me_d0i3_intr(dev, intr_source); in mei_me_pg_intr()
1141 mei_me_pg_legacy_intr(dev); in mei_me_pg_intr()
1151 int mei_me_pg_enter_sync(struct mei_device *dev) in mei_me_pg_enter_sync() argument
1153 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_enter_sync()
1156 return mei_me_d0i3_enter_sync(dev); in mei_me_pg_enter_sync()
1158 return mei_me_pg_legacy_enter_sync(dev); in mei_me_pg_enter_sync()
1168 int mei_me_pg_exit_sync(struct mei_device *dev) in mei_me_pg_exit_sync() argument
1170 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_exit_sync()
1173 return mei_me_d0i3_exit_sync(dev); in mei_me_pg_exit_sync()
1175 return mei_me_pg_legacy_exit_sync(dev); in mei_me_pg_exit_sync()
1186 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable) in mei_me_hw_reset() argument
1188 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_hw_reset()
1193 mei_me_intr_enable(dev); in mei_me_hw_reset()
1195 ret = mei_me_d0i3_exit_sync(dev); in mei_me_hw_reset()
1203 pm_runtime_set_active(dev->dev); in mei_me_hw_reset()
1205 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset()
1212 dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr); in mei_me_hw_reset()
1214 mei_hcsr_set(dev, hcsr); in mei_me_hw_reset()
1215 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset()
1220 if (!intr_enable || mei_me_hw_use_polling(to_me_hw(dev))) in mei_me_hw_reset()
1223 dev->recvd_hw_ready = false; in mei_me_hw_reset()
1224 mei_hcsr_write(dev, hcsr); in mei_me_hw_reset()
1230 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset()
1233 dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr); in mei_me_hw_reset()
1236 dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr); in mei_me_hw_reset()
1239 mei_me_hw_reset_release(dev); in mei_me_hw_reset()
1241 ret = mei_me_d0i3_enter(dev); in mei_me_hw_reset()
1259 struct mei_device *dev = (struct mei_device *)dev_id; in mei_me_irq_quick_handler() local
1262 hcsr = mei_hcsr_read(dev); in mei_me_irq_quick_handler()
1266 dev_dbg(dev->dev, "interrupt source 0x%08X\n", me_intr_src(hcsr)); in mei_me_irq_quick_handler()
1269 me_intr_disable(dev, hcsr); in mei_me_irq_quick_handler()
1286 struct mei_device *dev = (struct mei_device *) dev_id; in mei_me_irq_thread_handler() local
1292 dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n"); in mei_me_irq_thread_handler()
1294 mutex_lock(&dev->device_lock); in mei_me_irq_thread_handler()
1296 hcsr = mei_hcsr_read(dev); in mei_me_irq_thread_handler()
1297 me_intr_clear(dev, hcsr); in mei_me_irq_thread_handler()
1302 if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) { in mei_me_irq_thread_handler()
1303 dev_warn(dev->dev, "FW not ready: resetting: dev_state = %d pxp = %d\n", in mei_me_irq_thread_handler()
1304 dev->dev_state, dev->pxp_mode); in mei_me_irq_thread_handler()
1305 if (dev->dev_state == MEI_DEV_POWERING_DOWN || in mei_me_irq_thread_handler()
1306 dev->dev_state == MEI_DEV_POWER_DOWN) in mei_me_irq_thread_handler()
1307 mei_cl_all_disconnect(dev); in mei_me_irq_thread_handler()
1308 else if (dev->dev_state != MEI_DEV_DISABLED) in mei_me_irq_thread_handler()
1309 schedule_work(&dev->reset_work); in mei_me_irq_thread_handler()
1313 if (mei_me_hw_is_resetting(dev)) in mei_me_irq_thread_handler()
1314 mei_hcsr_set_hig(dev); in mei_me_irq_thread_handler()
1316 mei_me_pg_intr(dev, me_intr_src(hcsr)); in mei_me_irq_thread_handler()
1319 if (!mei_host_is_ready(dev)) { in mei_me_irq_thread_handler()
1320 if (mei_hw_is_ready(dev)) { in mei_me_irq_thread_handler()
1321 dev_dbg(dev->dev, "we need to start the dev.\n"); in mei_me_irq_thread_handler()
1322 dev->recvd_hw_ready = true; in mei_me_irq_thread_handler()
1323 wake_up(&dev->wait_hw_ready); in mei_me_irq_thread_handler()
1325 dev_dbg(dev->dev, "Spurious Interrupt\n"); in mei_me_irq_thread_handler()
1330 slots = mei_count_full_read_slots(dev); in mei_me_irq_thread_handler()
1332 dev_dbg(dev->dev, "slots to read = %08x\n", slots); in mei_me_irq_thread_handler()
1333 rets = mei_irq_read_handler(dev, &cmpl_list, &slots); in mei_me_irq_thread_handler()
1342 dev_err(dev->dev, "mei_irq_read_handler ret = %d, state = %d.\n", in mei_me_irq_thread_handler()
1343 rets, dev->dev_state); in mei_me_irq_thread_handler()
1344 if (dev->dev_state != MEI_DEV_RESETTING && in mei_me_irq_thread_handler()
1345 dev->dev_state != MEI_DEV_DISABLED && in mei_me_irq_thread_handler()
1346 dev->dev_state != MEI_DEV_POWERING_DOWN && in mei_me_irq_thread_handler()
1347 dev->dev_state != MEI_DEV_POWER_DOWN) in mei_me_irq_thread_handler()
1348 schedule_work(&dev->reset_work); in mei_me_irq_thread_handler()
1353 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); in mei_me_irq_thread_handler()
1360 if (dev->pg_event != MEI_PG_EVENT_WAIT && in mei_me_irq_thread_handler()
1361 dev->pg_event != MEI_PG_EVENT_RECEIVED) { in mei_me_irq_thread_handler()
1362 rets = mei_irq_write_handler(dev, &cmpl_list); in mei_me_irq_thread_handler()
1363 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); in mei_me_irq_thread_handler()
1366 mei_irq_compl_handler(dev, &cmpl_list); in mei_me_irq_thread_handler()
1369 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets); in mei_me_irq_thread_handler()
1370 mei_me_intr_enable(dev); in mei_me_irq_thread_handler()
1371 mutex_unlock(&dev->device_lock); in mei_me_irq_thread_handler()
1397 struct mei_device *dev = _dev; in mei_me_polling_thread() local
1401 dev_dbg(dev->dev, "kernel thread is running\n"); in mei_me_polling_thread()
1403 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_polling_thread()
1413 hcsr = mei_hcsr_read(dev); in mei_me_polling_thread()
1416 irq_ret = mei_me_irq_thread_handler(1, dev); in mei_me_polling_thread()
1418 dev_err(dev->dev, "irq_ret %d\n", irq_ret); in mei_me_polling_thread()
1486 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_2", PCI_CFG_HFS_2, reg); in mei_me_fw_type_nm()
1512 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg); in mei_me_fw_type_sps_4()
1537 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_3", PCI_CFG_HFS_3, reg); in mei_me_fw_type_sps_ign()
1540 dev_dbg(&pdev->dev, "fw type is %d\n", fw_type); in mei_me_fw_type_sps_ign()
1748 struct mei_device *dev; in mei_me_dev_init() local
1752 dev = devm_kzalloc(parent, sizeof(*dev) + sizeof(*hw), GFP_KERNEL); in mei_me_dev_init()
1753 if (!dev) in mei_me_dev_init()
1756 hw = to_me_hw(dev); in mei_me_dev_init()
1759 dev->dr_dscr[i].size = cfg->dma_size[i]; in mei_me_dev_init()
1761 mei_device_init(dev, parent, slow_fw, &mei_me_hw_ops); in mei_me_dev_init()
1764 dev->fw_f_fw_ver_supported = cfg->fw_ver_supported; in mei_me_dev_init()
1766 dev->kind = cfg->kind; in mei_me_dev_init()
1768 return dev; in mei_me_dev_init()