Lines Matching refs:next
78 ({ next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] = \
79 next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] / \
80 next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; })
86 ({ next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] += \
102 next->ptfv_list[dqs] = \
104 (next->ptfv_list[dqs] * \
105 next->ptfv_list[w])) / \
106 (next->ptfv_list[w] + 1); \
109 __stringify(dev), nval, next->ptfv_list[dqs]); \
120 struct tegra210_emc_timing *next = emc->next; in update_clock_tree_delay() local
122 u32 next_timing_rate_mhz = next->rate / 1000; in update_clock_tree_delay()
168 tdel = next->current_dram_clktree[C0D0U0] - in update_clock_tree_delay()
169 __MOVAVG_AC(next, C0D0U0); in update_clock_tree_delay()
174 next->tree_margin) in update_clock_tree_delay()
175 next->current_dram_clktree[C0D0U0] = in update_clock_tree_delay()
176 __MOVAVG_AC(next, C0D0U0); in update_clock_tree_delay()
193 tdel = next->current_dram_clktree[C0D0U1] - in update_clock_tree_delay()
194 __MOVAVG_AC(next, C0D0U1); in update_clock_tree_delay()
201 next->tree_margin) in update_clock_tree_delay()
202 next->current_dram_clktree[C0D0U1] = in update_clock_tree_delay()
203 __MOVAVG_AC(next, C0D0U1); in update_clock_tree_delay()
221 tdel = next->current_dram_clktree[C1D0U0] - in update_clock_tree_delay()
222 __MOVAVG_AC(next, C1D0U0); in update_clock_tree_delay()
229 next->tree_margin) in update_clock_tree_delay()
230 next->current_dram_clktree[C1D0U0] = in update_clock_tree_delay()
231 __MOVAVG_AC(next, C1D0U0); in update_clock_tree_delay()
248 tdel = next->current_dram_clktree[C1D0U1] - in update_clock_tree_delay()
249 __MOVAVG_AC(next, C1D0U1); in update_clock_tree_delay()
256 next->tree_margin) in update_clock_tree_delay()
257 next->current_dram_clktree[C1D0U1] = in update_clock_tree_delay()
258 __MOVAVG_AC(next, C1D0U1); in update_clock_tree_delay()
303 tdel = next->current_dram_clktree[C0D1U0] - in update_clock_tree_delay()
304 __MOVAVG_AC(next, C0D1U0); in update_clock_tree_delay()
311 next->tree_margin) in update_clock_tree_delay()
312 next->current_dram_clktree[C0D1U0] = in update_clock_tree_delay()
313 __MOVAVG_AC(next, C0D1U0); in update_clock_tree_delay()
330 tdel = next->current_dram_clktree[C0D1U1] - in update_clock_tree_delay()
331 __MOVAVG_AC(next, C0D1U1); in update_clock_tree_delay()
338 next->tree_margin) in update_clock_tree_delay()
339 next->current_dram_clktree[C0D1U1] = in update_clock_tree_delay()
340 __MOVAVG_AC(next, C0D1U1); in update_clock_tree_delay()
358 tdel = next->current_dram_clktree[C1D1U0] - in update_clock_tree_delay()
359 __MOVAVG_AC(next, C1D1U0); in update_clock_tree_delay()
366 next->tree_margin) in update_clock_tree_delay()
367 next->current_dram_clktree[C1D1U0] = in update_clock_tree_delay()
368 __MOVAVG_AC(next, C1D1U0); in update_clock_tree_delay()
385 tdel = next->current_dram_clktree[C1D1U1] - in update_clock_tree_delay()
386 __MOVAVG_AC(next, C1D1U1); in update_clock_tree_delay()
393 next->tree_margin) in update_clock_tree_delay()
394 next->current_dram_clktree[C1D1U1] = in update_clock_tree_delay()
395 __MOVAVG_AC(next, C1D1U1); in update_clock_tree_delay()
405 struct tegra210_emc_timing *next) in periodic_compensation_handler() argument
411 u32 i, adel = 0, samples = next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; in periodic_compensation_handler()
418 if (!next->periodic_training) in periodic_compensation_handler()
423 (next->ptfv_list[PTFV_CONFIG_CTRL_INDEX] & in periodic_compensation_handler()
430 __COPY_EMA(next, last, C0D0U0); in periodic_compensation_handler()
431 __COPY_EMA(next, last, C0D0U1); in periodic_compensation_handler()
432 __COPY_EMA(next, last, C1D0U0); in periodic_compensation_handler()
433 __COPY_EMA(next, last, C1D0U1); in periodic_compensation_handler()
434 __COPY_EMA(next, last, C0D1U0); in periodic_compensation_handler()
435 __COPY_EMA(next, last, C0D1U1); in periodic_compensation_handler()
436 __COPY_EMA(next, last, C1D1U0); in periodic_compensation_handler()
437 __COPY_EMA(next, last, C1D1U1); in periodic_compensation_handler()
440 __MOVAVG(next, C0D0U0) = 0; in periodic_compensation_handler()
441 __MOVAVG(next, C0D0U1) = 0; in periodic_compensation_handler()
442 __MOVAVG(next, C1D0U0) = 0; in periodic_compensation_handler()
443 __MOVAVG(next, C1D0U1) = 0; in periodic_compensation_handler()
444 __MOVAVG(next, C0D1U0) = 0; in periodic_compensation_handler()
445 __MOVAVG(next, C0D1U1) = 0; in periodic_compensation_handler()
446 __MOVAVG(next, C1D1U0) = 0; in periodic_compensation_handler()
447 __MOVAVG(next, C1D1U1) = 0; in periodic_compensation_handler()
607 struct tegra210_emc_timing *fake, *last = emc->last, *next = emc->next; in tegra210_emc_r21021_set_clock() local
612 u32 tFC_lpddr4 = 1000 * next->dram_timings[T_FC_LPDDR4]; in tegra210_emc_r21021_set_clock()
636 if ((next->burst_regs[EMC_ZCAL_INTERVAL_INDEX] != 0 && in tegra210_emc_r21021_set_clock()
642 opt_dll_mode = tegra210_emc_get_dll_state(next); in tegra210_emc_r21021_set_clock()
644 if ((next->burst_regs[EMC_FBIO_CFG5_INDEX] & BIT(25)) && in tegra210_emc_r21021_set_clock()
652 dst_clk_period = 1000000000 / next->rate; in tegra210_emc_r21021_set_clock()
665 emc_cfg = next->burst_regs[EMC_CFG_INDEX]; in tegra210_emc_r21021_set_clock()
668 emc_sel_dpd_ctrl = next->emc_sel_dpd_ctrl; in tegra210_emc_r21021_set_clock()
680 emc_dbg(emc, INFO, "DLL clksrc: 0x%08x\n", next->dll_clk_src); in tegra210_emc_r21021_set_clock()
682 next->rate); in tegra210_emc_r21021_set_clock()
708 emc_auto_cal_config = next->emc_auto_cal_config; in tegra210_emc_r21021_set_clock()
724 if (next->periodic_training) { in tegra210_emc_r21021_set_clock()
725 tegra210_emc_reset_dram_clktree_values(next); in tegra210_emc_r21021_set_clock()
743 next); in tegra210_emc_r21021_set_clock()
744 value = (value * 128 * next->rate / 1000) / 1000000; in tegra210_emc_r21021_set_clock()
746 if (next->periodic_training && value > next->tree_margin) in tegra210_emc_r21021_set_clock()
756 emc_writel(emc, next->emc_fdpd_ctrl_cmd_no_ramp & in tegra210_emc_r21021_set_clock()
761 ((next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
765 ((next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
770 (next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
773 (next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
793 ((next->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] & in tegra210_emc_r21021_set_clock()
797 ((next->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] & in tegra210_emc_r21021_set_clock()
800 next->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX]; in tegra210_emc_r21021_set_clock()
827 if (next->burst_regs[EMC_CFG_DIG_DLL_INDEX] & in tegra210_emc_r21021_set_clock()
844 emc_writel(emc, next->emc_auto_cal_config2, EMC_AUTO_CAL_CONFIG2); in tegra210_emc_r21021_set_clock()
845 emc_writel(emc, next->emc_auto_cal_config3, EMC_AUTO_CAL_CONFIG3); in tegra210_emc_r21021_set_clock()
846 emc_writel(emc, next->emc_auto_cal_config4, EMC_AUTO_CAL_CONFIG4); in tegra210_emc_r21021_set_clock()
847 emc_writel(emc, next->emc_auto_cal_config5, EMC_AUTO_CAL_CONFIG5); in tegra210_emc_r21021_set_clock()
848 emc_writel(emc, next->emc_auto_cal_config6, EMC_AUTO_CAL_CONFIG6); in tegra210_emc_r21021_set_clock()
849 emc_writel(emc, next->emc_auto_cal_config7, EMC_AUTO_CAL_CONFIG7); in tegra210_emc_r21021_set_clock()
850 emc_writel(emc, next->emc_auto_cal_config8, EMC_AUTO_CAL_CONFIG8); in tegra210_emc_r21021_set_clock()
866 emc_writel(emc, next->emc_cfg_2, EMC_CFG_2); in tegra210_emc_r21021_set_clock()
877 zq_wait_long = max(next->min_mrs_wait, in tegra210_emc_r21021_set_clock()
930 next->burst_regs[EMC_RP_INDEX]); in tegra210_emc_r21021_set_clock()
985 mr13_flip_fspwr = (next->emc_mrw3 & 0xffffff3f) | 0x80; in tegra210_emc_r21021_set_clock()
986 mr13_flip_fspop = (next->emc_mrw3 & 0xffffff3f) | 0x00; in tegra210_emc_r21021_set_clock()
988 mr13_flip_fspwr = (next->emc_mrw3 & 0xffffff3f) | 0x40; in tegra210_emc_r21021_set_clock()
989 mr13_flip_fspop = (next->emc_mrw3 & 0xffffff3f) | 0xc0; in tegra210_emc_r21021_set_clock()
994 emc_writel(emc, next->emc_mrw, EMC_MRW); in tegra210_emc_r21021_set_clock()
995 emc_writel(emc, next->emc_mrw2, EMC_MRW2); in tegra210_emc_r21021_set_clock()
1005 for (i = 0; i < next->num_burst; i++) { in tegra210_emc_r21021_set_clock()
1012 value = next->burst_regs[i]; in tegra210_emc_r21021_set_clock()
1073 tegra210_emc_adjust_timing(emc, next); in tegra210_emc_r21021_set_clock()
1077 (next->run_clocks & EMC_MRW_MRW_OP_MASK); in tegra210_emc_r21021_set_clock()
1084 for (i = 0; i < next->num_burst_per_ch; i++) { in tegra210_emc_r21021_set_clock()
1109 next->burst_reg_per_ch[i], burst[i].offset); in tegra210_emc_r21021_set_clock()
1111 next->burst_reg_per_ch[i], in tegra210_emc_r21021_set_clock()
1118 for (i = 0; i < next->vref_num; i++) { in tegra210_emc_r21021_set_clock()
1129 next->vref_perch_regs[i], vref[i].offset); in tegra210_emc_r21021_set_clock()
1130 emc_channel_writel(emc, vref[i].bank, next->vref_perch_regs[i], in tegra210_emc_r21021_set_clock()
1137 for (i = 0; i < next->num_trim; i++) { in tegra210_emc_r21021_set_clock()
1154 value = tegra210_emc_compensate(next, offsets[i]); in tegra210_emc_r21021_set_clock()
1162 next->trim_regs[i], offsets[i]); in tegra210_emc_r21021_set_clock()
1163 emc_writel(emc, next->trim_regs[i], offsets[i]); in tegra210_emc_r21021_set_clock()
1170 for (i = 0; i < next->num_trim_per_ch; i++) { in tegra210_emc_r21021_set_clock()
1194 value = tegra210_emc_compensate(next, offset); in tegra210_emc_r21021_set_clock()
1202 next->trim_perch_regs[i], offset); in tegra210_emc_r21021_set_clock()
1204 next->trim_perch_regs[i], offset); in tegra210_emc_r21021_set_clock()
1210 for (i = 0; i < next->num_mc_regs; i++) { in tegra210_emc_r21021_set_clock()
1212 u32 *values = next->burst_mc_regs; in tegra210_emc_r21021_set_clock()
1220 if (next->rate < last->rate) { in tegra210_emc_r21021_set_clock()
1225 for (i = 0; i < next->num_up_down; i++) { in tegra210_emc_r21021_set_clock()
1227 next->la_scale_regs[i], la[i]); in tegra210_emc_r21021_set_clock()
1228 mc_writel(emc->mc, next->la_scale_regs[i], la[i]); in tegra210_emc_r21021_set_clock()
1241 value = next->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX]; in tegra210_emc_r21021_set_clock()
1271 ccfifo_writel(emc, (next->burst_regs[EMC_MRW6_INDEX] & in tegra210_emc_r21021_set_clock()
1275 ccfifo_writel(emc, (next->burst_regs[EMC_MRW14_INDEX] & in tegra210_emc_r21021_set_clock()
1282 (next->burst_regs[EMC_MRW7_INDEX] & in tegra210_emc_r21021_set_clock()
1287 (next->burst_regs[EMC_MRW15_INDEX] & in tegra210_emc_r21021_set_clock()
1415 div_o3(1000 * next->dram_timings[T_PDEX], in tegra210_emc_r21021_set_clock()
1423 next->dram_timings[T_PDEX]); in tegra210_emc_r21021_set_clock()
1428 delay = div_o3(1000 * next->dram_timings[T_PDEX], in tegra210_emc_r21021_set_clock()
1508 ccfifo_writel(emc, next->emc_mrw2, EMC_MRW2, 0); in tegra210_emc_r21021_set_clock()
1509 ccfifo_writel(emc, next->emc_mrw, EMC_MRW, 0); in tegra210_emc_r21021_set_clock()
1511 ccfifo_writel(emc, next->emc_mrw4, EMC_MRW4, 0); in tegra210_emc_r21021_set_clock()
1514 ccfifo_writel(emc, next->emc_emrs & in tegra210_emc_r21021_set_clock()
1516 ccfifo_writel(emc, next->emc_emrs2 & in tegra210_emc_r21021_set_clock()
1518 ccfifo_writel(emc, next->emc_mrs | in tegra210_emc_r21021_set_clock()
1577 next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX], in tegra210_emc_r21021_set_clock()
1606 ccfifo_writel(emc, next->burst_regs[EMC_ZCAL_INTERVAL_INDEX], in tegra210_emc_r21021_set_clock()
1610 ccfifo_writel(emc, next->burst_regs[EMC_CFG_INDEX] & in tegra210_emc_r21021_set_clock()
1627 next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
1632 next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
1664 if (next->rate > last->rate) { in tegra210_emc_r21021_set_clock()
1665 for (i = 0; i < next->num_up_down; i++) in tegra210_emc_r21021_set_clock()
1666 mc_writel(emc->mc, next->la_scale_regs[i], in tegra210_emc_r21021_set_clock()
1680 emc_writel(emc, next->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX], in tegra210_emc_r21021_set_clock()
1682 emc_writel(emc, next->burst_regs[EMC_ZCAL_INTERVAL_INDEX], in tegra210_emc_r21021_set_clock()
1693 emc_writel(emc, next->burst_regs[EMC_MRS_WAIT_CNT_INDEX], in tegra210_emc_r21021_set_clock()
1696 emc_writel(emc, next->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX], in tegra210_emc_r21021_set_clock()
1708 emc_writel(emc, next->burst_regs[EMC_CFG_INDEX], EMC_CFG); in tegra210_emc_r21021_set_clock()
1710 emc_writel(emc, next->emc_fdpd_ctrl_cmd_no_ramp, in tegra210_emc_r21021_set_clock()
1712 emc_writel(emc, next->emc_sel_dpd_ctrl, EMC_SEL_DPD_CTRL); in tegra210_emc_r21021_set_clock()
1722 next->burst_regs[EMC_PMACRO_AUTOCAL_CFG_COMMON_INDEX], in tegra210_emc_r21021_set_clock()
1753 if (next->burst_regs[EMC_CFG_DIG_DLL_INDEX] & EMC_CFG_DIG_DLL_CFG_DLL_EN) { in tegra210_emc_r21021_set_clock()
1765 emc_writel(emc, next->emc_auto_cal_config, EMC_AUTO_CAL_CONFIG); in tegra210_emc_r21021_set_clock()