25 #define G1_REG_DEC_AXI_RD_ID(v)		(((v) << 24) & GENMASK(31, 24))  argument
26 #define G1_REG_DEC_TIMEOUT_E(v)		((v) ? BIT(23) : 0)  argument
27 #define G1_REG_DEC_STRSWAP32_E(v)	((v) ? BIT(22) : 0)  argument
28 #define G1_REG_DEC_STRENDIAN_E(v)	((v) ? BIT(21) : 0)  argument
29 #define G1_REG_DEC_INSWAP32_E(v)	((v) ? BIT(20) : 0)  argument
30 #define G1_REG_DEC_OUTSWAP32_E(v)	((v) ? BIT(19) : 0)  argument
31 #define G1_REG_DEC_DATA_DISC_E(v)	((v) ? BIT(18) : 0)  argument
32 #define G1_REG_DEC_LATENCY(v)		(((v) << 11) & GENMASK(16, 11))  argument
33 #define G1_REG_DEC_CLK_GATE_E(v)	((v) ? BIT(10) : 0)  argument
34 #define G1_REG_DEC_IN_ENDIAN(v)		((v) ? BIT(9) : 0)  argument
35 #define G1_REG_DEC_OUT_ENDIAN(v)	((v) ? BIT(8) : 0)  argument
36 #define G1_REG_DEC_ADV_PRE_DIS(v)	((v) ? BIT(6) : 0)  argument
37 #define G1_REG_DEC_SCMD_DIS(v)		((v) ? BIT(5) : 0)  argument
38 #define G1_REG_DEC_MAX_BURST(v)		(((v) << 0) & GENMASK(4, 0))  argument
40 #define G1_REG_DEC_MODE(v)		(((v) << 28) & GENMASK(31, 28))  argument
41 #define G1_REG_RLC_MODE_E(v)		((v) ? BIT(27) : 0)  argument
42 #define G1_REG_PIC_INTERLACE_E(v)	((v) ? BIT(23) : 0)  argument
43 #define G1_REG_PIC_FIELDMODE_E(v)	((v) ? BIT(22) : 0)  argument
44 #define G1_REG_PIC_B_E(v)		((v) ? BIT(21) : 0)  argument
45 #define G1_REG_PIC_INTER_E(v)		((v) ? BIT(20) : 0)  argument
46 #define G1_REG_PIC_TOPFIELD_E(v)	((v) ? BIT(19) : 0)  argument
47 #define G1_REG_FWD_INTERLACE_E(v)	((v) ? BIT(18) : 0)  argument
48 #define G1_REG_FILTERING_DIS(v)		((v) ? BIT(14) : 0)  argument
49 #define G1_REG_WRITE_MVS_E(v)		((v) ? BIT(12) : 0)  argument
50 #define G1_REG_DEC_AXI_WR_ID(v)		(((v) << 0) & GENMASK(7, 0))  argument
52 #define G1_REG_PIC_MB_WIDTH(v)		(((v) << 23) & GENMASK(31, 23))  argument
53 #define G1_REG_PIC_MB_HEIGHT_P(v)	(((v) << 11) & GENMASK(18, 11))  argument
54 #define G1_REG_ALT_SCAN_E(v)		((v) ? BIT(6) : 0)  argument
55 #define G1_REG_TOPFIELDFIRST_E(v)	((v) ? BIT(5) : 0)  argument
57 #define G1_REG_STRM_START_BIT(v)	(((v) << 26) & GENMASK(31, 26))  argument
58 #define G1_REG_QSCALE_TYPE(v)		((v) ? BIT(24) : 0)  argument
59 #define G1_REG_CON_MV_E(v)		((v) ? BIT(4) : 0)  argument
60 #define G1_REG_INTRA_DC_PREC(v)		(((v) << 2) & GENMASK(3, 2))  argument
61 #define G1_REG_INTRA_VLC_TAB(v)		((v) ? BIT(1) : 0)  argument
62 #define G1_REG_FRAME_PRED_DCT(v)	((v) ? BIT(0) : 0)  argument
64 #define G1_REG_INIT_QP(v)		(((v) << 25) & GENMASK(30, 25))  argument
65 #define G1_REG_STREAM_LEN(v)		(((v) << 0) & GENMASK(23, 0))  argument
67 #define G1_REG_ALT_SCAN_FLAG_E(v)	((v) ? BIT(19) : 0)  argument
68 #define G1_REG_FCODE_FWD_HOR(v)		(((v) << 15) & GENMASK(18, 15))  argument
69 #define G1_REG_FCODE_FWD_VER(v)		(((v) << 11) & GENMASK(14, 11))  argument
70 #define G1_REG_FCODE_BWD_HOR(v)		(((v) << 7) & GENMASK(10, 7))  argument
71 #define G1_REG_FCODE_BWD_VER(v)		(((v) << 3) & GENMASK(6, 3))  argument
72 #define G1_REG_MV_ACCURACY_FWD(v)	((v) ? BIT(2) : 0)  argument
73 #define G1_REG_MV_ACCURACY_BWD(v)	((v) ? BIT(1) : 0)  argument
75 #define G1_REG_STARTMB_X(v)		(((v) << 23) & GENMASK(31, 23))  argument
76 #define G1_REG_STARTMB_Y(v)		(((v) << 15) & GENMASK(22, 15))  argument
78 #define G1_REG_APF_THRESHOLD(v)		(((v) << 0) & GENMASK(13, 0))  argument