23 	u32 cfg;  in flite_hw_reset()  local
25 	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_reset()
26 	cfg |= FLITE_REG_CIGCTRL_SWRST_REQ;  in flite_hw_reset()
27 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_reset()
30 		cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_reset()
31 		if (cfg & FLITE_REG_CIGCTRL_SWRST_RDY)  in flite_hw_reset()
36 	cfg |= FLITE_REG_CIGCTRL_SWRST;  in flite_hw_reset()
37 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_reset()
42 	u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS);  in flite_hw_clear_pending_irq()  local
43 	cfg &= ~FLITE_REG_CISTATUS_IRQ_CAM;  in flite_hw_clear_pending_irq()
44 	writel(cfg, dev->regs + FLITE_REG_CISTATUS);  in flite_hw_clear_pending_irq()
56 	u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS2);  in flite_hw_clear_last_capture_end()  local
57 	cfg &= ~FLITE_REG_CISTATUS2_LASTCAPEND;  in flite_hw_clear_last_capture_end()
58 	writel(cfg, dev->regs + FLITE_REG_CISTATUS2);  in flite_hw_clear_last_capture_end()
63 	u32 cfg, intsrc;  in flite_hw_set_interrupt_mask()  local
77 	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_interrupt_mask()
78 	cfg |= FLITE_REG_CIGCTRL_IRQ_DISABLE_MASK;  in flite_hw_set_interrupt_mask()
79 	cfg &= ~intsrc;  in flite_hw_set_interrupt_mask()
80 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_interrupt_mask()
85 	u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT);  in flite_hw_capture_start()  local
86 	cfg |= FLITE_REG_CIIMGCPT_IMGCPTEN;  in flite_hw_capture_start()
87 	writel(cfg, dev->regs + FLITE_REG_CIIMGCPT);  in flite_hw_capture_start()
92 	u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT);  in flite_hw_capture_stop()  local
93 	cfg &= ~FLITE_REG_CIIMGCPT_IMGCPTEN;  in flite_hw_capture_stop()
94 	writel(cfg, dev->regs + FLITE_REG_CIIMGCPT);  in flite_hw_capture_stop()
103 	u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_test_pattern()  local
105 		cfg |= FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR;  in flite_hw_set_test_pattern()
107 		cfg &= ~FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR;  in flite_hw_set_test_pattern()
108 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_test_pattern()
131 	u32 cfg;  in flite_hw_set_source_format()  local
144 	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_source_format()
145 	cfg &= ~FLITE_REG_CIGCTRL_FMT_MASK;  in flite_hw_set_source_format()
146 	cfg |= src_pixfmt_map[i][2];  in flite_hw_set_source_format()
147 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_source_format()
149 	cfg = readl(dev->regs + FLITE_REG_CISRCSIZE);  in flite_hw_set_source_format()
150 	cfg &= ~(FLITE_REG_CISRCSIZE_ORDER422_MASK |  in flite_hw_set_source_format()
152 	cfg |= (f->f_width << 16) | f->f_height;  in flite_hw_set_source_format()
153 	cfg |= src_pixfmt_map[i][1];  in flite_hw_set_source_format()
154 	writel(cfg, dev->regs + FLITE_REG_CISRCSIZE);  in flite_hw_set_source_format()
161 	u32 cfg;  in flite_hw_set_window_offset()  local
163 	cfg = readl(dev->regs + FLITE_REG_CIWDOFST);  in flite_hw_set_window_offset()
164 	cfg &= ~FLITE_REG_CIWDOFST_OFST_MASK;  in flite_hw_set_window_offset()
165 	cfg |= (f->rect.left << 16) | f->rect.top;  in flite_hw_set_window_offset()
166 	cfg |= FLITE_REG_CIWDOFST_WINOFSEN;  in flite_hw_set_window_offset()
167 	writel(cfg, dev->regs + FLITE_REG_CIWDOFST);  in flite_hw_set_window_offset()
172 	cfg = (hoff2 << 16) | voff2;  in flite_hw_set_window_offset()
173 	writel(cfg, dev->regs + FLITE_REG_CIWDOFST2);  in flite_hw_set_window_offset()
179 	u32 cfg = readl(dev->regs + FLITE_REG_CIGENERAL);  in flite_hw_set_camera_port()  local
181 		cfg &= ~FLITE_REG_CIGENERAL_CAM_B;  in flite_hw_set_camera_port()
183 		cfg |= FLITE_REG_CIGENERAL_CAM_B;  in flite_hw_set_camera_port()
184 	writel(cfg, dev->regs + FLITE_REG_CIGENERAL);  in flite_hw_set_camera_port()
191 	u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_camera_bus()  local
195 		cfg &= ~(FLITE_REG_CIGCTRL_SELCAM_MIPI |  in flite_hw_set_camera_bus()
201 			cfg |= FLITE_REG_CIGCTRL_INVPOLPCLK;  in flite_hw_set_camera_bus()
204 			cfg |= FLITE_REG_CIGCTRL_INVPOLVSYNC;  in flite_hw_set_camera_bus()
207 			cfg |= FLITE_REG_CIGCTRL_INVPOLHREF;  in flite_hw_set_camera_bus()
209 		cfg |= FLITE_REG_CIGCTRL_SELCAM_MIPI;  in flite_hw_set_camera_bus()
212 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_camera_bus()
219 	u32 cfg = readl(dev->regs + FLITE_REG_CIODMAFMT);  in flite_hw_set_pack12()  local
221 	cfg &= ~FLITE_REG_CIODMAFMT_PACK12;  in flite_hw_set_pack12()
224 		cfg |= FLITE_REG_CIODMAFMT_PACK12;  in flite_hw_set_pack12()
226 	writel(cfg, dev->regs + FLITE_REG_CIODMAFMT);  in flite_hw_set_pack12()
237 	u32 cfg = readl(dev->regs + FLITE_REG_CIODMAFMT);  in flite_hw_set_out_order()  local
243 	cfg &= ~FLITE_REG_CIODMAFMT_YCBCR_ORDER_MASK;  in flite_hw_set_out_order()
244 	writel(cfg | pixcode[i][1], dev->regs + FLITE_REG_CIODMAFMT);  in flite_hw_set_out_order()
249 	u32 cfg;  in flite_hw_set_dma_window()  local
252 	cfg = readl(dev->regs + FLITE_REG_CIOCAN);  in flite_hw_set_dma_window()
253 	cfg &= ~FLITE_REG_CIOCAN_MASK;  in flite_hw_set_dma_window()
254 	cfg |= (f->f_height << 16) | f->f_width;  in flite_hw_set_dma_window()
255 	writel(cfg, dev->regs + FLITE_REG_CIOCAN);  in flite_hw_set_dma_window()
258 	cfg = readl(dev->regs + FLITE_REG_CIOOFF);  in flite_hw_set_dma_window()
259 	cfg &= ~FLITE_REG_CIOOFF_MASK;  in flite_hw_set_dma_window()
260 	cfg |= (f->rect.top << 16) | f->rect.left;  in flite_hw_set_dma_window()
261 	writel(cfg, dev->regs + FLITE_REG_CIOOFF);  in flite_hw_set_dma_window()
267 	u32 cfg;  in flite_hw_set_dma_buffer()  local
279 	cfg = readl(dev->regs + FLITE_REG_CIFCNTSEQ);  in flite_hw_set_dma_buffer()
280 	cfg |= BIT(index);  in flite_hw_set_dma_buffer()
281 	writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ);  in flite_hw_set_dma_buffer()
286 	u32 cfg;  in flite_hw_mask_dma_buffer()  local
291 	cfg = readl(dev->regs + FLITE_REG_CIFCNTSEQ);  in flite_hw_mask_dma_buffer()
292 	cfg &= ~BIT(index);  in flite_hw_mask_dma_buffer()
293 	writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ);  in flite_hw_mask_dma_buffer()
300 	u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_output_dma()  local
303 		cfg |= FLITE_REG_CIGCTRL_ODMA_DISABLE;  in flite_hw_set_output_dma()
304 		writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_output_dma()
308 	cfg &= ~FLITE_REG_CIGCTRL_ODMA_DISABLE;  in flite_hw_set_output_dma()
309 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_output_dma()
342 		u32 cfg = readl(dev->regs + registers[i].offset);  in flite_hw_dump_regs()  local
344 			  registers[i].name, cfg);  in flite_hw_dump_regs()