Lines Matching refs:vin
159 static void rvin_write(struct rvin_dev *vin, u32 value, u32 offset) in rvin_write() argument
161 iowrite32(value, vin->base + offset); in rvin_write()
164 static u32 rvin_read(struct rvin_dev *vin, u32 offset) in rvin_read() argument
166 return ioread32(vin->base + offset); in rvin_read()
173 static bool rvin_scaler_needed(const struct rvin_dev *vin) in rvin_scaler_needed() argument
175 return !(vin->crop.width == vin->format.width && in rvin_scaler_needed()
176 vin->compose.width == vin->format.width && in rvin_scaler_needed()
177 vin->crop.height == vin->format.height && in rvin_scaler_needed()
178 vin->compose.height == vin->format.height); in rvin_scaler_needed()
499 static void rvin_set_coeff(struct rvin_dev *vin, unsigned short xs) in rvin_set_coeff() argument
520 rvin_write(vin, p_set->coeff_set[0], VNC1A_REG); in rvin_set_coeff()
521 rvin_write(vin, p_set->coeff_set[1], VNC1B_REG); in rvin_set_coeff()
522 rvin_write(vin, p_set->coeff_set[2], VNC1C_REG); in rvin_set_coeff()
524 rvin_write(vin, p_set->coeff_set[3], VNC2A_REG); in rvin_set_coeff()
525 rvin_write(vin, p_set->coeff_set[4], VNC2B_REG); in rvin_set_coeff()
526 rvin_write(vin, p_set->coeff_set[5], VNC2C_REG); in rvin_set_coeff()
528 rvin_write(vin, p_set->coeff_set[6], VNC3A_REG); in rvin_set_coeff()
529 rvin_write(vin, p_set->coeff_set[7], VNC3B_REG); in rvin_set_coeff()
530 rvin_write(vin, p_set->coeff_set[8], VNC3C_REG); in rvin_set_coeff()
532 rvin_write(vin, p_set->coeff_set[9], VNC4A_REG); in rvin_set_coeff()
533 rvin_write(vin, p_set->coeff_set[10], VNC4B_REG); in rvin_set_coeff()
534 rvin_write(vin, p_set->coeff_set[11], VNC4C_REG); in rvin_set_coeff()
536 rvin_write(vin, p_set->coeff_set[12], VNC5A_REG); in rvin_set_coeff()
537 rvin_write(vin, p_set->coeff_set[13], VNC5B_REG); in rvin_set_coeff()
538 rvin_write(vin, p_set->coeff_set[14], VNC5C_REG); in rvin_set_coeff()
540 rvin_write(vin, p_set->coeff_set[15], VNC6A_REG); in rvin_set_coeff()
541 rvin_write(vin, p_set->coeff_set[16], VNC6B_REG); in rvin_set_coeff()
542 rvin_write(vin, p_set->coeff_set[17], VNC6C_REG); in rvin_set_coeff()
544 rvin_write(vin, p_set->coeff_set[18], VNC7A_REG); in rvin_set_coeff()
545 rvin_write(vin, p_set->coeff_set[19], VNC7B_REG); in rvin_set_coeff()
546 rvin_write(vin, p_set->coeff_set[20], VNC7C_REG); in rvin_set_coeff()
548 rvin_write(vin, p_set->coeff_set[21], VNC8A_REG); in rvin_set_coeff()
549 rvin_write(vin, p_set->coeff_set[22], VNC8B_REG); in rvin_set_coeff()
550 rvin_write(vin, p_set->coeff_set[23], VNC8C_REG); in rvin_set_coeff()
553 void rvin_scaler_gen2(struct rvin_dev *vin) in rvin_scaler_gen2() argument
559 crop_height = vin->crop.height; in rvin_scaler_gen2()
560 if (V4L2_FIELD_HAS_BOTH(vin->format.field)) in rvin_scaler_gen2()
564 if (crop_height != vin->compose.height) in rvin_scaler_gen2()
565 ys = (4096 * crop_height) / vin->compose.height; in rvin_scaler_gen2()
566 rvin_write(vin, ys, VNYS_REG); in rvin_scaler_gen2()
569 if (vin->crop.width != vin->compose.width) in rvin_scaler_gen2()
570 xs = (4096 * vin->crop.width) / vin->compose.width; in rvin_scaler_gen2()
576 rvin_write(vin, xs, VNXS_REG); in rvin_scaler_gen2()
582 rvin_set_coeff(vin, xs); in rvin_scaler_gen2()
585 rvin_write(vin, 0, VNSPPOC_REG); in rvin_scaler_gen2()
586 rvin_write(vin, 0, VNSLPOC_REG); in rvin_scaler_gen2()
587 rvin_write(vin, vin->format.width - 1, VNEPPOC_REG); in rvin_scaler_gen2()
589 if (V4L2_FIELD_HAS_BOTH(vin->format.field)) in rvin_scaler_gen2()
590 rvin_write(vin, vin->format.height / 2 - 1, VNELPOC_REG); in rvin_scaler_gen2()
592 rvin_write(vin, vin->format.height - 1, VNELPOC_REG); in rvin_scaler_gen2()
594 vin_dbg(vin, in rvin_scaler_gen2()
596 vin->crop.width, vin->crop.height, vin->crop.left, in rvin_scaler_gen2()
597 vin->crop.top, ys, xs, vin->format.width, vin->format.height, in rvin_scaler_gen2()
617 void rvin_scaler_gen3(struct rvin_dev *vin) in rvin_scaler_gen3() argument
623 vnmc = rvin_read(vin, VNMC_REG); in rvin_scaler_gen3()
626 if (!rvin_scaler_needed(vin)) { in rvin_scaler_gen3()
627 rvin_write(vin, vnmc & ~VNMC_SCLE, VNMC_REG); in rvin_scaler_gen3()
631 ratio_h = rvin_uds_scale_ratio(vin->crop.width, vin->compose.width); in rvin_scaler_gen3()
634 ratio_v = rvin_uds_scale_ratio(vin->crop.height, vin->compose.height); in rvin_scaler_gen3()
637 clip_size = vin->compose.width << 16; in rvin_scaler_gen3()
639 switch (vin->format.field) { in rvin_scaler_gen3()
645 clip_size |= vin->compose.height / 2; in rvin_scaler_gen3()
648 clip_size |= vin->compose.height; in rvin_scaler_gen3()
652 rvin_write(vin, vnmc | VNMC_SCLE, VNMC_REG); in rvin_scaler_gen3()
653 rvin_write(vin, VNUDS_CTRL_AMD, VNUDS_CTRL_REG); in rvin_scaler_gen3()
654 rvin_write(vin, (ratio_h << 16) | ratio_v, VNUDS_SCALE_REG); in rvin_scaler_gen3()
655 rvin_write(vin, (bwidth_h << 16) | bwidth_v, VNUDS_PASS_BWIDTH_REG); in rvin_scaler_gen3()
656 rvin_write(vin, clip_size, VNUDS_CLIP_SIZE_REG); in rvin_scaler_gen3()
658 vin_dbg(vin, "Pre-Clip: %ux%u@%u:%u Post-Clip: %ux%u@%u:%u\n", in rvin_scaler_gen3()
659 vin->crop.width, vin->crop.height, vin->crop.left, in rvin_scaler_gen3()
660 vin->crop.top, vin->compose.width, vin->compose.height, in rvin_scaler_gen3()
661 vin->compose.left, vin->compose.top); in rvin_scaler_gen3()
664 void rvin_crop_scale_comp(struct rvin_dev *vin) in rvin_crop_scale_comp() argument
670 rvin_write(vin, vin->crop.left, VNSPPRC_REG); in rvin_crop_scale_comp()
671 rvin_write(vin, vin->crop.left + vin->crop.width - 1, VNEPPRC_REG); in rvin_crop_scale_comp()
672 rvin_write(vin, vin->crop.top, VNSLPRC_REG); in rvin_crop_scale_comp()
673 rvin_write(vin, vin->crop.top + vin->crop.height - 1, VNELPRC_REG); in rvin_crop_scale_comp()
675 if (vin->scaler) in rvin_crop_scale_comp()
676 vin->scaler(vin); in rvin_crop_scale_comp()
678 fmt = rvin_format_from_pixel(vin, vin->format.pixelformat); in rvin_crop_scale_comp()
679 stride = vin->format.bytesperline / fmt->bpp; in rvin_crop_scale_comp()
684 switch (vin->format.pixelformat) { in rvin_crop_scale_comp()
696 rvin_write(vin, stride, VNIS_REG); in rvin_crop_scale_comp()
703 static int rvin_setup(struct rvin_dev *vin) in rvin_setup() argument
708 switch (vin->format.field) { in rvin_setup()
719 if (!vin->info->use_mc && vin->std & V4L2_STD_525_60) in rvin_setup()
743 switch (vin->mbus_code) { in rvin_setup()
755 if (!vin->is_csi && in rvin_setup()
756 vin->parallel.mbus_type == V4L2_MBUS_BT656) in rvin_setup()
768 if (!vin->is_csi && in rvin_setup()
769 vin->parallel.mbus_type == V4L2_MBUS_BT656) in rvin_setup()
788 if (vin->info->model == RCAR_GEN3) { in rvin_setup()
794 if (vin->is_csi) { in rvin_setup()
795 vin_err(vin, "Invalid setting in MIPI CSI2\n"); in rvin_setup()
800 if (!vin->is_csi) { in rvin_setup()
801 vin_err(vin, "Invalid setting in Digital Pins\n"); in rvin_setup()
811 if (vin->info->model == RCAR_GEN3) in rvin_setup()
816 if (!vin->is_csi) { in rvin_setup()
818 if (!(vin->parallel.bus.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) in rvin_setup()
822 if (!(vin->parallel.bus.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) in rvin_setup()
826 if (vin->parallel.bus.flags & V4L2_MBUS_DATA_ENABLE_LOW) in rvin_setup()
829 switch (vin->mbus_code) { in rvin_setup()
831 if (vin->parallel.bus.bus_width == 8 && in rvin_setup()
832 vin->parallel.bus.data_shift == 8) in rvin_setup()
843 switch (vin->format.pixelformat) { in rvin_setup()
846 rvin_write(vin, in rvin_setup()
847 ALIGN(vin->format.bytesperline * vin->format.height, in rvin_setup()
849 dmr = vin->format.pixelformat == V4L2_PIX_FMT_NV12 ? in rvin_setup()
872 dmr = (vin->alpha ? VNDMR_ABIT : 0) | VNDMR_DTMD_ARGB; in rvin_setup()
875 dmr = VNDMR_A8BIT(vin->alpha) | VNDMR_EXRGB | VNDMR_DTMD_ARGB; in rvin_setup()
892 vin_err(vin, "Invalid pixelformat (0x%x)\n", in rvin_setup()
893 vin->format.pixelformat); in rvin_setup()
900 if (!vin->info->use_isp) { in rvin_setup()
905 if (vin->info->model == RCAR_GEN3) { in rvin_setup()
907 if (vin->is_csi) in rvin_setup()
918 rvin_write(vin, interrupts, VNINTS_REG); in rvin_setup()
920 rvin_write(vin, interrupts, VNIE_REG); in rvin_setup()
922 rvin_write(vin, dmr, VNDMR_REG); in rvin_setup()
923 rvin_write(vin, dmr2, VNDMR2_REG); in rvin_setup()
926 rvin_write(vin, vnmc | VNMC_ME, VNMC_REG); in rvin_setup()
931 static void rvin_disable_interrupts(struct rvin_dev *vin) in rvin_disable_interrupts() argument
933 rvin_write(vin, 0, VNIE_REG); in rvin_disable_interrupts()
936 static u32 rvin_get_interrupt_status(struct rvin_dev *vin) in rvin_get_interrupt_status() argument
938 return rvin_read(vin, VNINTS_REG); in rvin_get_interrupt_status()
941 static void rvin_ack_interrupt(struct rvin_dev *vin) in rvin_ack_interrupt() argument
943 rvin_write(vin, rvin_read(vin, VNINTS_REG), VNINTS_REG); in rvin_ack_interrupt()
946 static bool rvin_capture_active(struct rvin_dev *vin) in rvin_capture_active() argument
948 return rvin_read(vin, VNMS_REG) & VNMS_CA; in rvin_capture_active()
951 static enum v4l2_field rvin_get_active_field(struct rvin_dev *vin, u32 vnms) in rvin_get_active_field() argument
953 if (vin->format.field == V4L2_FIELD_ALTERNATE) { in rvin_get_active_field()
960 return vin->format.field; in rvin_get_active_field()
963 static void rvin_set_slot_addr(struct rvin_dev *vin, int slot, dma_addr_t addr) in rvin_set_slot_addr() argument
969 fmt = rvin_format_from_pixel(vin, vin->format.pixelformat); in rvin_set_slot_addr()
975 offsetx = vin->compose.left * fmt->bpp; in rvin_set_slot_addr()
976 offsety = vin->compose.top * vin->format.bytesperline; in rvin_set_slot_addr()
986 rvin_write(vin, offset, VNMB_REG(slot)); in rvin_set_slot_addr()
995 static void rvin_fill_hw_slot(struct rvin_dev *vin, int slot) in rvin_fill_hw_slot() argument
1003 if (WARN_ON(vin->buf_hw[slot].buffer)) in rvin_fill_hw_slot()
1008 if (vin->buf_hw[prev].type == HALF_TOP) { in rvin_fill_hw_slot()
1009 vbuf = vin->buf_hw[prev].buffer; in rvin_fill_hw_slot()
1010 vin->buf_hw[slot].buffer = vbuf; in rvin_fill_hw_slot()
1011 vin->buf_hw[slot].type = HALF_BOTTOM; in rvin_fill_hw_slot()
1012 switch (vin->format.pixelformat) { in rvin_fill_hw_slot()
1015 phys_addr = vin->buf_hw[prev].phys + in rvin_fill_hw_slot()
1016 vin->format.sizeimage / 4; in rvin_fill_hw_slot()
1019 phys_addr = vin->buf_hw[prev].phys + in rvin_fill_hw_slot()
1020 vin->format.sizeimage / 2; in rvin_fill_hw_slot()
1023 } else if ((vin->state != STOPPED && vin->state != RUNNING) || in rvin_fill_hw_slot()
1024 list_empty(&vin->buf_list)) { in rvin_fill_hw_slot()
1025 vin->buf_hw[slot].buffer = NULL; in rvin_fill_hw_slot()
1026 vin->buf_hw[slot].type = FULL; in rvin_fill_hw_slot()
1027 phys_addr = vin->scratch_phys; in rvin_fill_hw_slot()
1030 buf = list_entry(vin->buf_list.next, struct rvin_buffer, list); in rvin_fill_hw_slot()
1033 vin->buf_hw[slot].buffer = vbuf; in rvin_fill_hw_slot()
1035 vin->buf_hw[slot].type = in rvin_fill_hw_slot()
1036 V4L2_FIELD_IS_SEQUENTIAL(vin->format.field) ? in rvin_fill_hw_slot()
1043 vin_dbg(vin, "Filling HW slot: %d type: %d buffer: %p\n", in rvin_fill_hw_slot()
1044 slot, vin->buf_hw[slot].type, vin->buf_hw[slot].buffer); in rvin_fill_hw_slot()
1046 vin->buf_hw[slot].phys = phys_addr; in rvin_fill_hw_slot()
1047 rvin_set_slot_addr(vin, slot, phys_addr); in rvin_fill_hw_slot()
1050 static int rvin_capture_start(struct rvin_dev *vin) in rvin_capture_start() argument
1055 vin->buf_hw[slot].buffer = NULL; in rvin_capture_start()
1056 vin->buf_hw[slot].type = FULL; in rvin_capture_start()
1060 rvin_fill_hw_slot(vin, slot); in rvin_capture_start()
1062 ret = rvin_setup(vin); in rvin_capture_start()
1066 rvin_crop_scale_comp(vin); in rvin_capture_start()
1068 vin_dbg(vin, "Starting to capture\n"); in rvin_capture_start()
1071 rvin_write(vin, VNFC_C_FRAME, VNFC_REG); in rvin_capture_start()
1073 vin->state = STARTING; in rvin_capture_start()
1078 static void rvin_capture_stop(struct rvin_dev *vin) in rvin_capture_stop() argument
1081 rvin_write(vin, 0, VNFC_REG); in rvin_capture_stop()
1084 rvin_write(vin, rvin_read(vin, VNMC_REG) & ~VNMC_ME, VNMC_REG); in rvin_capture_stop()
1096 struct rvin_dev *vin = data; in rvin_irq() local
1102 spin_lock_irqsave(&vin->qlock, flags); in rvin_irq()
1104 int_status = rvin_get_interrupt_status(vin); in rvin_irq()
1108 rvin_ack_interrupt(vin); in rvin_irq()
1116 if (vin->state == STOPPED) { in rvin_irq()
1117 vin_dbg(vin, "IRQ while state stopped\n"); in rvin_irq()
1122 vnms = rvin_read(vin, VNMS_REG); in rvin_irq()
1129 if (vin->state == STARTING) { in rvin_irq()
1131 vin_dbg(vin, "Starting sync slot: %d\n", slot); in rvin_irq()
1135 vin_dbg(vin, "Capture start synced!\n"); in rvin_irq()
1136 vin->state = RUNNING; in rvin_irq()
1140 if (vin->buf_hw[slot].buffer) { in rvin_irq()
1145 if (vin->buf_hw[slot].type == HALF_TOP) { in rvin_irq()
1146 vin->buf_hw[slot].buffer = NULL; in rvin_irq()
1147 rvin_fill_hw_slot(vin, slot); in rvin_irq()
1151 vin->buf_hw[slot].buffer->field = in rvin_irq()
1152 rvin_get_active_field(vin, vnms); in rvin_irq()
1153 vin->buf_hw[slot].buffer->sequence = vin->sequence; in rvin_irq()
1154 vin->buf_hw[slot].buffer->vb2_buf.timestamp = ktime_get_ns(); in rvin_irq()
1155 vb2_buffer_done(&vin->buf_hw[slot].buffer->vb2_buf, in rvin_irq()
1157 vin->buf_hw[slot].buffer = NULL; in rvin_irq()
1160 vin_dbg(vin, "Dropping frame %u\n", vin->sequence); in rvin_irq()
1163 vin->sequence++; in rvin_irq()
1166 rvin_fill_hw_slot(vin, slot); in rvin_irq()
1168 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_irq()
1173 static void return_unused_buffers(struct rvin_dev *vin, in return_unused_buffers() argument
1179 spin_lock_irqsave(&vin->qlock, flags); in return_unused_buffers()
1181 list_for_each_entry_safe(buf, node, &vin->buf_list, list) { in return_unused_buffers()
1186 spin_unlock_irqrestore(&vin->qlock, flags); in return_unused_buffers()
1194 struct rvin_dev *vin = vb2_get_drv_priv(vq); in rvin_queue_setup() local
1198 return sizes[0] < vin->format.sizeimage ? -EINVAL : 0; in rvin_queue_setup()
1201 sizes[0] = vin->format.sizeimage; in rvin_queue_setup()
1208 struct rvin_dev *vin = vb2_get_drv_priv(vb->vb2_queue); in rvin_buffer_prepare() local
1209 unsigned long size = vin->format.sizeimage; in rvin_buffer_prepare()
1212 vin_err(vin, "buffer too small (%lu < %lu)\n", in rvin_buffer_prepare()
1225 struct rvin_dev *vin = vb2_get_drv_priv(vb->vb2_queue); in rvin_buffer_queue() local
1228 spin_lock_irqsave(&vin->qlock, flags); in rvin_buffer_queue()
1230 list_add_tail(to_buf_list(vbuf), &vin->buf_list); in rvin_buffer_queue()
1232 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_buffer_queue()
1235 static int rvin_mc_validate_format(struct rvin_dev *vin, struct v4l2_subdev *sd, in rvin_mc_validate_format() argument
1254 if (vin->format.pixelformat != V4L2_PIX_FMT_SBGGR8) in rvin_mc_validate_format()
1258 if (vin->format.pixelformat != V4L2_PIX_FMT_SGBRG8) in rvin_mc_validate_format()
1262 if (vin->format.pixelformat != V4L2_PIX_FMT_SGRBG8) in rvin_mc_validate_format()
1266 if (vin->format.pixelformat != V4L2_PIX_FMT_SRGGB8) in rvin_mc_validate_format()
1270 if (vin->format.pixelformat != V4L2_PIX_FMT_GREY) in rvin_mc_validate_format()
1276 vin->mbus_code = fmt.format.code; in rvin_mc_validate_format()
1290 switch (vin->format.field) { in rvin_mc_validate_format()
1312 if (rvin_scaler_needed(vin)) { in rvin_mc_validate_format()
1314 if (vin->info->model == RCAR_GEN3 && in rvin_mc_validate_format()
1315 vin->format.pixelformat == V4L2_PIX_FMT_NV12) in rvin_mc_validate_format()
1318 if (!vin->scaler) in rvin_mc_validate_format()
1321 if (vin->format.pixelformat == V4L2_PIX_FMT_NV12) { in rvin_mc_validate_format()
1322 if (ALIGN(fmt.format.width, 32) != vin->format.width || in rvin_mc_validate_format()
1323 ALIGN(fmt.format.height, 32) != vin->format.height) in rvin_mc_validate_format()
1326 if (fmt.format.width != vin->format.width || in rvin_mc_validate_format()
1327 fmt.format.height != vin->format.height) in rvin_mc_validate_format()
1332 if (fmt.format.code != vin->mbus_code) in rvin_mc_validate_format()
1338 static int rvin_set_stream(struct rvin_dev *vin, int on) in rvin_set_stream() argument
1345 if (!vin->info->use_mc) { in rvin_set_stream()
1346 ret = v4l2_subdev_call(vin->parallel.subdev, video, s_stream, in rvin_set_stream()
1352 pad = media_pad_remote_pad_first(&vin->pad); in rvin_set_stream()
1359 video_device_pipeline_stop(&vin->vdev); in rvin_set_stream()
1363 ret = rvin_mc_validate_format(vin, sd, pad); in rvin_set_stream()
1367 ret = video_device_pipeline_alloc_start(&vin->vdev); in rvin_set_stream()
1375 video_device_pipeline_stop(&vin->vdev); in rvin_set_stream()
1380 int rvin_start_streaming(struct rvin_dev *vin) in rvin_start_streaming() argument
1385 ret = rvin_set_stream(vin, 1); in rvin_start_streaming()
1389 spin_lock_irqsave(&vin->qlock, flags); in rvin_start_streaming()
1391 vin->sequence = 0; in rvin_start_streaming()
1393 ret = rvin_capture_start(vin); in rvin_start_streaming()
1395 rvin_set_stream(vin, 0); in rvin_start_streaming()
1397 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_start_streaming()
1404 struct rvin_dev *vin = vb2_get_drv_priv(vq); in rvin_start_streaming_vq() local
1408 vin->scratch = dma_alloc_coherent(vin->dev, vin->format.sizeimage, in rvin_start_streaming_vq()
1409 &vin->scratch_phys, GFP_KERNEL); in rvin_start_streaming_vq()
1410 if (!vin->scratch) in rvin_start_streaming_vq()
1413 ret = rvin_start_streaming(vin); in rvin_start_streaming_vq()
1419 dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch, in rvin_start_streaming_vq()
1420 vin->scratch_phys); in rvin_start_streaming_vq()
1422 return_unused_buffers(vin, VB2_BUF_STATE_QUEUED); in rvin_start_streaming_vq()
1427 void rvin_stop_streaming(struct rvin_dev *vin) in rvin_stop_streaming() argument
1433 spin_lock_irqsave(&vin->qlock, flags); in rvin_stop_streaming()
1435 if (vin->state == STOPPED) { in rvin_stop_streaming()
1436 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_stop_streaming()
1440 vin->state = STOPPING; in rvin_stop_streaming()
1447 if (vin->buf_hw[i].buffer) in rvin_stop_streaming()
1453 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_stop_streaming()
1455 spin_lock_irqsave(&vin->qlock, flags); in rvin_stop_streaming()
1462 rvin_capture_stop(vin); in rvin_stop_streaming()
1465 if (!rvin_capture_active(vin)) { in rvin_stop_streaming()
1466 vin->state = STOPPED; in rvin_stop_streaming()
1470 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_stop_streaming()
1472 spin_lock_irqsave(&vin->qlock, flags); in rvin_stop_streaming()
1475 if (!buffersFreed || vin->state != STOPPED) { in rvin_stop_streaming()
1481 vin_err(vin, "Failed stop HW, something is seriously broken\n"); in rvin_stop_streaming()
1482 vin->state = STOPPED; in rvin_stop_streaming()
1485 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_stop_streaming()
1489 return_unused_buffers(vin, VB2_BUF_STATE_ERROR); in rvin_stop_streaming()
1491 if (vin->buf_hw[i].buffer) in rvin_stop_streaming()
1492 vb2_buffer_done(&vin->buf_hw[i].buffer->vb2_buf, in rvin_stop_streaming()
1497 rvin_set_stream(vin, 0); in rvin_stop_streaming()
1500 rvin_disable_interrupts(vin); in rvin_stop_streaming()
1505 struct rvin_dev *vin = vb2_get_drv_priv(vq); in rvin_stop_streaming_vq() local
1507 rvin_stop_streaming(vin); in rvin_stop_streaming_vq()
1510 dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch, in rvin_stop_streaming_vq()
1511 vin->scratch_phys); in rvin_stop_streaming_vq()
1513 return_unused_buffers(vin, VB2_BUF_STATE_ERROR); in rvin_stop_streaming_vq()
1526 void rvin_dma_unregister(struct rvin_dev *vin) in rvin_dma_unregister() argument
1528 mutex_destroy(&vin->lock); in rvin_dma_unregister()
1530 v4l2_device_unregister(&vin->v4l2_dev); in rvin_dma_unregister()
1533 int rvin_dma_register(struct rvin_dev *vin, int irq) in rvin_dma_register() argument
1535 struct vb2_queue *q = &vin->queue; in rvin_dma_register()
1539 ret = v4l2_device_register(vin->dev, &vin->v4l2_dev); in rvin_dma_register()
1543 mutex_init(&vin->lock); in rvin_dma_register()
1544 INIT_LIST_HEAD(&vin->buf_list); in rvin_dma_register()
1546 spin_lock_init(&vin->qlock); in rvin_dma_register()
1548 vin->state = STOPPED; in rvin_dma_register()
1551 vin->buf_hw[i].buffer = NULL; in rvin_dma_register()
1556 q->lock = &vin->lock; in rvin_dma_register()
1557 q->drv_priv = vin; in rvin_dma_register()
1563 q->dev = vin->dev; in rvin_dma_register()
1567 vin_err(vin, "failed to initialize VB2 queue\n"); in rvin_dma_register()
1572 ret = devm_request_irq(vin->dev, irq, rvin_irq, IRQF_SHARED, in rvin_dma_register()
1573 KBUILD_MODNAME, vin); in rvin_dma_register()
1575 vin_err(vin, "failed to request irq\n"); in rvin_dma_register()
1581 rvin_dma_unregister(vin); in rvin_dma_register()
1595 int rvin_set_channel_routing(struct rvin_dev *vin, u8 chsel) in rvin_set_channel_routing() argument
1602 ret = pm_runtime_resume_and_get(vin->dev); in rvin_set_channel_routing()
1607 vnmc = rvin_read(vin, VNMC_REG); in rvin_set_channel_routing()
1608 rvin_write(vin, vnmc & ~VNMC_VUP, VNMC_REG); in rvin_set_channel_routing()
1616 for (route = vin->info->routes; route->chsel; route++) { in rvin_set_channel_routing()
1628 rvin_write(vin, ifmd, VNCSI_IFMD_REG); in rvin_set_channel_routing()
1631 vin_dbg(vin, "Set IFMD 0x%x\n", ifmd); in rvin_set_channel_routing()
1633 vin->chsel = chsel; in rvin_set_channel_routing()
1636 rvin_write(vin, vnmc, VNMC_REG); in rvin_set_channel_routing()
1638 pm_runtime_put(vin->dev); in rvin_set_channel_routing()
1643 void rvin_set_alpha(struct rvin_dev *vin, unsigned int alpha) in rvin_set_alpha() argument
1648 spin_lock_irqsave(&vin->qlock, flags); in rvin_set_alpha()
1650 vin->alpha = alpha; in rvin_set_alpha()
1652 if (vin->state == STOPPED) in rvin_set_alpha()
1655 switch (vin->format.pixelformat) { in rvin_set_alpha()
1657 dmr = rvin_read(vin, VNDMR_REG) & ~VNDMR_ABIT; in rvin_set_alpha()
1658 if (vin->alpha) in rvin_set_alpha()
1662 dmr = rvin_read(vin, VNDMR_REG) & ~VNDMR_A8BIT_MASK; in rvin_set_alpha()
1663 dmr |= VNDMR_A8BIT(vin->alpha); in rvin_set_alpha()
1669 rvin_write(vin, dmr, VNDMR_REG); in rvin_set_alpha()
1671 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_set_alpha()