35 void print_cast_status(struct device *dev, void __iomem *reg,  in print_cast_status()  argument
39 	print_wrapper_reg(dev, reg, CAST_STATUS0);  in print_cast_status()
40 	print_wrapper_reg(dev, reg, CAST_STATUS1);  in print_cast_status()
41 	print_wrapper_reg(dev, reg, CAST_STATUS2);  in print_cast_status()
42 	print_wrapper_reg(dev, reg, CAST_STATUS3);  in print_cast_status()
43 	print_wrapper_reg(dev, reg, CAST_STATUS4);  in print_cast_status()
44 	print_wrapper_reg(dev, reg, CAST_STATUS5);  in print_cast_status()
45 	print_wrapper_reg(dev, reg, CAST_STATUS6);  in print_cast_status()
46 	print_wrapper_reg(dev, reg, CAST_STATUS7);  in print_cast_status()
47 	print_wrapper_reg(dev, reg, CAST_STATUS8);  in print_cast_status()
48 	print_wrapper_reg(dev, reg, CAST_STATUS9);  in print_cast_status()
49 	print_wrapper_reg(dev, reg, CAST_STATUS10);  in print_cast_status()
50 	print_wrapper_reg(dev, reg, CAST_STATUS11);  in print_cast_status()
51 	print_wrapper_reg(dev, reg, CAST_STATUS12);  in print_cast_status()
52 	print_wrapper_reg(dev, reg, CAST_STATUS13);  in print_cast_status()
55 	print_wrapper_reg(dev, reg, CAST_STATUS14);  in print_cast_status()
56 	print_wrapper_reg(dev, reg, CAST_STATUS15);  in print_cast_status()
57 	print_wrapper_reg(dev, reg, CAST_STATUS16);  in print_cast_status()
58 	print_wrapper_reg(dev, reg, CAST_STATUS17);  in print_cast_status()
59 	print_wrapper_reg(dev, reg, CAST_STATUS18);  in print_cast_status()
60 	print_wrapper_reg(dev, reg, CAST_STATUS19);  in print_cast_status()
63 void print_wrapper_info(struct device *dev, void __iomem *reg)  in print_wrapper_info()  argument
66 	print_wrapper_reg(dev, reg, GLB_CTRL);  in print_wrapper_info()
67 	print_wrapper_reg(dev, reg, COM_STATUS);  in print_wrapper_info()
68 	print_wrapper_reg(dev, reg, BUF_BASE0);  in print_wrapper_info()
69 	print_wrapper_reg(dev, reg, BUF_BASE1);  in print_wrapper_info()
70 	print_wrapper_reg(dev, reg, LINE_PITCH);  in print_wrapper_info()
71 	print_wrapper_reg(dev, reg, STM_BUFBASE);  in print_wrapper_info()
72 	print_wrapper_reg(dev, reg, STM_BUFSIZE);  in print_wrapper_info()
73 	print_wrapper_reg(dev, reg, IMGSIZE);  in print_wrapper_info()
74 	print_wrapper_reg(dev, reg, STM_CTRL);  in print_wrapper_info()
77 void mxc_jpeg_enable_irq(void __iomem *reg, int slot)  in mxc_jpeg_enable_irq()  argument
79 	writel(0xFFFFFFFF, reg + MXC_SLOT_OFFSET(slot, SLOT_STATUS));  in mxc_jpeg_enable_irq()
80 	writel(0xF0C, reg + MXC_SLOT_OFFSET(slot, SLOT_IRQ_EN));  in mxc_jpeg_enable_irq()
83 void mxc_jpeg_disable_irq(void __iomem *reg, int slot)  in mxc_jpeg_disable_irq()  argument
85 	writel(0x0, reg + MXC_SLOT_OFFSET(slot, SLOT_IRQ_EN));  in mxc_jpeg_disable_irq()
86 	writel(0xFFFFFFFF, reg + MXC_SLOT_OFFSET(slot, SLOT_STATUS));  in mxc_jpeg_disable_irq()
89 void mxc_jpeg_sw_reset(void __iomem *reg)  in mxc_jpeg_sw_reset()  argument
97 	writel(GLB_CTRL_SFT_RST, reg + GLB_CTRL);  in mxc_jpeg_sw_reset()
100 void mxc_jpeg_enc_mode_conf(struct device *dev, void __iomem *reg, u8 extseq)  in mxc_jpeg_enc_mode_conf()  argument
107 		writel(0xb0, reg + CAST_MODE);  in mxc_jpeg_enc_mode_conf()
109 		writel(0xa0, reg + CAST_MODE);  in mxc_jpeg_enc_mode_conf()
112 	writel(0x3ff, reg + CAST_CFG_MODE);  in mxc_jpeg_enc_mode_conf()
115 void mxc_jpeg_enc_mode_go(struct device *dev, void __iomem *reg, u8 extseq)  in mxc_jpeg_enc_mode_go()  argument
122 		writel(0x150, reg + CAST_MODE);  in mxc_jpeg_enc_mode_go()
124 		writel(0x140, reg + CAST_MODE);  in mxc_jpeg_enc_mode_go()
127 void mxc_jpeg_enc_set_quality(struct device *dev, void __iomem *reg, u8 quality)  in mxc_jpeg_enc_set_quality()  argument
132 	writel(quality, reg + CAST_QUALITY);  in mxc_jpeg_enc_set_quality()
135 void mxc_jpeg_dec_mode_go(struct device *dev, void __iomem *reg)  in mxc_jpeg_dec_mode_go()  argument
138 	writel(MXC_DEC_EXIT_IDLE_MODE, reg + CAST_CTRL);  in mxc_jpeg_dec_mode_go()
141 int mxc_jpeg_enable(void __iomem *reg)  in mxc_jpeg_enable()  argument
145 	writel(GLB_CTRL_JPG_EN, reg + GLB_CTRL);  in mxc_jpeg_enable()
146 	regval = readl(reg);  in mxc_jpeg_enable()
150 void mxc_jpeg_enable_slot(void __iomem *reg, int slot)  in mxc_jpeg_enable_slot()  argument
154 	regval = readl(reg + GLB_CTRL);  in mxc_jpeg_enable_slot()
155 	writel(GLB_CTRL_SLOT_EN(slot) | regval, reg + GLB_CTRL);  in mxc_jpeg_enable_slot()
158 void mxc_jpeg_set_l_endian(void __iomem *reg, int le)  in mxc_jpeg_set_l_endian()  argument
162 	regval = readl(reg + GLB_CTRL);  in mxc_jpeg_set_l_endian()
164 	writel(GLB_CTRL_L_ENDIAN(le) | regval, reg + GLB_CTRL); /* set */  in mxc_jpeg_set_l_endian()
182 void mxc_jpeg_set_desc(u32 desc, void __iomem *reg, int slot)  in mxc_jpeg_set_desc()  argument
185 	       reg + MXC_SLOT_OFFSET(slot, SLOT_NXT_DESCPT_PTR));  in mxc_jpeg_set_desc()
188 void mxc_jpeg_clr_desc(void __iomem *reg, int slot)  in mxc_jpeg_clr_desc()  argument
190 	writel(0, reg + MXC_SLOT_OFFSET(slot, SLOT_NXT_DESCPT_PTR));  in mxc_jpeg_clr_desc()