Lines Matching refs:state
25 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode);
26 static int power_down_qam(struct drxk_state *state);
27 static int set_dvbt_standard(struct drxk_state *state,
29 static int set_qam_standard(struct drxk_state *state,
31 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
33 static int set_dvbt_standard(struct drxk_state *state,
35 static int dvbt_start(struct drxk_state *state);
36 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
38 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status);
39 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status);
40 static int switch_antenna_to_qam(struct drxk_state *state);
41 static int switch_antenna_to_dvbt(struct drxk_state *state);
43 static bool is_dvbt(struct drxk_state *state) in is_dvbt() argument
45 return state->m_operation_mode == OM_DVBT; in is_dvbt()
48 static bool is_qam(struct drxk_state *state) in is_qam() argument
50 return state->m_operation_mode == OM_QAM_ITU_A || in is_qam()
51 state->m_operation_mode == OM_QAM_ITU_B || in is_qam()
52 state->m_operation_mode == OM_QAM_ITU_C; in is_qam()
94 #define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
97 #define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
100 #define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
191 static int drxk_i2c_lock(struct drxk_state *state) in drxk_i2c_lock() argument
193 i2c_lock_bus(state->i2c, I2C_LOCK_SEGMENT); in drxk_i2c_lock()
194 state->drxk_i2c_exclusive_lock = true; in drxk_i2c_lock()
199 static void drxk_i2c_unlock(struct drxk_state *state) in drxk_i2c_unlock() argument
201 if (!state->drxk_i2c_exclusive_lock) in drxk_i2c_unlock()
204 i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT); in drxk_i2c_unlock()
205 state->drxk_i2c_exclusive_lock = false; in drxk_i2c_unlock()
208 static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs, in drxk_i2c_transfer() argument
211 if (state->drxk_i2c_exclusive_lock) in drxk_i2c_transfer()
212 return __i2c_transfer(state->i2c, msgs, len); in drxk_i2c_transfer()
214 return i2c_transfer(state->i2c, msgs, len); in drxk_i2c_transfer()
217 static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val) in i2c_read1() argument
223 return drxk_i2c_transfer(state, msgs, 1); in i2c_read1()
226 static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len) in i2c_write() argument
234 status = drxk_i2c_transfer(state, &msg, 1); in i2c_write()
244 static int i2c_read(struct drxk_state *state, in i2c_read() argument
255 status = drxk_i2c_transfer(state, msgs, 2); in i2c_read()
269 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags) in read16_flags() argument
272 u8 adr = state->demod_address, mm1[4], mm2[2], len; in read16_flags()
274 if (state->single_master) in read16_flags()
289 status = i2c_read(state, adr, mm1, len, mm2, 2); in read16_flags()
298 static int read16(struct drxk_state *state, u32 reg, u16 *data) in read16() argument
300 return read16_flags(state, reg, data, 0); in read16()
303 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags) in read32_flags() argument
306 u8 adr = state->demod_address, mm1[4], mm2[4], len; in read32_flags()
308 if (state->single_master) in read32_flags()
323 status = i2c_read(state, adr, mm1, len, mm2, 4); in read32_flags()
333 static int read32(struct drxk_state *state, u32 reg, u32 *data) in read32() argument
335 return read32_flags(state, reg, data, 0); in read32()
338 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags) in write16_flags() argument
340 u8 adr = state->demod_address, mm[6], len; in write16_flags()
342 if (state->single_master) in write16_flags()
359 return i2c_write(state, adr, mm, len + 2); in write16_flags()
362 static int write16(struct drxk_state *state, u32 reg, u16 data) in write16() argument
364 return write16_flags(state, reg, data, 0); in write16()
367 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags) in write32_flags() argument
369 u8 adr = state->demod_address, mm[8], len; in write32_flags()
371 if (state->single_master) in write32_flags()
390 return i2c_write(state, adr, mm, len + 4); in write32_flags()
393 static int write32(struct drxk_state *state, u32 reg, u32 data) in write32() argument
395 return write32_flags(state, reg, data, 0); in write32()
398 static int write_block(struct drxk_state *state, u32 address, in write_block() argument
404 if (state->single_master) in write_block()
408 int chunk = blk_size > state->m_chunk_size ? in write_block()
409 state->m_chunk_size : blk_size; in write_block()
410 u8 *adr_buf = &state->chunk[0]; in write_block()
420 if (chunk == state->m_chunk_size) in write_block()
428 memcpy(&state->chunk[adr_length], p_block, chunk); in write_block()
432 status = i2c_write(state, state->demod_address, in write_block()
433 &state->chunk[0], chunk + adr_length); in write_block()
450 static int power_up_device(struct drxk_state *state) in power_up_device() argument
458 status = i2c_read1(state, state->demod_address, &data); in power_up_device()
462 status = i2c_write(state, state->demod_address, in power_up_device()
468 status = i2c_read1(state, state->demod_address, in power_up_device()
477 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE); in power_up_device()
480 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); in power_up_device()
484 status = write16(state, SIO_CC_PLL_LOCK__A, 1); in power_up_device()
488 state->m_current_power_mode = DRX_POWER_UP; in power_up_device()
498 static int init_state(struct drxk_state *state) in init_state() argument
554 state->m_has_lna = false; in init_state()
555 state->m_has_dvbt = false; in init_state()
556 state->m_has_dvbc = false; in init_state()
557 state->m_has_atv = false; in init_state()
558 state->m_has_oob = false; in init_state()
559 state->m_has_audio = false; in init_state()
561 if (!state->m_chunk_size) in init_state()
562 state->m_chunk_size = 124; in init_state()
564 state->m_osc_clock_freq = 0; in init_state()
565 state->m_smart_ant_inverted = false; in init_state()
566 state->m_b_p_down_open_bridge = false; in init_state()
569 state->m_sys_clock_freq = 151875; in init_state()
572 state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) * in init_state()
575 if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) in init_state()
576 state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; in init_state()
577 state->m_hi_cfg_wake_up_key = (state->demod_address << 1); in init_state()
579 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; in init_state()
581 state->m_b_power_down = (ul_power_down != 0); in init_state()
583 state->m_drxk_a3_patch_code = false; in init_state()
587 state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode; in init_state()
588 state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level; in init_state()
589 state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level; in init_state()
590 state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level; in init_state()
591 state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed; in init_state()
592 state->m_vsb_pga_cfg = 140; in init_state()
595 state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode; in init_state()
596 state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level; in init_state()
597 state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level; in init_state()
598 state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level; in init_state()
599 state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed; in init_state()
600 state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top; in init_state()
601 state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current; in init_state()
602 state->m_vsb_pre_saw_cfg.reference = 0x07; in init_state()
603 state->m_vsb_pre_saw_cfg.use_pre_saw = true; in init_state()
605 state->m_Quality83percent = DEFAULT_MER_83; in init_state()
606 state->m_Quality93percent = DEFAULT_MER_93; in init_state()
608 state->m_Quality83percent = ulQual83; in init_state()
609 state->m_Quality93percent = ulQual93; in init_state()
613 state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode; in init_state()
614 state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level; in init_state()
615 state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level; in init_state()
616 state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level; in init_state()
617 state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed; in init_state()
620 state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode; in init_state()
621 state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level; in init_state()
622 state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level; in init_state()
623 state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level; in init_state()
624 state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed; in init_state()
625 state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top; in init_state()
626 state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current; in init_state()
627 state->m_atv_pre_saw_cfg.reference = 0x04; in init_state()
628 state->m_atv_pre_saw_cfg.use_pre_saw = true; in init_state()
632 state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF; in init_state()
633 state->m_dvbt_rf_agc_cfg.output_level = 0; in init_state()
634 state->m_dvbt_rf_agc_cfg.min_output_level = 0; in init_state()
635 state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF; in init_state()
636 state->m_dvbt_rf_agc_cfg.top = 0x2100; in init_state()
637 state->m_dvbt_rf_agc_cfg.cut_off_current = 4000; in init_state()
638 state->m_dvbt_rf_agc_cfg.speed = 1; in init_state()
642 state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO; in init_state()
643 state->m_dvbt_if_agc_cfg.output_level = 0; in init_state()
644 state->m_dvbt_if_agc_cfg.min_output_level = 0; in init_state()
645 state->m_dvbt_if_agc_cfg.max_output_level = 9000; in init_state()
646 state->m_dvbt_if_agc_cfg.top = 13424; in init_state()
647 state->m_dvbt_if_agc_cfg.cut_off_current = 0; in init_state()
648 state->m_dvbt_if_agc_cfg.speed = 3; in init_state()
649 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30; in init_state()
650 state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000; in init_state()
653 state->m_dvbt_pre_saw_cfg.reference = 4; in init_state()
654 state->m_dvbt_pre_saw_cfg.use_pre_saw = false; in init_state()
657 state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF; in init_state()
658 state->m_qam_rf_agc_cfg.output_level = 0; in init_state()
659 state->m_qam_rf_agc_cfg.min_output_level = 6023; in init_state()
660 state->m_qam_rf_agc_cfg.max_output_level = 27000; in init_state()
661 state->m_qam_rf_agc_cfg.top = 0x2380; in init_state()
662 state->m_qam_rf_agc_cfg.cut_off_current = 4000; in init_state()
663 state->m_qam_rf_agc_cfg.speed = 3; in init_state()
666 state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO; in init_state()
667 state->m_qam_if_agc_cfg.output_level = 0; in init_state()
668 state->m_qam_if_agc_cfg.min_output_level = 0; in init_state()
669 state->m_qam_if_agc_cfg.max_output_level = 9000; in init_state()
670 state->m_qam_if_agc_cfg.top = 0x0511; in init_state()
671 state->m_qam_if_agc_cfg.cut_off_current = 0; in init_state()
672 state->m_qam_if_agc_cfg.speed = 3; in init_state()
673 state->m_qam_if_agc_cfg.ingain_tgt_max = 5119; in init_state()
674 state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50; in init_state()
676 state->m_qam_pga_cfg = 140; in init_state()
677 state->m_qam_pre_saw_cfg.reference = 4; in init_state()
678 state->m_qam_pre_saw_cfg.use_pre_saw = false; in init_state()
680 state->m_operation_mode = OM_NONE; in init_state()
681 state->m_drxk_state = DRXK_UNINITIALIZED; in init_state()
684 state->m_enable_mpeg_output = true; /* If TRUE; enable MPEG output */ in init_state()
685 state->m_insert_rs_byte = false; /* If TRUE; insert RS byte */ in init_state()
686 state->m_invert_data = false; /* If TRUE; invert DATA signals */ in init_state()
687 state->m_invert_err = false; /* If TRUE; invert ERR signal */ in init_state()
688 state->m_invert_str = false; /* If TRUE; invert STR signals */ in init_state()
689 state->m_invert_val = false; /* If TRUE; invert VAL signals */ in init_state()
690 state->m_invert_clk = (ul_invert_ts_clock != 0); /* If TRUE; invert CLK signals */ in init_state()
695 state->m_dvbt_bitrate = ul_dvbt_bitrate; in init_state()
696 state->m_dvbc_bitrate = ul_dvbc_bitrate; in init_state()
698 state->m_ts_data_strength = (ul_ts_data_strength & 0x07); in init_state()
701 state->m_mpeg_ts_static_bitrate = 19392658; in init_state()
702 state->m_disable_te_ihandling = false; in init_state()
705 state->m_insert_rs_byte = true; in init_state()
707 state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; in init_state()
709 state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out; in init_state()
710 state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; in init_state()
712 state->m_demod_lock_time_out = ul_demod_lock_time_out; in init_state()
715 state->m_constellation = DRX_CONSTELLATION_AUTO; in init_state()
716 state->m_qam_interleave_mode = DRXK_QAM_I12_J17; in init_state()
717 state->m_fec_rs_plen = 204 * 8; /* fecRsPlen annex A */ in init_state()
718 state->m_fec_rs_prescale = 1; in init_state()
720 state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM; in init_state()
721 state->m_agcfast_clip_ctrl_delay = 0; in init_state()
723 state->m_gpio_cfg = ul_gpio_cfg; in init_state()
725 state->m_b_power_down = false; in init_state()
726 state->m_current_power_mode = DRX_POWER_DOWN; in init_state()
728 state->m_rfmirror = (ul_rf_mirror == 0); in init_state()
729 state->m_if_agc_pol = false; in init_state()
733 static int drxx_open(struct drxk_state *state) in drxx_open() argument
742 status = write16(state, SCU_RAM_GPIO__A, in drxx_open()
747 status = read16(state, SIO_TOP_COMM_KEY__A, &key); in drxx_open()
750 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); in drxx_open()
753 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag); in drxx_open()
756 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid); in drxx_open()
759 status = write16(state, SIO_TOP_COMM_KEY__A, key); in drxx_open()
766 static int get_device_capabilities(struct drxk_state *state) in get_device_capabilities() argument
777 status = write16(state, SCU_RAM_GPIO__A, in get_device_capabilities()
781 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); in get_device_capabilities()
784 status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg); in get_device_capabilities()
787 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); in get_device_capabilities()
797 state->m_osc_clock_freq = 27000; in get_device_capabilities()
801 state->m_osc_clock_freq = 20250; in get_device_capabilities()
805 state->m_osc_clock_freq = 20250; in get_device_capabilities()
815 status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo); in get_device_capabilities()
824 state->m_device_spin = DRXK_SPIN_A1; in get_device_capabilities()
828 state->m_device_spin = DRXK_SPIN_A2; in get_device_capabilities()
832 state->m_device_spin = DRXK_SPIN_A3; in get_device_capabilities()
836 state->m_device_spin = DRXK_SPIN_UNKNOWN; in get_device_capabilities()
844 state->m_has_lna = false; in get_device_capabilities()
845 state->m_has_oob = false; in get_device_capabilities()
846 state->m_has_atv = false; in get_device_capabilities()
847 state->m_has_audio = false; in get_device_capabilities()
848 state->m_has_dvbt = true; in get_device_capabilities()
849 state->m_has_dvbc = true; in get_device_capabilities()
850 state->m_has_sawsw = true; in get_device_capabilities()
851 state->m_has_gpio2 = false; in get_device_capabilities()
852 state->m_has_gpio1 = false; in get_device_capabilities()
853 state->m_has_irqn = false; in get_device_capabilities()
857 state->m_has_lna = false; in get_device_capabilities()
858 state->m_has_oob = false; in get_device_capabilities()
859 state->m_has_atv = true; in get_device_capabilities()
860 state->m_has_audio = false; in get_device_capabilities()
861 state->m_has_dvbt = true; in get_device_capabilities()
862 state->m_has_dvbc = false; in get_device_capabilities()
863 state->m_has_sawsw = true; in get_device_capabilities()
864 state->m_has_gpio2 = true; in get_device_capabilities()
865 state->m_has_gpio1 = true; in get_device_capabilities()
866 state->m_has_irqn = false; in get_device_capabilities()
870 state->m_has_lna = false; in get_device_capabilities()
871 state->m_has_oob = false; in get_device_capabilities()
872 state->m_has_atv = true; in get_device_capabilities()
873 state->m_has_audio = false; in get_device_capabilities()
874 state->m_has_dvbt = true; in get_device_capabilities()
875 state->m_has_dvbc = false; in get_device_capabilities()
876 state->m_has_sawsw = true; in get_device_capabilities()
877 state->m_has_gpio2 = true; in get_device_capabilities()
878 state->m_has_gpio1 = true; in get_device_capabilities()
879 state->m_has_irqn = false; in get_device_capabilities()
883 state->m_has_lna = false; in get_device_capabilities()
884 state->m_has_oob = false; in get_device_capabilities()
885 state->m_has_atv = true; in get_device_capabilities()
886 state->m_has_audio = true; in get_device_capabilities()
887 state->m_has_dvbt = true; in get_device_capabilities()
888 state->m_has_dvbc = false; in get_device_capabilities()
889 state->m_has_sawsw = true; in get_device_capabilities()
890 state->m_has_gpio2 = true; in get_device_capabilities()
891 state->m_has_gpio1 = true; in get_device_capabilities()
892 state->m_has_irqn = false; in get_device_capabilities()
896 state->m_has_lna = false; in get_device_capabilities()
897 state->m_has_oob = false; in get_device_capabilities()
898 state->m_has_atv = true; in get_device_capabilities()
899 state->m_has_audio = true; in get_device_capabilities()
900 state->m_has_dvbt = true; in get_device_capabilities()
901 state->m_has_dvbc = true; in get_device_capabilities()
902 state->m_has_sawsw = true; in get_device_capabilities()
903 state->m_has_gpio2 = true; in get_device_capabilities()
904 state->m_has_gpio1 = true; in get_device_capabilities()
905 state->m_has_irqn = false; in get_device_capabilities()
909 state->m_has_lna = false; in get_device_capabilities()
910 state->m_has_oob = false; in get_device_capabilities()
911 state->m_has_atv = true; in get_device_capabilities()
912 state->m_has_audio = true; in get_device_capabilities()
913 state->m_has_dvbt = true; in get_device_capabilities()
914 state->m_has_dvbc = true; in get_device_capabilities()
915 state->m_has_sawsw = true; in get_device_capabilities()
916 state->m_has_gpio2 = true; in get_device_capabilities()
917 state->m_has_gpio1 = true; in get_device_capabilities()
918 state->m_has_irqn = false; in get_device_capabilities()
922 state->m_has_lna = false; in get_device_capabilities()
923 state->m_has_oob = false; in get_device_capabilities()
924 state->m_has_atv = true; in get_device_capabilities()
925 state->m_has_audio = true; in get_device_capabilities()
926 state->m_has_dvbt = true; in get_device_capabilities()
927 state->m_has_dvbc = true; in get_device_capabilities()
928 state->m_has_sawsw = true; in get_device_capabilities()
929 state->m_has_gpio2 = true; in get_device_capabilities()
930 state->m_has_gpio1 = true; in get_device_capabilities()
931 state->m_has_irqn = false; in get_device_capabilities()
935 state->m_has_lna = false; in get_device_capabilities()
936 state->m_has_oob = false; in get_device_capabilities()
937 state->m_has_atv = true; in get_device_capabilities()
938 state->m_has_audio = false; in get_device_capabilities()
939 state->m_has_dvbt = true; in get_device_capabilities()
940 state->m_has_dvbc = true; in get_device_capabilities()
941 state->m_has_sawsw = true; in get_device_capabilities()
942 state->m_has_gpio2 = true; in get_device_capabilities()
943 state->m_has_gpio1 = true; in get_device_capabilities()
944 state->m_has_irqn = false; in get_device_capabilities()
955 state->m_osc_clock_freq / 1000, in get_device_capabilities()
956 state->m_osc_clock_freq % 1000); in get_device_capabilities()
966 static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result) in hi_command() argument
974 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd); in hi_command()
982 ((state->m_hi_cfg_ctrl) & in hi_command()
993 status = read16(state, SIO_HI_RA_RAM_CMD__A, in hi_command()
998 status = read16(state, SIO_HI_RA_RAM_RES__A, p_result); in hi_command()
1007 static int hi_cfg_command(struct drxk_state *state) in hi_cfg_command() argument
1013 mutex_lock(&state->mutex); in hi_cfg_command()
1015 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, in hi_cfg_command()
1016 state->m_hi_cfg_timeout); in hi_cfg_command()
1019 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, in hi_cfg_command()
1020 state->m_hi_cfg_ctrl); in hi_cfg_command()
1023 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, in hi_cfg_command()
1024 state->m_hi_cfg_wake_up_key); in hi_cfg_command()
1027 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, in hi_cfg_command()
1028 state->m_hi_cfg_bridge_delay); in hi_cfg_command()
1031 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, in hi_cfg_command()
1032 state->m_hi_cfg_timing_div); in hi_cfg_command()
1035 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, in hi_cfg_command()
1039 status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL); in hi_cfg_command()
1043 state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; in hi_cfg_command()
1045 mutex_unlock(&state->mutex); in hi_cfg_command()
1051 static int init_hi(struct drxk_state *state) in init_hi() argument
1055 state->m_hi_cfg_wake_up_key = (state->demod_address << 1); in init_hi()
1056 state->m_hi_cfg_timeout = 0x96FF; in init_hi()
1058 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; in init_hi()
1060 return hi_cfg_command(state); in init_hi()
1063 static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable) in mpegts_configure_pins() argument
1072 state->m_enable_parallel ? "parallel" : "serial"); in mpegts_configure_pins()
1075 status = write16(state, SCU_RAM_GPIO__A, in mpegts_configure_pins()
1081 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); in mpegts_configure_pins()
1087 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000); in mpegts_configure_pins()
1090 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000); in mpegts_configure_pins()
1093 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000); in mpegts_configure_pins()
1096 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000); in mpegts_configure_pins()
1099 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000); in mpegts_configure_pins()
1102 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); in mpegts_configure_pins()
1105 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); in mpegts_configure_pins()
1108 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); in mpegts_configure_pins()
1111 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); in mpegts_configure_pins()
1114 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); in mpegts_configure_pins()
1117 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); in mpegts_configure_pins()
1120 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); in mpegts_configure_pins()
1126 ((state->m_ts_data_strength << in mpegts_configure_pins()
1128 sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength << in mpegts_configure_pins()
1132 status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg); in mpegts_configure_pins()
1136 if (state->enable_merr_cfg) in mpegts_configure_pins()
1139 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg); in mpegts_configure_pins()
1142 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg); in mpegts_configure_pins()
1146 if (state->m_enable_parallel) { in mpegts_configure_pins()
1148 status = write16(state, SIO_PDR_MD1_CFG__A, in mpegts_configure_pins()
1152 status = write16(state, SIO_PDR_MD2_CFG__A, in mpegts_configure_pins()
1156 status = write16(state, SIO_PDR_MD3_CFG__A, in mpegts_configure_pins()
1160 status = write16(state, SIO_PDR_MD4_CFG__A, in mpegts_configure_pins()
1164 status = write16(state, SIO_PDR_MD5_CFG__A, in mpegts_configure_pins()
1168 status = write16(state, SIO_PDR_MD6_CFG__A, in mpegts_configure_pins()
1172 status = write16(state, SIO_PDR_MD7_CFG__A, in mpegts_configure_pins()
1177 sio_pdr_mdx_cfg = ((state->m_ts_data_strength << in mpegts_configure_pins()
1181 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); in mpegts_configure_pins()
1184 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); in mpegts_configure_pins()
1187 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); in mpegts_configure_pins()
1190 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); in mpegts_configure_pins()
1193 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); in mpegts_configure_pins()
1196 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); in mpegts_configure_pins()
1199 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); in mpegts_configure_pins()
1203 status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg); in mpegts_configure_pins()
1206 status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg); in mpegts_configure_pins()
1211 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000); in mpegts_configure_pins()
1215 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); in mpegts_configure_pins()
1222 static int mpegts_disable(struct drxk_state *state) in mpegts_disable() argument
1226 return mpegts_configure_pins(state, false); in mpegts_disable()
1229 static int bl_chain_cmd(struct drxk_state *state, in bl_chain_cmd() argument
1237 mutex_lock(&state->mutex); in bl_chain_cmd()
1238 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN); in bl_chain_cmd()
1241 status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset); in bl_chain_cmd()
1244 status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements); in bl_chain_cmd()
1247 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); in bl_chain_cmd()
1254 status = read16(state, SIO_BL_STATUS__A, &bl_status); in bl_chain_cmd()
1269 mutex_unlock(&state->mutex); in bl_chain_cmd()
1274 static int download_microcode(struct drxk_state *state, in download_microcode() argument
1327 status = write_block(state, address, block_size, p_src); in download_microcode()
1338 static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable) in dvbt_enable_ofdm_token_ring() argument
1353 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); in dvbt_enable_ofdm_token_ring()
1359 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl); in dvbt_enable_ofdm_token_ring()
1363 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); in dvbt_enable_ofdm_token_ring()
1376 static int mpegts_stop(struct drxk_state *state) in mpegts_stop() argument
1385 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode); in mpegts_stop()
1389 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode); in mpegts_stop()
1394 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode); in mpegts_stop()
1398 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode); in mpegts_stop()
1407 static int scu_command(struct drxk_state *state, in scu_command() argument
1430 mutex_lock(&state->mutex); in scu_command()
1443 write_block(state, SCU_RAM_PARAM_0__A - in scu_command()
1449 status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd); in scu_command()
1464 status = read16(state, SCU_RAM_PARAM_0__A - ii, in scu_command()
1503 mutex_unlock(&state->mutex); in scu_command()
1507 static int set_iqm_af(struct drxk_state *state, bool active) in set_iqm_af() argument
1515 status = read16(state, IQM_AF_STDBY__A, &data); in set_iqm_af()
1533 status = write16(state, IQM_AF_STDBY__A, data); in set_iqm_af()
1541 static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode) in ctrl_power_mode() argument
1574 if (state->m_current_power_mode == *mode) in ctrl_power_mode()
1578 if (state->m_current_power_mode != DRX_POWER_UP) { in ctrl_power_mode()
1579 status = power_up_device(state); in ctrl_power_mode()
1582 status = dvbt_enable_ofdm_token_ring(state, true); in ctrl_power_mode()
1599 switch (state->m_operation_mode) { in ctrl_power_mode()
1601 status = mpegts_stop(state); in ctrl_power_mode()
1604 status = power_down_dvbt(state, false); in ctrl_power_mode()
1610 status = mpegts_stop(state); in ctrl_power_mode()
1613 status = power_down_qam(state); in ctrl_power_mode()
1620 status = dvbt_enable_ofdm_token_ring(state, false); in ctrl_power_mode()
1623 status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode); in ctrl_power_mode()
1626 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); in ctrl_power_mode()
1631 state->m_hi_cfg_ctrl |= in ctrl_power_mode()
1633 status = hi_cfg_command(state); in ctrl_power_mode()
1638 state->m_current_power_mode = *mode; in ctrl_power_mode()
1647 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode) in power_down_dvbt() argument
1656 status = read16(state, SCU_COMM_EXEC__A, &data); in power_down_dvbt()
1661 status = scu_command(state, in power_down_dvbt()
1668 status = scu_command(state, in power_down_dvbt()
1677 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); in power_down_dvbt()
1680 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); in power_down_dvbt()
1683 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); in power_down_dvbt()
1688 status = set_iqm_af(state, false); in power_down_dvbt()
1694 status = ctrl_power_mode(state, &power_mode); in power_down_dvbt()
1704 static int setoperation_mode(struct drxk_state *state, in setoperation_mode() argument
1717 status = write16(state, SCU_RAM_GPIO__A, in setoperation_mode()
1723 if (state->m_operation_mode == o_mode) in setoperation_mode()
1726 switch (state->m_operation_mode) { in setoperation_mode()
1731 status = mpegts_stop(state); in setoperation_mode()
1734 status = power_down_dvbt(state, true); in setoperation_mode()
1737 state->m_operation_mode = OM_NONE; in setoperation_mode()
1741 status = mpegts_stop(state); in setoperation_mode()
1744 status = power_down_qam(state); in setoperation_mode()
1747 state->m_operation_mode = OM_NONE; in setoperation_mode()
1761 state->m_operation_mode = o_mode; in setoperation_mode()
1762 status = set_dvbt_standard(state, o_mode); in setoperation_mode()
1769 (state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C'); in setoperation_mode()
1770 state->m_operation_mode = o_mode; in setoperation_mode()
1771 status = set_qam_standard(state, o_mode); in setoperation_mode()
1785 static int start(struct drxk_state *state, s32 offset_freq, in start() argument
1794 if (state->m_drxk_state != DRXK_STOPPED && in start()
1795 state->m_drxk_state != DRXK_DTV_STARTED) in start()
1798 state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON); in start()
1801 state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect; in start()
1805 switch (state->m_operation_mode) { in start()
1809 status = set_qam(state, i_freqk_hz, offsetk_hz); in start()
1812 state->m_drxk_state = DRXK_DTV_STARTED; in start()
1816 status = mpegts_stop(state); in start()
1819 status = set_dvbt(state, i_freqk_hz, offsetk_hz); in start()
1822 status = dvbt_start(state); in start()
1825 state->m_drxk_state = DRXK_DTV_STARTED; in start()
1836 static int shut_down(struct drxk_state *state) in shut_down() argument
1840 mpegts_stop(state); in shut_down()
1844 static int get_lock_status(struct drxk_state *state, u32 *p_lock_status) in get_lock_status() argument
1856 switch (state->m_operation_mode) { in get_lock_status()
1860 status = get_qam_lock_status(state, p_lock_status); in get_lock_status()
1863 status = get_dvbt_lock_status(state, p_lock_status); in get_lock_status()
1867 state->m_operation_mode, __func__); in get_lock_status()
1876 static int mpegts_start(struct drxk_state *state) in mpegts_start() argument
1883 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode); in mpegts_start()
1887 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode); in mpegts_start()
1890 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1); in mpegts_start()
1897 static int mpegts_dto_init(struct drxk_state *state) in mpegts_dto_init() argument
1904 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000); in mpegts_dto_init()
1907 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C); in mpegts_dto_init()
1910 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A); in mpegts_dto_init()
1913 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008); in mpegts_dto_init()
1916 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006); in mpegts_dto_init()
1919 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680); in mpegts_dto_init()
1922 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080); in mpegts_dto_init()
1925 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4); in mpegts_dto_init()
1930 status = write16(state, FEC_OC_OCR_INVERT__A, 0); in mpegts_dto_init()
1933 status = write16(state, FEC_OC_SNC_LWM__A, 2); in mpegts_dto_init()
1936 status = write16(state, FEC_OC_SNC_HWM__A, 12); in mpegts_dto_init()
1944 static int mpegts_dto_setup(struct drxk_state *state, in mpegts_dto_setup() argument
1964 status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode); in mpegts_dto_setup()
1967 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode); in mpegts_dto_setup()
1972 if (state->m_insert_rs_byte) { in mpegts_dto_setup()
1983 if (!state->m_enable_parallel) { in mpegts_dto_setup()
1990 max_bit_rate = state->m_dvbt_bitrate; in mpegts_dto_setup()
1993 static_clk = state->m_dvbt_static_clk; in mpegts_dto_setup()
1999 max_bit_rate = state->m_dvbc_bitrate; in mpegts_dto_setup()
2000 static_clk = state->m_dvbc_static_clk; in mpegts_dto_setup()
2032 fec_oc_dto_period = (u16) (((state->m_sys_clock_freq) in mpegts_dto_setup()
2047 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len); in mpegts_dto_setup()
2050 status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period); in mpegts_dto_setup()
2053 status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode); in mpegts_dto_setup()
2056 status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode); in mpegts_dto_setup()
2059 status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode); in mpegts_dto_setup()
2062 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode); in mpegts_dto_setup()
2067 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate); in mpegts_dto_setup()
2070 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, in mpegts_dto_setup()
2074 status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode); in mpegts_dto_setup()
2081 static int mpegts_configure_polarity(struct drxk_state *state) in mpegts_configure_polarity() argument
2096 if (state->m_invert_data) in mpegts_configure_polarity()
2099 if (state->m_invert_err) in mpegts_configure_polarity()
2102 if (state->m_invert_str) in mpegts_configure_polarity()
2105 if (state->m_invert_val) in mpegts_configure_polarity()
2108 if (state->m_invert_clk) in mpegts_configure_polarity()
2111 return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert); in mpegts_configure_polarity()
2116 static int set_agc_rf(struct drxk_state *state, in set_agc_rf() argument
2131 status = read16(state, IQM_AF_STDBY__A, &data); in set_agc_rf()
2135 status = write16(state, IQM_AF_STDBY__A, data); in set_agc_rf()
2138 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in set_agc_rf()
2146 if (state->m_rf_agc_pol) in set_agc_rf()
2150 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in set_agc_rf()
2155 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); in set_agc_rf()
2164 status = write16(state, SCU_RAM_AGC_KI_RED__A, data); in set_agc_rf()
2168 if (is_dvbt(state)) in set_agc_rf()
2169 p_if_agc_settings = &state->m_dvbt_if_agc_cfg; in set_agc_rf()
2170 else if (is_qam(state)) in set_agc_rf()
2171 p_if_agc_settings = &state->m_qam_if_agc_cfg; in set_agc_rf()
2173 p_if_agc_settings = &state->m_atv_if_agc_cfg; in set_agc_rf()
2181 status = write16(state, in set_agc_rf()
2189 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, in set_agc_rf()
2195 status = write16(state, SCU_RAM_AGC_RF_MAX__A, in set_agc_rf()
2204 status = read16(state, IQM_AF_STDBY__A, &data); in set_agc_rf()
2208 status = write16(state, IQM_AF_STDBY__A, data); in set_agc_rf()
2213 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in set_agc_rf()
2217 if (state->m_rf_agc_pol) in set_agc_rf()
2221 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in set_agc_rf()
2226 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0); in set_agc_rf()
2231 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, in set_agc_rf()
2239 status = read16(state, IQM_AF_STDBY__A, &data); in set_agc_rf()
2243 status = write16(state, IQM_AF_STDBY__A, data); in set_agc_rf()
2248 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in set_agc_rf()
2252 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in set_agc_rf()
2269 static int set_agc_if(struct drxk_state *state, in set_agc_if() argument
2282 status = read16(state, IQM_AF_STDBY__A, &data); in set_agc_if()
2286 status = write16(state, IQM_AF_STDBY__A, data); in set_agc_if()
2290 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in set_agc_if()
2298 if (state->m_if_agc_pol) in set_agc_if()
2302 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in set_agc_if()
2307 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); in set_agc_if()
2315 status = write16(state, SCU_RAM_AGC_KI_RED__A, data); in set_agc_if()
2319 if (is_qam(state)) in set_agc_if()
2320 p_rf_agc_settings = &state->m_qam_rf_agc_cfg; in set_agc_if()
2322 p_rf_agc_settings = &state->m_atv_rf_agc_cfg; in set_agc_if()
2326 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, in set_agc_if()
2335 status = read16(state, IQM_AF_STDBY__A, &data); in set_agc_if()
2339 status = write16(state, IQM_AF_STDBY__A, data); in set_agc_if()
2343 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in set_agc_if()
2351 if (state->m_if_agc_pol) in set_agc_if()
2355 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in set_agc_if()
2360 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, in set_agc_if()
2369 status = read16(state, IQM_AF_STDBY__A, &data); in set_agc_if()
2373 status = write16(state, IQM_AF_STDBY__A, data); in set_agc_if()
2378 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in set_agc_if()
2382 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in set_agc_if()
2390 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top); in set_agc_if()
2397 static int get_qam_signal_to_noise(struct drxk_state *state, in get_qam_signal_to_noise() argument
2412 status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power); in get_qam_signal_to_noise()
2418 switch (state->props.modulation) { in get_qam_signal_to_noise()
2446 static int get_dvbt_signal_to_noise(struct drxk_state *state, in get_dvbt_signal_to_noise() argument
2466 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, in get_dvbt_signal_to_noise()
2470 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, in get_dvbt_signal_to_noise()
2474 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, in get_dvbt_signal_to_noise()
2478 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, in get_dvbt_signal_to_noise()
2488 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®_data); in get_dvbt_signal_to_noise()
2497 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, in get_dvbt_signal_to_noise()
2550 static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise) in get_signal_to_noise() argument
2555 switch (state->m_operation_mode) { in get_signal_to_noise()
2557 return get_dvbt_signal_to_noise(state, p_signal_to_noise); in get_signal_to_noise()
2560 return get_qam_signal_to_noise(state, p_signal_to_noise); in get_signal_to_noise()
2568 static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality)
2602 status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2605 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2611 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2635 static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality)
2647 status = get_qam_signal_to_noise(state, &signal_to_noise);
2651 switch (state->props.modulation) {
2682 static int get_quality(struct drxk_state *state, s32 *p_quality)
2686 switch (state->m_operation_mode) {
2688 return get_dvbt_quality(state, p_quality);
2690 return get_dvbc_quality(state, p_quality);
2712 static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge) in ConfigureI2CBridge() argument
2718 if (state->m_drxk_state == DRXK_UNINITIALIZED) in ConfigureI2CBridge()
2720 if (state->m_drxk_state == DRXK_POWERED_DOWN) in ConfigureI2CBridge()
2723 if (state->no_i2c_bridge) in ConfigureI2CBridge()
2726 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, in ConfigureI2CBridge()
2731 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, in ConfigureI2CBridge()
2736 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, in ConfigureI2CBridge()
2742 status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL); in ConfigureI2CBridge()
2750 static int set_pre_saw(struct drxk_state *state, in set_pre_saw() argument
2761 status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference); in set_pre_saw()
2768 static int bl_direct_cmd(struct drxk_state *state, u32 target_addr, in bl_direct_cmd() argument
2779 mutex_lock(&state->mutex); in bl_direct_cmd()
2780 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT); in bl_direct_cmd()
2783 status = write16(state, SIO_BL_TGT_HDR__A, blockbank); in bl_direct_cmd()
2786 status = write16(state, SIO_BL_TGT_ADDR__A, offset); in bl_direct_cmd()
2789 status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset); in bl_direct_cmd()
2792 status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements); in bl_direct_cmd()
2795 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); in bl_direct_cmd()
2801 status = read16(state, SIO_BL_STATUS__A, &bl_status); in bl_direct_cmd()
2814 mutex_unlock(&state->mutex); in bl_direct_cmd()
2819 static int adc_sync_measurement(struct drxk_state *state, u16 *count) in adc_sync_measurement() argument
2827 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); in adc_sync_measurement()
2830 status = write16(state, IQM_AF_START_LOCK__A, 1); in adc_sync_measurement()
2835 status = read16(state, IQM_AF_PHASE0__A, &data); in adc_sync_measurement()
2840 status = read16(state, IQM_AF_PHASE1__A, &data); in adc_sync_measurement()
2845 status = read16(state, IQM_AF_PHASE2__A, &data); in adc_sync_measurement()
2857 static int adc_synchronization(struct drxk_state *state) in adc_synchronization() argument
2864 status = adc_sync_measurement(state, &count); in adc_synchronization()
2872 status = read16(state, IQM_AF_CLKNEG__A, &clk_neg); in adc_synchronization()
2885 status = write16(state, IQM_AF_CLKNEG__A, clk_neg); in adc_synchronization()
2888 status = adc_sync_measurement(state, &count); in adc_synchronization()
2901 static int set_frequency_shifter(struct drxk_state *state, in set_frequency_shifter() argument
2908 bool tuner_mirror = !state->m_b_mirror_freq_spect; in set_frequency_shifter()
2913 u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3); in set_frequency_shifter()
2924 if ((state->m_operation_mode == OM_QAM_ITU_A) || in set_frequency_shifter()
2925 (state->m_operation_mode == OM_QAM_ITU_C) || in set_frequency_shifter()
2926 (state->m_operation_mode == OM_DVBT)) in set_frequency_shifter()
2950 image_to_select = state->m_rfmirror ^ tuner_mirror ^ in set_frequency_shifter()
2952 state->m_iqm_fs_rate_ofs = in set_frequency_shifter()
2956 state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1; in set_frequency_shifter()
2960 status = write32(state, IQM_FS_RATE_OFS_LO__A, in set_frequency_shifter()
2961 state->m_iqm_fs_rate_ofs); in set_frequency_shifter()
2967 static int init_agc(struct drxk_state *state, bool is_dtv) in init_agc() argument
2997 if (!is_qam(state)) { in init_agc()
2999 __func__, state->m_operation_mode); in init_agc()
3017 fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay; in init_agc()
3019 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, in init_agc()
3024 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode); in init_agc()
3027 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt); in init_agc()
3030 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min); in init_agc()
3033 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max); in init_agc()
3036 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, in init_agc()
3040 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, in init_agc()
3044 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0); in init_agc()
3047 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0); in init_agc()
3050 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0); in init_agc()
3053 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0); in init_agc()
3056 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max); in init_agc()
3059 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max); in init_agc()
3063 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, in init_agc()
3067 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, in init_agc()
3071 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen); in init_agc()
3075 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023); in init_agc()
3078 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023); in init_agc()
3081 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50); in init_agc()
3085 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20); in init_agc()
3088 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min); in init_agc()
3091 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min); in init_agc()
3094 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to); in init_agc()
3097 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to); in init_agc()
3100 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); in init_agc()
3103 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0); in init_agc()
3106 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117); in init_agc()
3109 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657); in init_agc()
3112 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0); in init_agc()
3115 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0); in init_agc()
3118 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0); in init_agc()
3121 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1); in init_agc()
3124 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0); in init_agc()
3127 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0); in init_agc()
3130 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0); in init_agc()
3133 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1); in init_agc()
3136 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500); in init_agc()
3139 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500); in init_agc()
3144 status = read16(state, SCU_RAM_AGC_KI__A, &data); in init_agc()
3154 status = write16(state, SCU_RAM_AGC_KI__A, data); in init_agc()
3161 static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err) in dvbtqam_get_acc_pkt_err() argument
3167 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); in dvbtqam_get_acc_pkt_err()
3169 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, in dvbtqam_get_acc_pkt_err()
3176 static int dvbt_sc_command(struct drxk_state *state, in dvbt_sc_command() argument
3188 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec); in dvbt_sc_command()
3200 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd); in dvbt_sc_command()
3212 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd); in dvbt_sc_command()
3231 status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1); in dvbt_sc_command()
3235 status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0); in dvbt_sc_command()
3240 status |= write16(state, OFDM_SC_RA_RAM_CMD__A, cmd); in dvbt_sc_command()
3253 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd); in dvbt_sc_command()
3260 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code); in dvbt_sc_command()
3277 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0)); in dvbt_sc_command()
3298 static int power_up_dvbt(struct drxk_state *state) in power_up_dvbt() argument
3304 status = ctrl_power_mode(state, &power_mode); in power_up_dvbt()
3310 static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled) in dvbt_ctrl_set_inc_enable() argument
3316 status = write16(state, IQM_CF_BYPASSDET__A, 0); in dvbt_ctrl_set_inc_enable()
3318 status = write16(state, IQM_CF_BYPASSDET__A, 1); in dvbt_ctrl_set_inc_enable()
3325 static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled) in dvbt_ctrl_set_fr_enable() argument
3333 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, in dvbt_ctrl_set_fr_enable()
3337 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0); in dvbt_ctrl_set_fr_enable()
3345 static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state, in dvbt_ctrl_set_echo_threshold() argument
3352 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data); in dvbt_ctrl_set_echo_threshold()
3373 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data); in dvbt_ctrl_set_echo_threshold()
3380 static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state, in dvbt_ctrl_set_sqi_speed() argument
3395 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A, in dvbt_ctrl_set_sqi_speed()
3413 static int dvbt_activate_presets(struct drxk_state *state) in dvbt_activate_presets() argument
3423 status = dvbt_ctrl_set_inc_enable(state, &setincenable); in dvbt_activate_presets()
3426 status = dvbt_ctrl_set_fr_enable(state, &setfrenable); in dvbt_activate_presets()
3429 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k); in dvbt_activate_presets()
3432 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k); in dvbt_activate_presets()
3435 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, in dvbt_activate_presets()
3436 state->m_dvbt_if_agc_cfg.ingain_tgt_max); in dvbt_activate_presets()
3453 static int set_dvbt_standard(struct drxk_state *state, in set_dvbt_standard() argument
3462 power_up_dvbt(state); in set_dvbt_standard()
3464 switch_antenna_to_dvbt(state); in set_dvbt_standard()
3466 status = scu_command(state, in set_dvbt_standard()
3474 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM in set_dvbt_standard()
3481 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); in set_dvbt_standard()
3484 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); in set_dvbt_standard()
3487 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); in set_dvbt_standard()
3493 status = write16(state, IQM_AF_UPD_SEL__A, 1); in set_dvbt_standard()
3497 status = write16(state, IQM_AF_CLP_LEN__A, 0); in set_dvbt_standard()
3501 status = write16(state, IQM_AF_SNS_LEN__A, 0); in set_dvbt_standard()
3505 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); in set_dvbt_standard()
3508 status = set_iqm_af(state, true); in set_dvbt_standard()
3512 status = write16(state, IQM_AF_AGC_RF__A, 0); in set_dvbt_standard()
3517 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */ in set_dvbt_standard()
3520 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */ in set_dvbt_standard()
3523 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */ in set_dvbt_standard()
3527 status = write16(state, IQM_RC_STRETCH__A, 16); in set_dvbt_standard()
3530 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */ in set_dvbt_standard()
3533 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */ in set_dvbt_standard()
3536 status = write16(state, IQM_CF_SCALE__A, 1600); in set_dvbt_standard()
3539 status = write16(state, IQM_CF_SCALE_SH__A, 0); in set_dvbt_standard()
3544 status = write16(state, IQM_AF_CLP_TH__A, 448); in set_dvbt_standard()
3547 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */ in set_dvbt_standard()
3551 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, in set_dvbt_standard()
3556 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */ in set_dvbt_standard()
3559 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2); in set_dvbt_standard()
3563 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1); in set_dvbt_standard()
3566 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); in set_dvbt_standard()
3571 status = adc_synchronization(state); in set_dvbt_standard()
3574 status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg); in set_dvbt_standard()
3579 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); in set_dvbt_standard()
3583 status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true); in set_dvbt_standard()
3586 status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true); in set_dvbt_standard()
3591 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data); in set_dvbt_standard()
3595 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data); in set_dvbt_standard()
3600 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); in set_dvbt_standard()
3604 if (!state->m_drxk_a3_rom_code) { in set_dvbt_standard()
3606 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, in set_dvbt_standard()
3607 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay); in set_dvbt_standard()
3614 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1); in set_dvbt_standard()
3617 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2); in set_dvbt_standard()
3623 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */ in set_dvbt_standard()
3629 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400); in set_dvbt_standard()
3633 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000); in set_dvbt_standard()
3637 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001); in set_dvbt_standard()
3642 status = mpegts_dto_setup(state, OM_DVBT); in set_dvbt_standard()
3646 status = dvbt_activate_presets(state); in set_dvbt_standard()
3662 static int dvbt_start(struct drxk_state *state) in dvbt_start() argument
3672 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, in dvbt_start()
3678 status = mpegts_start(state); in dvbt_start()
3681 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); in dvbt_start()
3699 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, in set_dvbt() argument
3712 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM in set_dvbt()
3719 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); in set_dvbt()
3724 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); in set_dvbt()
3727 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); in set_dvbt()
3733 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP); in set_dvbt()
3740 switch (state->props.transmission_mode) { in set_dvbt()
3752 switch (state->props.guard_interval) { in set_dvbt()
3770 switch (state->props.hierarchy) { in set_dvbt()
3787 switch (state->props.modulation) { in set_dvbt()
3822 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI); in set_dvbt()
3828 switch (state->props.code_rate_HP) { in set_dvbt()
3861 switch (state->props.bandwidth_hz) { in set_dvbt()
3863 state->props.bandwidth_hz = 8000000; in set_dvbt()
3867 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, in set_dvbt()
3872 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, in set_dvbt()
3876 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, in set_dvbt()
3880 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, in set_dvbt()
3884 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, in set_dvbt()
3891 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, in set_dvbt()
3896 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, in set_dvbt()
3900 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, in set_dvbt()
3904 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, in set_dvbt()
3908 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, in set_dvbt()
3915 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, in set_dvbt()
3920 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, in set_dvbt()
3924 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, in set_dvbt()
3928 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, in set_dvbt()
3932 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, in set_dvbt()
3956 ((state->m_sys_clock_freq * in set_dvbt()
3969 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs); in set_dvbt()
3980 status = set_frequency_shifter(state, intermediate_freqk_hz, in set_dvbt()
3988 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); in set_dvbt()
3993 status = write16(state, OFDM_SC_COMM_STATE__A, 0); in set_dvbt()
3996 status = write16(state, OFDM_SC_COMM_EXEC__A, 1); in set_dvbt()
4001 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM in set_dvbt()
4013 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM, in set_dvbt()
4018 if (!state->m_drxk_a3_rom_code) in set_dvbt()
4019 status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed); in set_dvbt()
4037 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status) in get_dvbt_lock_status() argument
4053 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec); in get_dvbt_lock_status()
4059 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock); in get_dvbt_lock_status()
4078 static int power_up_qam(struct drxk_state *state) in power_up_qam() argument
4084 status = ctrl_power_mode(state, &power_mode); in power_up_qam()
4093 static int power_down_qam(struct drxk_state *state) in power_down_qam() argument
4100 status = read16(state, SCU_COMM_EXEC__A, &data); in power_down_qam()
4109 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); in power_down_qam()
4112 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM in power_down_qam()
4119 status = set_iqm_af(state, false); in power_down_qam()
4141 static int set_qam_measurement(struct drxk_state *state, in set_qam_measurement() argument
4202 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period); in set_qam_measurement()
4205 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, in set_qam_measurement()
4209 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period); in set_qam_measurement()
4216 static int set_qam16(struct drxk_state *state) in set_qam16() argument
4223 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517); in set_qam16()
4226 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517); in set_qam16()
4229 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517); in set_qam16()
4232 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517); in set_qam16()
4235 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517); in set_qam16()
4238 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517); in set_qam16()
4242 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2); in set_qam16()
4245 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2); in set_qam16()
4248 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2); in set_qam16()
4251 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2); in set_qam16()
4254 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2); in set_qam16()
4257 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); in set_qam16()
4261 status = write16(state, QAM_SY_SYNC_HWM__A, 5); in set_qam16()
4264 status = write16(state, QAM_SY_SYNC_AWM__A, 4); in set_qam16()
4267 status = write16(state, QAM_SY_SYNC_LWM__A, 3); in set_qam16()
4272 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, in set_qam16()
4278 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); in set_qam16()
4281 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); in set_qam16()
4284 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); in set_qam16()
4287 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); in set_qam16()
4290 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); in set_qam16()
4293 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); in set_qam16()
4296 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); in set_qam16()
4299 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); in set_qam16()
4303 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); in set_qam16()
4306 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); in set_qam16()
4309 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); in set_qam16()
4312 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); in set_qam16()
4315 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); in set_qam16()
4318 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); in set_qam16()
4321 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); in set_qam16()
4324 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); in set_qam16()
4327 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32); in set_qam16()
4330 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); in set_qam16()
4333 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); in set_qam16()
4336 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); in set_qam16()
4343 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140); in set_qam16()
4346 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); in set_qam16()
4349 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95); in set_qam16()
4352 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120); in set_qam16()
4355 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230); in set_qam16()
4358 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105); in set_qam16()
4362 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); in set_qam16()
4365 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); in set_qam16()
4368 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24); in set_qam16()
4375 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16); in set_qam16()
4378 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220); in set_qam16()
4381 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25); in set_qam16()
4384 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6); in set_qam16()
4387 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24); in set_qam16()
4390 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65); in set_qam16()
4393 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127); in set_qam16()
4410 static int set_qam32(struct drxk_state *state) in set_qam32() argument
4418 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707); in set_qam32()
4421 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707); in set_qam32()
4424 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707); in set_qam32()
4427 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707); in set_qam32()
4430 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707); in set_qam32()
4433 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707); in set_qam32()
4438 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3); in set_qam32()
4441 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3); in set_qam32()
4444 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3); in set_qam32()
4447 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3); in set_qam32()
4450 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); in set_qam32()
4453 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); in set_qam32()
4457 status = write16(state, QAM_SY_SYNC_HWM__A, 6); in set_qam32()
4460 status = write16(state, QAM_SY_SYNC_AWM__A, 5); in set_qam32()
4463 status = write16(state, QAM_SY_SYNC_LWM__A, 3); in set_qam32()
4469 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, in set_qam32()
4477 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); in set_qam32()
4480 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); in set_qam32()
4483 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); in set_qam32()
4486 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); in set_qam32()
4489 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); in set_qam32()
4492 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); in set_qam32()
4495 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); in set_qam32()
4498 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); in set_qam32()
4502 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); in set_qam32()
4505 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); in set_qam32()
4508 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); in set_qam32()
4511 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); in set_qam32()
4514 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); in set_qam32()
4517 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); in set_qam32()
4520 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); in set_qam32()
4523 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); in set_qam32()
4526 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16); in set_qam32()
4529 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); in set_qam32()
4532 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); in set_qam32()
4535 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); in set_qam32()
4542 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90); in set_qam32()
4545 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); in set_qam32()
4548 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); in set_qam32()
4551 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); in set_qam32()
4554 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170); in set_qam32()
4557 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); in set_qam32()
4561 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); in set_qam32()
4564 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); in set_qam32()
4567 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10); in set_qam32()
4574 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); in set_qam32()
4577 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140); in set_qam32()
4580 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8); in set_qam32()
4583 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16); in set_qam32()
4586 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26); in set_qam32()
4589 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56); in set_qam32()
4592 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86); in set_qam32()
4606 static int set_qam64(struct drxk_state *state) in set_qam64() argument
4613 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336); in set_qam64()
4616 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618); in set_qam64()
4619 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988); in set_qam64()
4622 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809); in set_qam64()
4625 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809); in set_qam64()
4628 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609); in set_qam64()
4633 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4); in set_qam64()
4636 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4); in set_qam64()
4639 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4); in set_qam64()
4642 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4); in set_qam64()
4645 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); in set_qam64()
4648 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); in set_qam64()
4652 status = write16(state, QAM_SY_SYNC_HWM__A, 5); in set_qam64()
4655 status = write16(state, QAM_SY_SYNC_AWM__A, 4); in set_qam64()
4658 status = write16(state, QAM_SY_SYNC_LWM__A, 3); in set_qam64()
4663 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, in set_qam64()
4671 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); in set_qam64()
4674 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); in set_qam64()
4677 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); in set_qam64()
4680 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); in set_qam64()
4683 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); in set_qam64()
4686 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); in set_qam64()
4689 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); in set_qam64()
4692 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); in set_qam64()
4696 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); in set_qam64()
4699 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30); in set_qam64()
4702 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100); in set_qam64()
4705 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); in set_qam64()
4708 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30); in set_qam64()
4711 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); in set_qam64()
4714 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); in set_qam64()
4717 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); in set_qam64()
4720 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); in set_qam64()
4723 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); in set_qam64()
4726 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); in set_qam64()
4729 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); in set_qam64()
4736 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100); in set_qam64()
4739 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); in set_qam64()
4742 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); in set_qam64()
4745 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110); in set_qam64()
4748 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200); in set_qam64()
4751 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95); in set_qam64()
4755 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); in set_qam64()
4758 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); in set_qam64()
4761 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15); in set_qam64()
4768 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); in set_qam64()
4771 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141); in set_qam64()
4774 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7); in set_qam64()
4777 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0); in set_qam64()
4780 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15); in set_qam64()
4783 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45); in set_qam64()
4786 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80); in set_qam64()
4801 static int set_qam128(struct drxk_state *state) in set_qam128() argument
4808 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564); in set_qam128()
4811 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598); in set_qam128()
4814 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394); in set_qam128()
4817 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409); in set_qam128()
4820 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656); in set_qam128()
4823 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238); in set_qam128()
4828 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6); in set_qam128()
4831 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6); in set_qam128()
4834 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6); in set_qam128()
4837 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6); in set_qam128()
4840 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5); in set_qam128()
4843 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); in set_qam128()
4847 status = write16(state, QAM_SY_SYNC_HWM__A, 6); in set_qam128()
4850 status = write16(state, QAM_SY_SYNC_AWM__A, 5); in set_qam128()
4853 status = write16(state, QAM_SY_SYNC_LWM__A, 3); in set_qam128()
4860 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, in set_qam128()
4868 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); in set_qam128()
4871 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); in set_qam128()
4874 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); in set_qam128()
4877 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); in set_qam128()
4880 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); in set_qam128()
4883 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); in set_qam128()
4886 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); in set_qam128()
4889 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); in set_qam128()
4893 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); in set_qam128()
4896 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40); in set_qam128()
4899 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120); in set_qam128()
4902 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); in set_qam128()
4905 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40); in set_qam128()
4908 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60); in set_qam128()
4911 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); in set_qam128()
4914 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); in set_qam128()
4917 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64); in set_qam128()
4920 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); in set_qam128()
4923 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); in set_qam128()
4926 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); in set_qam128()
4933 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); in set_qam128()
4936 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); in set_qam128()
4939 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); in set_qam128()
4942 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); in set_qam128()
4945 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140); in set_qam128()
4948 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); in set_qam128()
4952 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); in set_qam128()
4955 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5); in set_qam128()
4959 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); in set_qam128()
4965 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); in set_qam128()
4968 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65); in set_qam128()
4971 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5); in set_qam128()
4974 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3); in set_qam128()
4977 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1); in set_qam128()
4980 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12); in set_qam128()
4983 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23); in set_qam128()
4998 static int set_qam256(struct drxk_state *state) in set_qam256() argument
5005 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502); in set_qam256()
5008 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084); in set_qam256()
5011 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543); in set_qam256()
5014 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931); in set_qam256()
5017 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629); in set_qam256()
5020 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385); in set_qam256()
5025 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8); in set_qam256()
5028 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8); in set_qam256()
5031 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8); in set_qam256()
5034 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8); in set_qam256()
5037 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6); in set_qam256()
5040 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); in set_qam256()
5044 status = write16(state, QAM_SY_SYNC_HWM__A, 5); in set_qam256()
5047 status = write16(state, QAM_SY_SYNC_AWM__A, 4); in set_qam256()
5050 status = write16(state, QAM_SY_SYNC_LWM__A, 3); in set_qam256()
5056 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, in set_qam256()
5064 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); in set_qam256()
5067 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); in set_qam256()
5070 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); in set_qam256()
5073 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); in set_qam256()
5076 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); in set_qam256()
5079 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); in set_qam256()
5082 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); in set_qam256()
5085 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); in set_qam256()
5089 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); in set_qam256()
5092 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50); in set_qam256()
5095 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250); in set_qam256()
5098 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); in set_qam256()
5101 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50); in set_qam256()
5104 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125); in set_qam256()
5107 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); in set_qam256()
5110 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); in set_qam256()
5113 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); in set_qam256()
5116 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); in set_qam256()
5119 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); in set_qam256()
5122 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); in set_qam256()
5129 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); in set_qam256()
5132 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); in set_qam256()
5135 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); in set_qam256()
5138 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); in set_qam256()
5141 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150); in set_qam256()
5144 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110); in set_qam256()
5148 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); in set_qam256()
5151 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); in set_qam256()
5154 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); in set_qam256()
5161 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); in set_qam256()
5164 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74); in set_qam256()
5167 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18); in set_qam256()
5170 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13); in set_qam256()
5173 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7); in set_qam256()
5176 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0); in set_qam256()
5179 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8); in set_qam256()
5194 static int qam_reset_qam(struct drxk_state *state) in qam_reset_qam() argument
5201 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); in qam_reset_qam()
5205 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM in qam_reset_qam()
5222 static int qam_set_symbolrate(struct drxk_state *state) in qam_set_symbolrate() argument
5233 adc_frequency = (state->m_sys_clock_freq * 1000) / 3; in qam_set_symbolrate()
5235 if (state->props.symbol_rate <= 1188750) in qam_set_symbolrate()
5237 else if (state->props.symbol_rate <= 2377500) in qam_set_symbolrate()
5239 else if (state->props.symbol_rate <= 4755000) in qam_set_symbolrate()
5241 status = write16(state, IQM_FD_RATESEL__A, ratesel); in qam_set_symbolrate()
5248 symb_freq = state->props.symbol_rate * (1 << ratesel); in qam_set_symbolrate()
5257 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate); in qam_set_symbolrate()
5260 state->m_iqm_rc_rate = iqm_rc_rate; in qam_set_symbolrate()
5264 symb_freq = state->props.symbol_rate; in qam_set_symbolrate()
5275 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate); in qam_set_symbolrate()
5292 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status) in get_qam_lock_status() argument
5299 status = scu_command(state, in get_qam_lock_status()
5333 static int qam_demodulator_command(struct drxk_state *state, in qam_demodulator_command() argument
5340 set_param_parameters[0] = state->m_constellation; /* modulation */ in qam_demodulator_command()
5346 if (state->m_operation_mode == OM_QAM_ITU_C) in qam_demodulator_command()
5351 status = scu_command(state, in qam_demodulator_command()
5358 status = scu_command(state, in qam_demodulator_command()
5364 if (state->m_operation_mode == OM_QAM_ITU_C) in qam_demodulator_command()
5374 status = scu_command(state, in qam_demodulator_command()
5391 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, in set_qam() argument
5396 int qam_demod_param_count = state->qam_demod_parameter_count; in set_qam()
5405 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP); in set_qam()
5408 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP); in set_qam()
5411 status = qam_reset_qam(state); in set_qam()
5420 status = qam_set_symbolrate(state); in set_qam()
5425 switch (state->props.modulation) { in set_qam()
5427 state->m_constellation = DRX_CONSTELLATION_QAM256; in set_qam()
5431 state->m_constellation = DRX_CONSTELLATION_QAM64; in set_qam()
5434 state->m_constellation = DRX_CONSTELLATION_QAM16; in set_qam()
5437 state->m_constellation = DRX_CONSTELLATION_QAM32; in set_qam()
5440 state->m_constellation = DRX_CONSTELLATION_QAM128; in set_qam()
5451 if (state->qam_demod_parameter_count == 4 in set_qam()
5452 || !state->qam_demod_parameter_count) { in set_qam()
5454 status = qam_demodulator_command(state, qam_demod_param_count); in set_qam()
5460 if (state->qam_demod_parameter_count == 2 in set_qam()
5461 || (!state->qam_demod_parameter_count && status < 0)) { in set_qam()
5463 status = qam_demodulator_command(state, qam_demod_param_count); in set_qam()
5470 state->qam_demod_parameter_count, in set_qam()
5471 state->microcode_name); in set_qam()
5473 } else if (!state->qam_demod_parameter_count) { in set_qam()
5482 state->qam_demod_parameter_count = qam_demod_param_count; in set_qam()
5494 status = set_frequency_shifter(state, intermediate_freqk_hz, in set_qam()
5500 status = set_qam_measurement(state, state->m_constellation, in set_qam()
5501 state->props.symbol_rate); in set_qam()
5506 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE); in set_qam()
5509 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE); in set_qam()
5514 status = write16(state, QAM_LC_RATE_LIMIT__A, 3); in set_qam()
5517 status = write16(state, QAM_LC_LPF_FACTORP__A, 4); in set_qam()
5520 status = write16(state, QAM_LC_LPF_FACTORI__A, 4); in set_qam()
5523 status = write16(state, QAM_LC_MODE__A, 7); in set_qam()
5527 status = write16(state, QAM_LC_QUAL_TAB0__A, 1); in set_qam()
5530 status = write16(state, QAM_LC_QUAL_TAB1__A, 1); in set_qam()
5533 status = write16(state, QAM_LC_QUAL_TAB2__A, 1); in set_qam()
5536 status = write16(state, QAM_LC_QUAL_TAB3__A, 1); in set_qam()
5539 status = write16(state, QAM_LC_QUAL_TAB4__A, 2); in set_qam()
5542 status = write16(state, QAM_LC_QUAL_TAB5__A, 2); in set_qam()
5545 status = write16(state, QAM_LC_QUAL_TAB6__A, 2); in set_qam()
5548 status = write16(state, QAM_LC_QUAL_TAB8__A, 2); in set_qam()
5551 status = write16(state, QAM_LC_QUAL_TAB9__A, 2); in set_qam()
5554 status = write16(state, QAM_LC_QUAL_TAB10__A, 2); in set_qam()
5557 status = write16(state, QAM_LC_QUAL_TAB12__A, 2); in set_qam()
5560 status = write16(state, QAM_LC_QUAL_TAB15__A, 3); in set_qam()
5563 status = write16(state, QAM_LC_QUAL_TAB16__A, 3); in set_qam()
5566 status = write16(state, QAM_LC_QUAL_TAB20__A, 4); in set_qam()
5569 status = write16(state, QAM_LC_QUAL_TAB25__A, 4); in set_qam()
5574 status = write16(state, QAM_SY_SP_INV__A, in set_qam()
5580 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); in set_qam()
5585 switch (state->props.modulation) { in set_qam()
5587 status = set_qam16(state); in set_qam()
5590 status = set_qam32(state); in set_qam()
5594 status = set_qam64(state); in set_qam()
5597 status = set_qam128(state); in set_qam()
5600 status = set_qam256(state); in set_qam()
5610 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); in set_qam()
5617 status = mpegts_dto_setup(state, state->m_operation_mode); in set_qam()
5622 status = mpegts_start(state); in set_qam()
5625 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); in set_qam()
5628 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE); in set_qam()
5631 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); in set_qam()
5636 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM in set_qam()
5651 static int set_qam_standard(struct drxk_state *state, in set_qam_standard() argument
5664 switch_antenna_to_qam(state); in set_qam_standard()
5667 status = power_up_qam(state); in set_qam_standard()
5671 status = qam_reset_qam(state); in set_qam_standard()
5677 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); in set_qam_standard()
5680 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); in set_qam_standard()
5688 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, in set_qam_standard()
5693 status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A, in set_qam_standard()
5699 status = bl_direct_cmd(state, in set_qam_standard()
5711 status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B); in set_qam_standard()
5714 status = write16(state, IQM_CF_SYMMETRIC__A, 0); in set_qam_standard()
5717 status = write16(state, IQM_CF_MIDTAP__A, in set_qam_standard()
5722 status = write16(state, IQM_RC_STRETCH__A, 21); in set_qam_standard()
5725 status = write16(state, IQM_AF_CLP_LEN__A, 0); in set_qam_standard()
5728 status = write16(state, IQM_AF_CLP_TH__A, 448); in set_qam_standard()
5731 status = write16(state, IQM_AF_SNS_LEN__A, 0); in set_qam_standard()
5734 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0); in set_qam_standard()
5738 status = write16(state, IQM_FS_ADJ_SEL__A, 1); in set_qam_standard()
5741 status = write16(state, IQM_RC_ADJ_SEL__A, 1); in set_qam_standard()
5744 status = write16(state, IQM_CF_ADJ_SEL__A, 1); in set_qam_standard()
5747 status = write16(state, IQM_AF_UPD_SEL__A, 0); in set_qam_standard()
5752 status = write16(state, IQM_CF_CLP_VAL__A, 500); in set_qam_standard()
5755 status = write16(state, IQM_CF_DATATH__A, 1000); in set_qam_standard()
5758 status = write16(state, IQM_CF_BYPASSDET__A, 1); in set_qam_standard()
5761 status = write16(state, IQM_CF_DET_LCT__A, 0); in set_qam_standard()
5764 status = write16(state, IQM_CF_WND_LEN__A, 1); in set_qam_standard()
5767 status = write16(state, IQM_CF_PKDTH__A, 1); in set_qam_standard()
5770 status = write16(state, IQM_AF_INC_BYPASS__A, 1); in set_qam_standard()
5775 status = set_iqm_af(state, true); in set_qam_standard()
5778 status = write16(state, IQM_AF_START_LOCK__A, 0x01); in set_qam_standard()
5783 status = adc_synchronization(state); in set_qam_standard()
5788 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000); in set_qam_standard()
5793 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); in set_qam_standard()
5800 status = init_agc(state, true); in set_qam_standard()
5803 status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg)); in set_qam_standard()
5808 status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true); in set_qam_standard()
5811 status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true); in set_qam_standard()
5816 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); in set_qam_standard()
5823 static int write_gpio(struct drxk_state *state) in write_gpio() argument
5830 status = write16(state, SCU_RAM_GPIO__A, in write_gpio()
5836 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); in write_gpio()
5840 if (state->m_has_sawsw) { in write_gpio()
5841 if (state->uio_mask & 0x0001) { /* UIO-1 */ in write_gpio()
5843 status = write16(state, SIO_PDR_SMA_TX_CFG__A, in write_gpio()
5844 state->m_gpio_cfg); in write_gpio()
5849 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); in write_gpio()
5852 if ((state->m_gpio & 0x0001) == 0) in write_gpio()
5857 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); in write_gpio()
5861 if (state->uio_mask & 0x0002) { /* UIO-2 */ in write_gpio()
5863 status = write16(state, SIO_PDR_SMA_RX_CFG__A, in write_gpio()
5864 state->m_gpio_cfg); in write_gpio()
5869 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); in write_gpio()
5872 if ((state->m_gpio & 0x0002) == 0) in write_gpio()
5877 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); in write_gpio()
5881 if (state->uio_mask & 0x0004) { /* UIO-3 */ in write_gpio()
5883 status = write16(state, SIO_PDR_GPIO_CFG__A, in write_gpio()
5884 state->m_gpio_cfg); in write_gpio()
5889 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); in write_gpio()
5892 if ((state->m_gpio & 0x0004) == 0) in write_gpio()
5897 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); in write_gpio()
5903 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); in write_gpio()
5910 static int switch_antenna_to_qam(struct drxk_state *state) in switch_antenna_to_qam() argument
5917 if (!state->antenna_gpio) in switch_antenna_to_qam()
5920 gpio_state = state->m_gpio & state->antenna_gpio; in switch_antenna_to_qam()
5922 if (state->antenna_dvbt ^ gpio_state) { in switch_antenna_to_qam()
5924 if (state->antenna_dvbt) in switch_antenna_to_qam()
5925 state->m_gpio &= ~state->antenna_gpio; in switch_antenna_to_qam()
5927 state->m_gpio |= state->antenna_gpio; in switch_antenna_to_qam()
5928 status = write_gpio(state); in switch_antenna_to_qam()
5935 static int switch_antenna_to_dvbt(struct drxk_state *state) in switch_antenna_to_dvbt() argument
5942 if (!state->antenna_gpio) in switch_antenna_to_dvbt()
5945 gpio_state = state->m_gpio & state->antenna_gpio; in switch_antenna_to_dvbt()
5947 if (!(state->antenna_dvbt ^ gpio_state)) { in switch_antenna_to_dvbt()
5949 if (state->antenna_dvbt) in switch_antenna_to_dvbt()
5950 state->m_gpio |= state->antenna_gpio; in switch_antenna_to_dvbt()
5952 state->m_gpio &= ~state->antenna_gpio; in switch_antenna_to_dvbt()
5953 status = write_gpio(state); in switch_antenna_to_dvbt()
5961 static int power_down_device(struct drxk_state *state) in power_down_device() argument
5972 if (state->m_b_p_down_open_bridge) { in power_down_device()
5974 status = ConfigureI2CBridge(state, true); in power_down_device()
5979 status = dvbt_enable_ofdm_token_ring(state, false); in power_down_device()
5983 status = write16(state, SIO_CC_PWD_MODE__A, in power_down_device()
5987 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); in power_down_device()
5990 state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; in power_down_device()
5991 status = hi_cfg_command(state); in power_down_device()
5999 static int init_drxk(struct drxk_state *state) in init_drxk() argument
6006 if (state->m_drxk_state == DRXK_UNINITIALIZED) { in init_drxk()
6007 drxk_i2c_lock(state); in init_drxk()
6008 status = power_up_device(state); in init_drxk()
6011 status = drxx_open(state); in init_drxk()
6015 status = write16(state, SIO_CC_SOFT_RST__A, in init_drxk()
6021 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); in init_drxk()
6029 state->m_drxk_a3_patch_code = true; in init_drxk()
6030 status = get_device_capabilities(state); in init_drxk()
6037 state->m_hi_cfg_bridge_delay = in init_drxk()
6038 (u16) ((state->m_osc_clock_freq / 1000) * in init_drxk()
6041 if (state->m_hi_cfg_bridge_delay > in init_drxk()
6043 state->m_hi_cfg_bridge_delay = in init_drxk()
6047 state->m_hi_cfg_bridge_delay += in init_drxk()
6048 state->m_hi_cfg_bridge_delay << in init_drxk()
6051 status = init_hi(state); in init_drxk()
6056 if (!(state->m_DRXK_A1_ROM_CODE) in init_drxk()
6057 && !(state->m_DRXK_A2_ROM_CODE)) in init_drxk()
6060 status = write16(state, SCU_RAM_GPIO__A, in init_drxk()
6067 status = mpegts_disable(state); in init_drxk()
6072 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP); in init_drxk()
6075 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP); in init_drxk()
6080 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, in init_drxk()
6086 status = write16(state, SIO_BL_COMM_EXEC__A, in init_drxk()
6090 status = bl_chain_cmd(state, 0, 6, 100); in init_drxk()
6094 if (state->fw) { in init_drxk()
6095 status = download_microcode(state, state->fw->data, in init_drxk()
6096 state->fw->size); in init_drxk()
6102 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, in init_drxk()
6108 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); in init_drxk()
6111 status = drxx_open(state); in init_drxk()
6118 status = ctrl_power_mode(state, &power_mode); in init_drxk()
6133 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, in init_drxk()
6142 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, in init_drxk()
6162 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0); in init_drxk()
6168 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); in init_drxk()
6172 status = mpegts_dto_init(state); in init_drxk()
6175 status = mpegts_stop(state); in init_drxk()
6178 status = mpegts_configure_polarity(state); in init_drxk()
6181 status = mpegts_configure_pins(state, state->m_enable_mpeg_output); in init_drxk()
6185 status = write_gpio(state); in init_drxk()
6189 state->m_drxk_state = DRXK_STOPPED; in init_drxk()
6191 if (state->m_b_power_down) { in init_drxk()
6192 status = power_down_device(state); in init_drxk()
6195 state->m_drxk_state = DRXK_POWERED_DOWN; in init_drxk()
6197 state->m_drxk_state = DRXK_STOPPED; in init_drxk()
6201 if (state->m_has_dvbc) { in init_drxk()
6202 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A; in init_drxk()
6203 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C; in init_drxk()
6204 strlcat(state->frontend.ops.info.name, " DVB-C", in init_drxk()
6205 sizeof(state->frontend.ops.info.name)); in init_drxk()
6207 if (state->m_has_dvbt) { in init_drxk()
6208 state->frontend.ops.delsys[n++] = SYS_DVBT; in init_drxk()
6209 strlcat(state->frontend.ops.info.name, " DVB-T", in init_drxk()
6210 sizeof(state->frontend.ops.info.name)); in init_drxk()
6212 drxk_i2c_unlock(state); in init_drxk()
6216 state->m_drxk_state = DRXK_NO_DEV; in init_drxk()
6217 drxk_i2c_unlock(state); in init_drxk()
6227 struct drxk_state *state = context; in load_firmware_cb() local
6232 state->microcode_name); in load_firmware_cb()
6234 state->microcode_name); in load_firmware_cb()
6235 state->microcode_name = NULL; in load_firmware_cb()
6248 state->fw = fw; in load_firmware_cb()
6250 init_drxk(state); in load_firmware_cb()
6255 struct drxk_state *state = fe->demodulator_priv; in drxk_release() local
6258 release_firmware(state->fw); in drxk_release()
6260 kfree(state); in drxk_release()
6265 struct drxk_state *state = fe->demodulator_priv; in drxk_sleep() local
6269 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_sleep()
6271 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_sleep()
6274 shut_down(state); in drxk_sleep()
6280 struct drxk_state *state = fe->demodulator_priv; in drxk_gate_ctrl() local
6284 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_gate_ctrl()
6287 return ConfigureI2CBridge(state, enable ? true : false); in drxk_gate_ctrl()
6294 struct drxk_state *state = fe->demodulator_priv; in drxk_set_parameters() local
6299 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_set_parameters()
6302 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_set_parameters()
6317 old_delsys = state->props.delivery_system; in drxk_set_parameters()
6318 state->props = *p; in drxk_set_parameters()
6321 shut_down(state); in drxk_set_parameters()
6325 if (!state->m_has_dvbc) in drxk_set_parameters()
6327 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? in drxk_set_parameters()
6329 if (state->m_itut_annex_c) in drxk_set_parameters()
6330 setoperation_mode(state, OM_QAM_ITU_C); in drxk_set_parameters()
6332 setoperation_mode(state, OM_QAM_ITU_A); in drxk_set_parameters()
6335 if (!state->m_has_dvbt) in drxk_set_parameters()
6337 setoperation_mode(state, OM_DVBT); in drxk_set_parameters()
6345 start(state, 0, IF); in drxk_set_parameters()
6362 static int get_strength(struct drxk_state *state, u64 *strength) in get_strength() argument
6377 if (is_dvbt(state)) { in get_strength()
6378 rf_agc = state->m_dvbt_rf_agc_cfg; in get_strength()
6379 if_agc = state->m_dvbt_if_agc_cfg; in get_strength()
6380 } else if (is_qam(state)) { in get_strength()
6381 rf_agc = state->m_qam_rf_agc_cfg; in get_strength()
6382 if_agc = state->m_qam_if_agc_cfg; in get_strength()
6384 rf_agc = state->m_atv_rf_agc_cfg; in get_strength()
6385 if_agc = state->m_atv_if_agc_cfg; in get_strength()
6390 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl); in get_strength()
6395 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc); in get_strength()
6423 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A, in get_strength()
6428 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, in get_strength()
6466 struct drxk_state *state = fe->demodulator_priv; in drxk_get_stats() local
6479 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_get_stats()
6481 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_get_stats()
6485 state->fe_status = 0; in drxk_get_stats()
6486 get_lock_status(state, &stat); in drxk_get_stats()
6488 state->fe_status |= 0x1f; in drxk_get_stats()
6490 state->fe_status |= 0x0f; in drxk_get_stats()
6492 state->fe_status |= 0x07; in drxk_get_stats()
6497 get_strength(state, &c->strength.stat[0].uvalue); in drxk_get_stats()
6502 get_signal_to_noise(state, &cnr); in drxk_get_stats()
6530 status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, ®16); in drxk_get_stats()
6535 status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , ®16); in drxk_get_stats()
6541 status = read16(state, FEC_RS_NR_BIT_ERRORS__A, ®16); in drxk_get_stats()
6546 status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, ®16); in drxk_get_stats()
6551 status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, ®16); in drxk_get_stats()
6556 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, ®16); in drxk_get_stats()
6560 write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); in drxk_get_stats()
6589 struct drxk_state *state = fe->demodulator_priv; in drxk_read_status() local
6598 *status = state->fe_status; in drxk_read_status()
6606 struct drxk_state *state = fe->demodulator_priv; in drxk_read_signal_strength() local
6611 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_read_signal_strength()
6613 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_read_signal_strength()
6622 struct drxk_state *state = fe->demodulator_priv; in drxk_read_snr() local
6627 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_read_snr()
6629 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_read_snr()
6632 get_signal_to_noise(state, &snr2); in drxk_read_snr()
6643 struct drxk_state *state = fe->demodulator_priv; in drxk_read_ucblocks() local
6648 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_read_ucblocks()
6650 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_read_ucblocks()
6653 dvbtqam_get_acc_pkt_err(state, &err); in drxk_read_ucblocks()
6661 struct drxk_state *state = fe->demodulator_priv; in drxk_get_tune_settings() local
6666 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_get_tune_settings()
6668 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_get_tune_settings()
6721 struct drxk_state *state = NULL; in drxk_attach() local
6726 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL); in drxk_attach()
6727 if (!state) in drxk_attach()
6730 state->i2c = i2c; in drxk_attach()
6731 state->demod_address = adr; in drxk_attach()
6732 state->single_master = config->single_master; in drxk_attach()
6733 state->microcode_name = config->microcode_name; in drxk_attach()
6734 state->qam_demod_parameter_count = config->qam_demod_parameter_count; in drxk_attach()
6735 state->no_i2c_bridge = config->no_i2c_bridge; in drxk_attach()
6736 state->antenna_gpio = config->antenna_gpio; in drxk_attach()
6737 state->antenna_dvbt = config->antenna_dvbt; in drxk_attach()
6738 state->m_chunk_size = config->chunk_size; in drxk_attach()
6739 state->enable_merr_cfg = config->enable_merr_cfg; in drxk_attach()
6742 state->m_dvbt_static_clk = false; in drxk_attach()
6743 state->m_dvbc_static_clk = false; in drxk_attach()
6745 state->m_dvbt_static_clk = true; in drxk_attach()
6746 state->m_dvbc_static_clk = true; in drxk_attach()
6751 state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07; in drxk_attach()
6753 state->m_ts_clockk_strength = 0x06; in drxk_attach()
6756 state->m_enable_parallel = true; in drxk_attach()
6758 state->m_enable_parallel = false; in drxk_attach()
6761 state->uio_mask = config->antenna_gpio; in drxk_attach()
6764 if (!state->antenna_dvbt && state->antenna_gpio) in drxk_attach()
6765 state->m_gpio |= state->antenna_gpio; in drxk_attach()
6767 state->m_gpio &= ~state->antenna_gpio; in drxk_attach()
6769 mutex_init(&state->mutex); in drxk_attach()
6771 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops)); in drxk_attach()
6772 state->frontend.demodulator_priv = state; in drxk_attach()
6774 init_state(state); in drxk_attach()
6777 if (state->microcode_name) { in drxk_attach()
6780 status = request_firmware(&fw, state->microcode_name, in drxk_attach()
6781 state->i2c->dev.parent); in drxk_attach()
6784 load_firmware_cb(fw, state); in drxk_attach()
6785 } else if (init_drxk(state) < 0) in drxk_attach()
6790 p = &state->frontend.dtv_property_cache; in drxk_attach()
6810 return &state->frontend; in drxk_attach()
6814 kfree(state); in drxk_attach()