Lines Matching refs:status

317 	int status = 0;  in WriteTable()  local
322 while (!status) { in WriteTable()
335 status = WriteBlock(state, Address, Length * 2, pTable, 0); in WriteTable()
338 return status; in WriteTable()
357 int status; in InitCE() local
361 status = WriteTable(state, state->m_InitCE); in InitCE()
362 if (status < 0) in InitCE()
370 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0); in InitCE()
371 if (status < 0) in InitCE()
374 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0); in InitCE()
375 if (status < 0) in InitCE()
378 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0); in InitCE()
379 if (status < 0) in InitCE()
382 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0); in InitCE()
383 if (status < 0) in InitCE()
388 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0); in InitCE()
389 if (status < 0) in InitCE()
392 return status; in InitCE()
397 int status = 0; in StopOC() local
405 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0); in StopOC()
406 if (status < 0) in StopOC()
413 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0); in StopOC()
414 if (status < 0) in StopOC()
416 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0); in StopOC()
417 if (status < 0) in StopOC()
419 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0); in StopOC()
420 if (status < 0) in StopOC()
422 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0); in StopOC()
423 if (status < 0) in StopOC()
427 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); in StopOC()
428 if (status < 0) in StopOC()
430 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); in StopOC()
431 if (status < 0) in StopOC()
436 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0); in StopOC()
437 if (status < 0) in StopOC()
442 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0); in StopOC()
443 if (status < 0) in StopOC()
448 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); in StopOC()
449 if (status < 0) in StopOC()
451 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0); in StopOC()
452 if (status < 0) in StopOC()
454 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); in StopOC()
455 if (status < 0) in StopOC()
459 return status; in StopOC()
464 int status = 0; in StartOC() local
468 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); in StartOC()
469 if (status < 0) in StartOC()
473 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0); in StartOC()
474 if (status < 0) in StartOC()
476 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0); in StartOC()
477 if (status < 0) in StartOC()
481 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0); in StartOC()
482 if (status < 0) in StartOC()
486 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); in StartOC()
487 if (status < 0) in StartOC()
490 return status; in StartOC()
525 int status; in DRX_GetLockStatus() local
529 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000); in DRX_GetLockStatus()
530 if (status < 0) { in DRX_GetLockStatus()
531 printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status); in DRX_GetLockStatus()
532 return status; in DRX_GetLockStatus()
555 int status; in SetCfgIfAgc() local
565 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); in SetCfgIfAgc()
566 if (status < 0) in SetCfgIfAgc()
570 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); in SetCfgIfAgc()
571 if (status < 0) in SetCfgIfAgc()
576 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0); in SetCfgIfAgc()
577 if (status < 0) in SetCfgIfAgc()
594 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); in SetCfgIfAgc()
595 if (status < 0) in SetCfgIfAgc()
600 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); in SetCfgIfAgc()
601 if (status < 0) in SetCfgIfAgc()
608 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0); in SetCfgIfAgc()
609 if (status < 0) in SetCfgIfAgc()
619 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0); in SetCfgIfAgc()
620 if (status < 0) in SetCfgIfAgc()
622 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0); in SetCfgIfAgc()
623 if (status < 0) in SetCfgIfAgc()
672 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0); in SetCfgIfAgc()
673 if (status < 0) in SetCfgIfAgc()
675 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0); in SetCfgIfAgc()
676 if (status < 0) in SetCfgIfAgc()
678 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0); in SetCfgIfAgc()
679 if (status < 0) in SetCfgIfAgc()
681 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0); in SetCfgIfAgc()
682 if (status < 0) in SetCfgIfAgc()
684 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0); in SetCfgIfAgc()
685 if (status < 0) in SetCfgIfAgc()
695 return status; in SetCfgIfAgc()
700 int status = 0; in SetCfgRfAgc() local
713 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000); in SetCfgRfAgc()
714 if (status < 0) in SetCfgRfAgc()
723 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); in SetCfgRfAgc()
724 if (status < 0) in SetCfgRfAgc()
727 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
728 if (status < 0) in SetCfgRfAgc()
734 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
735 if (status < 0) in SetCfgRfAgc()
741 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
742 if (status < 0) in SetCfgRfAgc()
748 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
749 if (status < 0) in SetCfgRfAgc()
765 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); in SetCfgRfAgc()
766 if (status < 0) in SetCfgRfAgc()
769 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
770 if (status < 0) in SetCfgRfAgc()
776 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
777 if (status < 0) in SetCfgRfAgc()
782 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000); in SetCfgRfAgc()
783 if (status < 0) in SetCfgRfAgc()
793 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
794 if (status < 0) in SetCfgRfAgc()
800 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
801 if (status < 0) in SetCfgRfAgc()
816 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); in SetCfgRfAgc()
817 if (status < 0) in SetCfgRfAgc()
820 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
821 if (status < 0) in SetCfgRfAgc()
827 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
828 if (status < 0) in SetCfgRfAgc()
834 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
835 if (status < 0) in SetCfgRfAgc()
841 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
842 if (status < 0) in SetCfgRfAgc()
847 return status; in SetCfgRfAgc()
852 int status = 0; in ReadIFAgc() local
857 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0); in ReadIFAgc()
859 if (status >= 0) { in ReadIFAgc()
887 return status; in ReadIFAgc()
917 int i, status = 0; in DownloadMicrocode() local
942 status = WriteBlock(state, Address, BlockSize, in DownloadMicrocode()
944 if (status < 0) in DownloadMicrocode()
949 return status; in DownloadMicrocode()
955 int status; in HI_Command() local
957 status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0); in HI_Command()
958 if (status < 0) in HI_Command()
959 return status; in HI_Command()
964 status = -1; in HI_Command()
967 status = Read16(state, HI_RA_RAM_SRV_CMD__A, NULL, 0); in HI_Command()
968 } while (status != 0); in HI_Command()
970 if (status >= 0) in HI_Command()
971 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0); in HI_Command()
972 return status; in HI_Command()
977 int status = 0; in HI_CfgCommand() local
990 status = Write16(state, HI_RA_RAM_SRV_CMD__A, in HI_CfgCommand()
993 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, NULL); in HI_CfgCommand()
995 return status; in HI_CfgCommand()
1008 int status; in HI_ResetCommand() local
1011 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A, in HI_ResetCommand()
1013 if (status == 0) in HI_ResetCommand()
1014 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, NULL); in HI_ResetCommand()
1017 return status; in HI_ResetCommand()
1040 int status;
1052 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1053 if (status < 0)
1055 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1056 if (status < 0)
1058 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1059 if (status < 0)
1061 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1062 if (status < 0)
1064 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1065 if (status < 0)
1068 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1069 if (status < 0)
1074 if (status >= 0) {
1078 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1080 if (status < 0)
1087 return status;
1094 int status;
1098 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1102 return status;
1127 int status = 0; in InitCC() local
1136 status |= Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0); in InitCC()
1137 status |= Write16(state, CC_REG_PLL_MODE__A, in InitCC()
1140 status |= Write16(state, CC_REG_REF_DIVIDE__A, in InitCC()
1142 status |= Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, in InitCC()
1144 status |= Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0); in InitCC()
1146 return status; in InitCC()
1151 int status = 0; in ResetECOD() local
1154 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0); in ResetECOD()
1156 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0); in ResetECOD()
1158 if (!(status < 0)) in ResetECOD()
1159 status = WriteTable(state, state->m_ResetECRAM); in ResetECOD()
1160 if (!(status < 0)) in ResetECOD()
1161 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0); in ResetECOD()
1162 return status; in ResetECOD()
1169 int status; in SetCfgPga() local
1176 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgPga()
1177 if (status < 0) in SetCfgPga()
1181 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgPga()
1182 if (status < 0) in SetCfgPga()
1186 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); in SetCfgPga()
1187 if (status < 0) in SetCfgPga()
1191 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); in SetCfgPga()
1192 if (status < 0) in SetCfgPga()
1197status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x000… in SetCfgPga()
1198 if (status < 0) in SetCfgPga()
1204 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgPga()
1205 if (status < 0) in SetCfgPga()
1209 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgPga()
1210 if (status < 0) in SetCfgPga()
1214 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); in SetCfgPga()
1215 if (status < 0) in SetCfgPga()
1219 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); in SetCfgPga()
1220 if (status < 0) in SetCfgPga()
1225status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x000… in SetCfgPga()
1226 if (status < 0) in SetCfgPga()
1230 return status; in SetCfgPga()
1235 int status; in InitFE() local
1238 status = WriteTable(state, state->m_InitFE_1); in InitFE()
1239 if (status < 0) in InitFE()
1243 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A, in InitFE()
1248 status = SetCfgPga(state, 0); in InitFE()
1250 status = in InitFE()
1256 if (status < 0) in InitFE()
1258 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000); in InitFE()
1259 if (status < 0) in InitFE()
1261 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); in InitFE()
1262 if (status < 0) in InitFE()
1265 status = WriteTable(state, state->m_InitFE_2); in InitFE()
1266 if (status < 0) in InitFE()
1271 return status; in InitFE()
1288 int status = Read16(state, SC_RA_RAM_CMD__A, NULL, 0); in SC_WaitForReady() local
1289 if (status == 0) in SC_WaitForReady()
1290 return status; in SC_WaitForReady()
1297 int status = 0, ret; in SC_SendCommand() local
1300 status = Write16(state, SC_RA_RAM_CMD__A, cmd, 0); in SC_SendCommand()
1301 if (status < 0) in SC_SendCommand()
1302 return status; in SC_SendCommand()
1310 status = -1; in SC_SendCommand()
1313 return status; in SC_SendCommand()
1319 int ret, status = 0; in SC_ProcStartCommand() local
1326 status = -1; in SC_ProcStartCommand()
1330 status |= Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); in SC_ProcStartCommand()
1331 status |= Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); in SC_ProcStartCommand()
1332 status |= Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); in SC_ProcStartCommand()
1337 return status; in SC_ProcStartCommand()
1343 int status; in SC_SetPrefParamCommand() local
1347 status = SC_WaitForReady(state); in SC_SetPrefParamCommand()
1348 if (status < 0) in SC_SetPrefParamCommand()
1350 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); in SC_SetPrefParamCommand()
1351 if (status < 0) in SC_SetPrefParamCommand()
1353 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); in SC_SetPrefParamCommand()
1354 if (status < 0) in SC_SetPrefParamCommand()
1356 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); in SC_SetPrefParamCommand()
1357 if (status < 0) in SC_SetPrefParamCommand()
1360 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM); in SC_SetPrefParamCommand()
1361 if (status < 0) in SC_SetPrefParamCommand()
1365 return status; in SC_SetPrefParamCommand()
1371 int status = 0;
1375 status = SC_WaitForReady(state);
1376 if (status < 0)
1378 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1379 if (status < 0)
1381 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1382 if (status < 0)
1386 return status;
1392 int status; in ConfigureMPEGOutput() local
1464 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0); in ConfigureMPEGOutput()
1465 if (status < 0) in ConfigureMPEGOutput()
1467 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0); in ConfigureMPEGOutput()
1468 if (status < 0) in ConfigureMPEGOutput()
1470 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000); in ConfigureMPEGOutput()
1471 if (status < 0) in ConfigureMPEGOutput()
1473 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0); in ConfigureMPEGOutput()
1474 if (status < 0) in ConfigureMPEGOutput()
1477 return status; in ConfigureMPEGOutput()
1482 int status = 0; in SetDeviceTypeId() local
1486 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); in SetDeviceTypeId()
1487 if (status < 0) in SetDeviceTypeId()
1490 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); in SetDeviceTypeId()
1491 if (status < 0) in SetDeviceTypeId()
1519 status = -1; in SetDeviceTypeId()
1525 if (status < 0) in SetDeviceTypeId()
1526 return status; in SetDeviceTypeId()
1571 return status; in SetDeviceTypeId()
1576 int status; in CorrectSysClockDeviation() local
1590 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0); in CorrectSysClockDeviation()
1591 if (status < 0) in CorrectSysClockDeviation()
1593 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0); in CorrectSysClockDeviation()
1594 if (status < 0) in CorrectSysClockDeviation()
1650 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0); in CorrectSysClockDeviation()
1651 if (status < 0) in CorrectSysClockDeviation()
1655 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0); in CorrectSysClockDeviation()
1656 if (status < 0) in CorrectSysClockDeviation()
1662 return status; in CorrectSysClockDeviation()
1667 int status; in DRX_Stop() local
1675 status = DRX_GetLockStatus(state, &lock); in DRX_Stop()
1676 if (status < 0) in DRX_Stop()
1680 status = StopOC(state); in DRX_Stop()
1681 if (status < 0) in DRX_Stop()
1686 status = ConfigureMPEGOutput(state, 0); in DRX_Stop()
1687 if (status < 0) in DRX_Stop()
1692 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000); in DRX_Stop()
1693 if (status < 0) in DRX_Stop()
1696 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1697 if (status < 0) in DRX_Stop()
1699 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1700 if (status < 0) in DRX_Stop()
1704 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1705 if (status < 0) in DRX_Stop()
1707 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1708 if (status < 0) in DRX_Stop()
1710 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1711 if (status < 0) in DRX_Stop()
1713 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1714 if (status < 0) in DRX_Stop()
1716 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1717 if (status < 0) in DRX_Stop()
1719 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1720 if (status < 0) in DRX_Stop()
1722 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0); in DRX_Stop()
1723 if (status < 0) in DRX_Stop()
1728 return status; in DRX_Stop()
1734 int status;
1738 status = -1;
1743 status = 0;
1748 status = -1;
1754 status = WriteTable(state, state->m_InitDiversityFront);
1757 status = WriteTable(state, state->m_InitDiversityEnd);
1763 status = WriteTable(state, state->m_DisableDiversity);
1768 if (!status)
1770 return status;
1776 int status = 0; in StartDiversity() local
1781 status = WriteTable(state, state->m_StartDiversityFront); in StartDiversity()
1782 if (status < 0) in StartDiversity()
1785 status = WriteTable(state, state->m_StartDiversityEnd); in StartDiversity()
1786 if (status < 0) in StartDiversity()
1789 status = WriteTable(state, state->m_DiversityDelay8MHZ); in StartDiversity()
1790 if (status < 0) in StartDiversity()
1793 status = WriteTable(state, state->m_DiversityDelay6MHZ); in StartDiversity()
1794 if (status < 0) in StartDiversity()
1798 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0); in StartDiversity()
1799 if (status < 0) in StartDiversity()
1807 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0); in StartDiversity()
1808 if (status < 0) in StartDiversity()
1812 return status; in StartDiversity()
1857 int status = 0; in SetCfgNoiseCalibration() local
1860 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0); in SetCfgNoiseCalibration()
1861 if (status < 0) in SetCfgNoiseCalibration()
1867 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0); in SetCfgNoiseCalibration()
1868 if (status < 0) in SetCfgNoiseCalibration()
1871 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0); in SetCfgNoiseCalibration()
1872 if (status < 0) in SetCfgNoiseCalibration()
1876 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0); in SetCfgNoiseCalibration()
1877 if (status < 0) in SetCfgNoiseCalibration()
1879 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0); in SetCfgNoiseCalibration()
1880 if (status < 0) in SetCfgNoiseCalibration()
1885 return status; in SetCfgNoiseCalibration()
1891 int status; in DRX_Start() local
1921 status = ResetECOD(state); in DRX_Start()
1922 if (status < 0) in DRX_Start()
1925 status = InitSC(state); in DRX_Start()
1926 if (status < 0) in DRX_Start()
1929 status = InitFT(state); in DRX_Start()
1930 if (status < 0) in DRX_Start()
1932 status = InitCP(state); in DRX_Start()
1933 if (status < 0) in DRX_Start()
1935 status = InitCE(state); in DRX_Start()
1936 if (status < 0) in DRX_Start()
1938 status = InitEQ(state); in DRX_Start()
1939 if (status < 0) in DRX_Start()
1941 status = InitSC(state); in DRX_Start()
1942 if (status < 0) in DRX_Start()
1948 status = SetCfgIfAgc(state, &state->if_agc_cfg); in DRX_Start()
1949 if (status < 0) in DRX_Start()
1951 status = SetCfgRfAgc(state, &state->rf_agc_cfg); in DRX_Start()
1952 if (status < 0) in DRX_Start()
1964 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000); in DRX_Start()
1965 if (status < 0) in DRX_Start()
1975 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000); in DRX_Start()
1976 if (status < 0) in DRX_Start()
2009 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000); in DRX_Start()
2010 if (status < 0) in DRX_Start()
2012 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000); in DRX_Start()
2013 if (status < 0) in DRX_Start()
2039 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000); in DRX_Start()
2040 if (status < 0) in DRX_Start()
2042 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000); in DRX_Start()
2043 if (status < 0) in DRX_Start()
2068 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000); in DRX_Start()
2069 if (status < 0) in DRX_Start()
2071 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000); in DRX_Start()
2072 if (status < 0) in DRX_Start()
2100 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000); in DRX_Start()
2101 if (status < 0) in DRX_Start()
2103 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000); in DRX_Start()
2104 if (status < 0) in DRX_Start()
2127 if (status < 0) in DRX_Start()
2137 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000); in DRX_Start()
2138 if (status < 0) in DRX_Start()
2140 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000); in DRX_Start()
2141 if (status < 0) in DRX_Start()
2143 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000); in DRX_Start()
2144 if (status < 0) in DRX_Start()
2146 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000); in DRX_Start()
2147 if (status < 0) in DRX_Start()
2149 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000); in DRX_Start()
2150 if (status < 0) in DRX_Start()
2153 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000); in DRX_Start()
2154 if (status < 0) in DRX_Start()
2156 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000); in DRX_Start()
2157 if (status < 0) in DRX_Start()
2159 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000); in DRX_Start()
2160 if (status < 0) in DRX_Start()
2162 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000); in DRX_Start()
2163 if (status < 0) in DRX_Start()
2170 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000); in DRX_Start()
2171 if (status < 0) in DRX_Start()
2173 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000); in DRX_Start()
2174 if (status < 0) in DRX_Start()
2176 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); in DRX_Start()
2177 if (status < 0) in DRX_Start()
2179 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000); in DRX_Start()
2180 if (status < 0) in DRX_Start()
2182 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); in DRX_Start()
2183 if (status < 0) in DRX_Start()
2186 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000); in DRX_Start()
2187 if (status < 0) in DRX_Start()
2189 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000); in DRX_Start()
2190 if (status < 0) in DRX_Start()
2192 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000); in DRX_Start()
2193 if (status < 0) in DRX_Start()
2195 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000); in DRX_Start()
2196 if (status < 0) in DRX_Start()
2204 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000); in DRX_Start()
2205 if (status < 0) in DRX_Start()
2207 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000); in DRX_Start()
2208 if (status < 0) in DRX_Start()
2210 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); in DRX_Start()
2211 if (status < 0) in DRX_Start()
2213 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000); in DRX_Start()
2214 if (status < 0) in DRX_Start()
2216 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); in DRX_Start()
2217 if (status < 0) in DRX_Start()
2220 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000); in DRX_Start()
2221 if (status < 0) in DRX_Start()
2223 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000); in DRX_Start()
2224 if (status < 0) in DRX_Start()
2226 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000); in DRX_Start()
2227 if (status < 0) in DRX_Start()
2229 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000); in DRX_Start()
2230 if (status < 0) in DRX_Start()
2236 if (status < 0) in DRX_Start()
2244 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000); in DRX_Start()
2248 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000); in DRX_Start()
2256 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000); in DRX_Start()
2264 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000); in DRX_Start()
2269 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000); in DRX_Start()
2274 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000); in DRX_Start()
2279 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000); in DRX_Start()
2282 if (status < 0) in DRX_Start()
2301 status = Write16(state, in DRX_Start()
2308 status = Write16(state, in DRX_Start()
2315 status = Write16(state, in DRX_Start()
2319 status = -EINVAL; in DRX_Start()
2321 if (status < 0) in DRX_Start()
2324 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000); in DRX_Start()
2325 if (status < 0) in DRX_Start()
2330 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0); in DRX_Start()
2331 if (status < 0) in DRX_Start()
2344 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0); in DRX_Start()
2345 if (status < 0) in DRX_Start()
2349 status = SetCfgNoiseCalibration(state, &state->noise_cal); in DRX_Start()
2350 if (status < 0) in DRX_Start()
2355 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000); in DRX_Start()
2356 if (status < 0) in DRX_Start()
2367 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000); in DRX_Start()
2368 if (status < 0) in DRX_Start()
2370status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_IN… in DRX_Start()
2371 if (status < 0) in DRX_Start()
2381 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000); in DRX_Start()
2382 if (status < 0) in DRX_Start()
2384 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000); in DRX_Start()
2385 if (status < 0) in DRX_Start()
2396 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode); in DRX_Start()
2397 if (status < 0) in DRX_Start()
2401status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_… in DRX_Start()
2402 if (status < 0) in DRX_Start()
2405 status = StartOC(state); in DRX_Start()
2406 if (status < 0) in DRX_Start()
2410 status = StartDiversity(state); in DRX_Start()
2411 if (status < 0) in DRX_Start()
2418 return status; in DRX_Start()
2576 int status = 0; in DRXD_init() local
2587 status = SetDeviceTypeId(state); in DRXD_init()
2588 if (status < 0) in DRXD_init()
2593 status = WriteTable(state, state->m_HiI2cPatch); in DRXD_init()
2594 if (status < 0) in DRXD_init()
2601 status = Write16(state, 0x43012D, 0x047f, 0); in DRXD_init()
2602 if (status < 0) in DRXD_init()
2606 status = HI_ResetCommand(state); in DRXD_init()
2607 if (status < 0) in DRXD_init()
2610 status = StopAllProcessors(state); in DRXD_init()
2611 if (status < 0) in DRXD_init()
2613 status = InitCC(state); in DRXD_init()
2614 if (status < 0) in DRXD_init()
2643 status = InitHI(state); in DRXD_init()
2644 if (status < 0) in DRXD_init()
2646 status = InitAtomicRead(state); in DRXD_init()
2647 if (status < 0) in DRXD_init()
2650 status = EnableAndResetMB(state); in DRXD_init()
2651 if (status < 0) in DRXD_init()
2654 status = ResetCEFR(state); in DRXD_init()
2655 if (status < 0) in DRXD_init()
2659 status = DownloadMicrocode(state, fw, fw_size); in DRXD_init()
2660 if (status < 0) in DRXD_init()
2663 status = DownloadMicrocode(state, state->microcode, state->microcode_length); in DRXD_init()
2664 if (status < 0) in DRXD_init()
2677 status = InitFE(state); in DRXD_init()
2678 if (status < 0) in DRXD_init()
2680 status = InitFT(state); in DRXD_init()
2681 if (status < 0) in DRXD_init()
2683 status = InitCP(state); in DRXD_init()
2684 if (status < 0) in DRXD_init()
2686 status = InitCE(state); in DRXD_init()
2687 if (status < 0) in DRXD_init()
2689 status = InitEQ(state); in DRXD_init()
2690 if (status < 0) in DRXD_init()
2692 status = InitEC(state); in DRXD_init()
2693 if (status < 0) in DRXD_init()
2695 status = InitSC(state); in DRXD_init()
2696 if (status < 0) in DRXD_init()
2699 status = SetCfgIfAgc(state, &state->if_agc_cfg); in DRXD_init()
2700 if (status < 0) in DRXD_init()
2702 status = SetCfgRfAgc(state, &state->rf_agc_cfg); in DRXD_init()
2703 if (status < 0) in DRXD_init()
2707 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRXD_init()
2708 if (status < 0) in DRXD_init()
2710 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRXD_init()
2711 if (status < 0) in DRXD_init()
2722 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0); in DRXD_init()
2723 if (status < 0) in DRXD_init()
2726 status = StopOC(state); in DRXD_init()
2727 if (status < 0) in DRXD_init()
2732 status = 0; in DRXD_init()
2734 return status; in DRXD_init()
2769 static int drxd_read_status(struct dvb_frontend *fe, enum fe_status *status) in drxd_read_status() argument
2775 *status = 0; in drxd_read_status()
2779 *status |= FE_HAS_LOCK; in drxd_read_status()
2782 *status |= FE_HAS_LOCK; in drxd_read_status()
2785 *status |= FE_HAS_VITERBI | FE_HAS_SYNC; in drxd_read_status()
2787 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL; in drxd_read_status()