Lines Matching refs:state
225 static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags) in Read16() argument
227 u8 adr = state->config.demod_address; in Read16()
232 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0) in Read16()
239 static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags) in Read32() argument
241 u8 adr = state->config.demod_address; in Read32()
247 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0) in Read32()
255 static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags) in Write16() argument
257 u8 adr = state->config.demod_address; in Write16()
263 if (i2c_write(state->i2c, adr, mm, 6) < 0) in Write16()
268 static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags) in Write32() argument
270 u8 adr = state->config.demod_address; in Write32()
277 if (i2c_write(state->i2c, adr, mm, 8) < 0) in Write32()
282 static int write_chunk(struct drxd_state *state, in write_chunk() argument
285 u8 adr = state->config.demod_address; in write_chunk()
293 if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) { in write_chunk()
300 static int WriteBlock(struct drxd_state *state, in WriteBlock() argument
306 if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0) in WriteBlock()
315 static int WriteTable(struct drxd_state *state, u8 * pTable) in WriteTable() argument
335 status = WriteBlock(state, Address, Length * 2, pTable, 0); in WriteTable()
345 static int ResetCEFR(struct drxd_state *state) in ResetCEFR() argument
347 return WriteTable(state, state->m_ResetCEFR); in ResetCEFR()
350 static int InitCP(struct drxd_state *state) in InitCP() argument
352 return WriteTable(state, state->m_InitCP); in InitCP()
355 static int InitCE(struct drxd_state *state) in InitCE() argument
358 enum app_env AppEnv = state->app_env_default; in InitCE()
361 status = WriteTable(state, state->m_InitCE); in InitCE()
365 if (state->operation_mode == OM_DVBT_Diversity_Front || in InitCE()
366 state->operation_mode == OM_DVBT_Diversity_End) { in InitCE()
367 AppEnv = state->app_env_diversity; in InitCE()
370 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0); in InitCE()
374 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0); in InitCE()
377 } else if (AppEnv == APPENV_MOBILE && state->type_A) { in InitCE()
378 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0); in InitCE()
381 } else if (AppEnv == APPENV_MOBILE && !state->type_A) { in InitCE()
382 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0); in InitCE()
388 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0); in InitCE()
395 static int StopOC(struct drxd_state *state) in StopOC() argument
399 u16 ocModeLop = state->m_EcOcRegOcModeLop; in StopOC()
405 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0); in StopOC()
409 state->m_EcOcRegSncSncLvl = ocSyncLvl; in StopOC()
413 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0); in StopOC()
416 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0); in StopOC()
419 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0); in StopOC()
422 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0); in StopOC()
427 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); in StopOC()
430 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); in StopOC()
436 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0); in StopOC()
442 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0); in StopOC()
448 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); in StopOC()
451 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0); in StopOC()
454 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); in StopOC()
462 static int StartOC(struct drxd_state *state) in StartOC() argument
468 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); in StartOC()
473 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0); in StartOC()
476 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0); in StartOC()
481 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0); in StartOC()
486 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); in StartOC()
493 static int InitEQ(struct drxd_state *state) in InitEQ() argument
495 return WriteTable(state, state->m_InitEQ); in InitEQ()
498 static int InitEC(struct drxd_state *state) in InitEC() argument
500 return WriteTable(state, state->m_InitEC); in InitEC()
503 static int InitSC(struct drxd_state *state) in InitSC() argument
505 return WriteTable(state, state->m_InitSC); in InitSC()
508 static int InitAtomicRead(struct drxd_state *state) in InitAtomicRead() argument
510 return WriteTable(state, state->m_InitAtomicRead); in InitAtomicRead()
513 static int CorrectSysClockDeviation(struct drxd_state *state);
515 static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus) in DRX_GetLockStatus() argument
529 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000); in DRX_GetLockStatus()
535 if (state->drxd_state != DRXD_STARTED) in DRX_GetLockStatus()
540 CorrectSysClockDeviation(state); in DRX_GetLockStatus()
553 static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg) in SetCfgIfAgc() argument
565 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); in SetCfgIfAgc()
570 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); in SetCfgIfAgc()
576 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0); in SetCfgIfAgc()
594 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); in SetCfgIfAgc()
600 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); in SetCfgIfAgc()
608 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0); in SetCfgIfAgc()
619 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0); in SetCfgIfAgc()
622 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0); in SetCfgIfAgc()
672 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0); in SetCfgIfAgc()
675 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0); in SetCfgIfAgc()
678 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0); in SetCfgIfAgc()
681 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0); in SetCfgIfAgc()
684 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0); in SetCfgIfAgc()
698 static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg) in SetCfgRfAgc() argument
713 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000); in SetCfgRfAgc()
720 state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M); in SetCfgRfAgc()
721 state->m_FeAgRegAgPwd |= in SetCfgRfAgc()
723 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); in SetCfgRfAgc()
727 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
734 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
741 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
748 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
761 (state->m_FeAgRegAgPwd) &= in SetCfgRfAgc()
763 (state->m_FeAgRegAgPwd) |= in SetCfgRfAgc()
765 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); in SetCfgRfAgc()
769 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
776 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
782 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000); in SetCfgRfAgc()
793 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
800 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
812 (state->m_FeAgRegAgPwd) &= in SetCfgRfAgc()
814 (state->m_FeAgRegAgPwd) |= in SetCfgRfAgc()
816 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); in SetCfgRfAgc()
820 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
827 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
834 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
841 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
850 static int ReadIFAgc(struct drxd_state *state, u32 * pValue) in ReadIFAgc() argument
855 if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) { in ReadIFAgc()
857 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0); in ReadIFAgc()
870 u32 R1 = state->if_agc_cfg.R1; in ReadIFAgc()
871 u32 R2 = state->if_agc_cfg.R2; in ReadIFAgc()
872 u32 R3 = state->if_agc_cfg.R3; in ReadIFAgc()
890 static int load_firmware(struct drxd_state *state, const char *fw_name) in load_firmware() argument
894 if (request_firmware(&fw, fw_name, state->dev) < 0) { in load_firmware()
899 state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL); in load_firmware()
900 if (!state->microcode) { in load_firmware()
905 state->microcode_length = fw->size; in load_firmware()
910 static int DownloadMicrocode(struct drxd_state *state, in DownloadMicrocode() argument
942 status = WriteBlock(state, Address, BlockSize, in DownloadMicrocode()
952 static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult) in HI_Command() argument
957 status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0); in HI_Command()
967 status = Read16(state, HI_RA_RAM_SRV_CMD__A, NULL, 0); in HI_Command()
971 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0); in HI_Command()
975 static int HI_CfgCommand(struct drxd_state *state) in HI_CfgCommand() argument
979 mutex_lock(&state->mutex); in HI_CfgCommand()
980 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0); in HI_CfgCommand()
981 Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0); in HI_CfgCommand()
982 Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0); in HI_CfgCommand()
983 Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0); in HI_CfgCommand()
984 Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0); in HI_CfgCommand()
986 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0); in HI_CfgCommand()
988 if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) == in HI_CfgCommand()
990 status = Write16(state, HI_RA_RAM_SRV_CMD__A, in HI_CfgCommand()
993 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, NULL); in HI_CfgCommand()
994 mutex_unlock(&state->mutex); in HI_CfgCommand()
998 static int InitHI(struct drxd_state *state) in InitHI() argument
1000 state->hi_cfg_wakeup_key = (state->chip_adr); in InitHI()
1002 state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON; in InitHI()
1003 return HI_CfgCommand(state); in InitHI()
1006 static int HI_ResetCommand(struct drxd_state *state) in HI_ResetCommand() argument
1010 mutex_lock(&state->mutex); in HI_ResetCommand()
1011 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A, in HI_ResetCommand()
1014 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, NULL); in HI_ResetCommand()
1015 mutex_unlock(&state->mutex); in HI_ResetCommand()
1020 static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge) in DRX_ConfigureI2CBridge() argument
1022 state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M); in DRX_ConfigureI2CBridge()
1024 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON; in DRX_ConfigureI2CBridge()
1026 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF; in DRX_ConfigureI2CBridge()
1028 return HI_CfgCommand(state); in DRX_ConfigureI2CBridge()
1037 static int AtomicReadBlock(struct drxd_state *state,
1047 mutex_lock(&state->mutex);
1052 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1055 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1058 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1061 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1064 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1068 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1078 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1086 mutex_unlock(&state->mutex);
1090 static int AtomicReadReg32(struct drxd_state *state,
1098 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1106 static int StopAllProcessors(struct drxd_state *state) in StopAllProcessors() argument
1108 return Write16(state, HI_COMM_EXEC__A, in StopAllProcessors()
1112 static int EnableAndResetMB(struct drxd_state *state) in EnableAndResetMB() argument
1114 if (state->type_A) { in EnableAndResetMB()
1116 Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000); in EnableAndResetMB()
1120 Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST); in EnableAndResetMB()
1121 Write16(state, HI_COMM_MB__A, 0x0000, 0x0000); in EnableAndResetMB()
1125 static int InitCC(struct drxd_state *state) in InitCC() argument
1129 if (state->osc_clock_freq == 0 || in InitCC()
1130 state->osc_clock_freq > 20000 || in InitCC()
1131 (state->osc_clock_freq % 4000) != 0) { in InitCC()
1132 printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq); in InitCC()
1136 status |= Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0); in InitCC()
1137 status |= Write16(state, CC_REG_PLL_MODE__A, in InitCC()
1140 status |= Write16(state, CC_REG_REF_DIVIDE__A, in InitCC()
1141 state->osc_clock_freq / 4000, 0); in InitCC()
1142 status |= Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, in InitCC()
1144 status |= Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0); in InitCC()
1149 static int ResetECOD(struct drxd_state *state) in ResetECOD() argument
1153 if (state->type_A) in ResetECOD()
1154 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0); in ResetECOD()
1156 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0); in ResetECOD()
1159 status = WriteTable(state, state->m_ResetECRAM); in ResetECOD()
1161 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0); in ResetECOD()
1167 static int SetCfgPga(struct drxd_state *state, int pgaSwitch) in SetCfgPga() argument
1176 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgPga()
1181 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgPga()
1186 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); in SetCfgPga()
1191 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); in SetCfgPga()
1197 …status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x000… in SetCfgPga()
1204 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgPga()
1209 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgPga()
1214 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); in SetCfgPga()
1219 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); in SetCfgPga()
1225 …status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x000… in SetCfgPga()
1233 static int InitFE(struct drxd_state *state) in InitFE() argument
1238 status = WriteTable(state, state->m_InitFE_1); in InitFE()
1242 if (state->type_A) { in InitFE()
1243 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A, in InitFE()
1247 if (state->PGA) in InitFE()
1248 status = SetCfgPga(state, 0); in InitFE()
1251 Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, in InitFE()
1258 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000); in InitFE()
1261 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); in InitFE()
1265 status = WriteTable(state, state->m_InitFE_2); in InitFE()
1274 static int InitFT(struct drxd_state *state) in InitFT() argument
1280 return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000); in InitFT()
1283 static int SC_WaitForReady(struct drxd_state *state) in SC_WaitForReady() argument
1288 int status = Read16(state, SC_RA_RAM_CMD__A, NULL, 0); in SC_WaitForReady()
1295 static int SC_SendCommand(struct drxd_state *state, u16 cmd) in SC_SendCommand() argument
1300 status = Write16(state, SC_RA_RAM_CMD__A, cmd, 0); in SC_SendCommand()
1304 SC_WaitForReady(state); in SC_SendCommand()
1306 ret = Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0); in SC_SendCommand()
1316 static int SC_ProcStartCommand(struct drxd_state *state, in SC_ProcStartCommand() argument
1322 mutex_lock(&state->mutex); in SC_ProcStartCommand()
1324 ret = Read16(state, SC_COMM_EXEC__A, &scExec, 0); in SC_ProcStartCommand()
1329 SC_WaitForReady(state); in SC_ProcStartCommand()
1330 status |= Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); in SC_ProcStartCommand()
1331 status |= Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); in SC_ProcStartCommand()
1332 status |= Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); in SC_ProcStartCommand()
1334 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START); in SC_ProcStartCommand()
1336 mutex_unlock(&state->mutex); in SC_ProcStartCommand()
1340 static int SC_SetPrefParamCommand(struct drxd_state *state, in SC_SetPrefParamCommand() argument
1345 mutex_lock(&state->mutex); in SC_SetPrefParamCommand()
1347 status = SC_WaitForReady(state); in SC_SetPrefParamCommand()
1350 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); in SC_SetPrefParamCommand()
1353 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); in SC_SetPrefParamCommand()
1356 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); in SC_SetPrefParamCommand()
1360 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM); in SC_SetPrefParamCommand()
1364 mutex_unlock(&state->mutex); in SC_SetPrefParamCommand()
1369 static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
1373 mutex_lock(&state->mutex);
1375 status = SC_WaitForReady(state);
1378 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1381 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1385 mutex_unlock(&state->mutex);
1390 static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput) in ConfigureMPEGOutput() argument
1402 if (state->operation_mode == OM_DVBT_Diversity_Front) { in ConfigureMPEGOutput()
1411 EcOcRegOcModeLop = state->m_EcOcRegOcModeLop; in ConfigureMPEGOutput()
1419 if (state->insert_rs_byte) { in ConfigureMPEGOutput()
1436 if (state->enable_parallel) in ConfigureMPEGOutput()
1464 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0); in ConfigureMPEGOutput()
1467 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0); in ConfigureMPEGOutput()
1470 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000); in ConfigureMPEGOutput()
1473 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0); in ConfigureMPEGOutput()
1480 static int SetDeviceTypeId(struct drxd_state *state) in SetDeviceTypeId() argument
1486 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); in SetDeviceTypeId()
1490 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); in SetDeviceTypeId()
1495 state->type_A = 0; in SetDeviceTypeId()
1496 state->PGA = 0; in SetDeviceTypeId()
1497 state->diversity = 0; in SetDeviceTypeId()
1499 state->type_A = 1; in SetDeviceTypeId()
1506 state->diversity = 1; in SetDeviceTypeId()
1510 state->PGA = 1; in SetDeviceTypeId()
1513 state->diversity = 1; in SetDeviceTypeId()
1529 state->m_InitAtomicRead = DRXD_InitAtomicRead; in SetDeviceTypeId()
1530 state->m_InitSC = DRXD_InitSC; in SetDeviceTypeId()
1531 state->m_ResetECRAM = DRXD_ResetECRAM; in SetDeviceTypeId()
1532 if (state->type_A) { in SetDeviceTypeId()
1533 state->m_ResetCEFR = DRXD_ResetCEFR; in SetDeviceTypeId()
1534 state->m_InitFE_1 = DRXD_InitFEA2_1; in SetDeviceTypeId()
1535 state->m_InitFE_2 = DRXD_InitFEA2_2; in SetDeviceTypeId()
1536 state->m_InitCP = DRXD_InitCPA2; in SetDeviceTypeId()
1537 state->m_InitCE = DRXD_InitCEA2; in SetDeviceTypeId()
1538 state->m_InitEQ = DRXD_InitEQA2; in SetDeviceTypeId()
1539 state->m_InitEC = DRXD_InitECA2; in SetDeviceTypeId()
1540 if (load_firmware(state, DRX_FW_FILENAME_A2)) in SetDeviceTypeId()
1543 state->m_ResetCEFR = NULL; in SetDeviceTypeId()
1544 state->m_InitFE_1 = DRXD_InitFEB1_1; in SetDeviceTypeId()
1545 state->m_InitFE_2 = DRXD_InitFEB1_2; in SetDeviceTypeId()
1546 state->m_InitCP = DRXD_InitCPB1; in SetDeviceTypeId()
1547 state->m_InitCE = DRXD_InitCEB1; in SetDeviceTypeId()
1548 state->m_InitEQ = DRXD_InitEQB1; in SetDeviceTypeId()
1549 state->m_InitEC = DRXD_InitECB1; in SetDeviceTypeId()
1550 if (load_firmware(state, DRX_FW_FILENAME_B1)) in SetDeviceTypeId()
1553 if (state->diversity) { in SetDeviceTypeId()
1554 state->m_InitDiversityFront = DRXD_InitDiversityFront; in SetDeviceTypeId()
1555 state->m_InitDiversityEnd = DRXD_InitDiversityEnd; in SetDeviceTypeId()
1556 state->m_DisableDiversity = DRXD_DisableDiversity; in SetDeviceTypeId()
1557 state->m_StartDiversityFront = DRXD_StartDiversityFront; in SetDeviceTypeId()
1558 state->m_StartDiversityEnd = DRXD_StartDiversityEnd; in SetDeviceTypeId()
1559 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ; in SetDeviceTypeId()
1560 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ; in SetDeviceTypeId()
1562 state->m_InitDiversityFront = NULL; in SetDeviceTypeId()
1563 state->m_InitDiversityEnd = NULL; in SetDeviceTypeId()
1564 state->m_DisableDiversity = NULL; in SetDeviceTypeId()
1565 state->m_StartDiversityFront = NULL; in SetDeviceTypeId()
1566 state->m_StartDiversityEnd = NULL; in SetDeviceTypeId()
1567 state->m_DiversityDelay8MHZ = NULL; in SetDeviceTypeId()
1568 state->m_DiversityDelay6MHZ = NULL; in SetDeviceTypeId()
1574 static int CorrectSysClockDeviation(struct drxd_state *state) in CorrectSysClockDeviation() argument
1590 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0); in CorrectSysClockDeviation()
1593 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0); in CorrectSysClockDeviation()
1597 if (state->type_A) { in CorrectSysClockDeviation()
1605 switch (state->props.bandwidth_hz) { in CorrectSysClockDeviation()
1631 (state->expected_sys_clock_freq)) * in CorrectSysClockDeviation()
1634 (state->expected_sys_clock_freq)); in CorrectSysClockDeviation()
1636 Diff = oscClockDeviation - state->osc_clock_deviation; in CorrectSysClockDeviation()
1639 state->sys_clock_freq = (u16) sysClockFreq; in CorrectSysClockDeviation()
1640 if (oscClockDeviation != state->osc_clock_deviation) { in CorrectSysClockDeviation()
1641 if (state->config.osc_deviation) { in CorrectSysClockDeviation()
1642 state->config.osc_deviation(state->priv, in CorrectSysClockDeviation()
1645 state->osc_clock_deviation = in CorrectSysClockDeviation()
1650 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0); in CorrectSysClockDeviation()
1655 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0); in CorrectSysClockDeviation()
1658 state->cscd_state = CSCD_SAVED; in CorrectSysClockDeviation()
1665 static int DRX_Stop(struct drxd_state *state) in DRX_Stop() argument
1669 if (state->drxd_state != DRXD_STARTED) in DRX_Stop()
1673 if (state->cscd_state != CSCD_SAVED) { in DRX_Stop()
1675 status = DRX_GetLockStatus(state, &lock); in DRX_Stop()
1680 status = StopOC(state); in DRX_Stop()
1684 state->drxd_state = DRXD_STOPPED; in DRX_Stop()
1686 status = ConfigureMPEGOutput(state, 0); in DRX_Stop()
1690 if (state->type_A) { in DRX_Stop()
1692 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000); in DRX_Stop()
1696 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1699 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1704 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1707 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1710 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1713 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1716 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1719 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1722 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0); in DRX_Stop()
1732 static int SetOperationMode(struct drxd_state *state, int oMode)
1737 if (state->drxd_state != DRXD_STOPPED) {
1742 if (oMode == state->operation_mode) {
1747 if (oMode != OM_Default && !state->diversity) {
1754 status = WriteTable(state, state->m_InitDiversityFront);
1757 status = WriteTable(state, state->m_InitDiversityEnd);
1763 status = WriteTable(state, state->m_DisableDiversity);
1769 state->operation_mode = oMode;
1774 static int StartDiversity(struct drxd_state *state) in StartDiversity() argument
1780 if (state->operation_mode == OM_DVBT_Diversity_Front) { in StartDiversity()
1781 status = WriteTable(state, state->m_StartDiversityFront); in StartDiversity()
1784 } else if (state->operation_mode == OM_DVBT_Diversity_End) { in StartDiversity()
1785 status = WriteTable(state, state->m_StartDiversityEnd); in StartDiversity()
1788 if (state->props.bandwidth_hz == 8000000) { in StartDiversity()
1789 status = WriteTable(state, state->m_DiversityDelay8MHZ); in StartDiversity()
1793 status = WriteTable(state, state->m_DiversityDelay6MHZ); in StartDiversity()
1798 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0); in StartDiversity()
1807 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0); in StartDiversity()
1815 static int SetFrequencyShift(struct drxd_state *state, in SetFrequencyShift() argument
1818 int negativeShift = (state->tuner_mirrors == channelMirrored); in SetFrequencyShift()
1831 state->fe_fs_add_incr = MulDiv32(state->intermediate_freq + in SetFrequencyShift()
1833 1 << 28, state->sys_clock_freq); in SetFrequencyShift()
1835 state->fe_fs_add_incr &= 0x0FFFFFFFL; in SetFrequencyShift()
1837 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr); in SetFrequencyShift()
1841 state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq, in SetFrequencyShift()
1842 1 << 28, state->sys_clock_freq); in SetFrequencyShift()
1844 state->org_fe_fs_add_incr &= 0x0FFFFFFFL; in SetFrequencyShift()
1846 state->org_fe_fs_add_incr = ((1L << 28) - in SetFrequencyShift()
1847 state->org_fe_fs_add_incr); in SetFrequencyShift()
1849 return Write32(state, FE_FS_REG_ADD_INC_LOP__A, in SetFrequencyShift()
1850 state->fe_fs_add_incr, 0); in SetFrequencyShift()
1853 static int SetCfgNoiseCalibration(struct drxd_state *state, in SetCfgNoiseCalibration() argument
1860 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0); in SetCfgNoiseCalibration()
1867 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0); in SetCfgNoiseCalibration()
1871 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0); in SetCfgNoiseCalibration()
1875 if (!state->type_A) { in SetCfgNoiseCalibration()
1876 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0); in SetCfgNoiseCalibration()
1879 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0); in SetCfgNoiseCalibration()
1888 static int DRX_Start(struct drxd_state *state, s32 off) in DRX_Start() argument
1890 struct dtv_frontend_properties *p = &state->props; in DRX_Start()
1919 if (state->drxd_state != DRXD_STOPPED) in DRX_Start()
1921 status = ResetECOD(state); in DRX_Start()
1924 if (state->type_A) { in DRX_Start()
1925 status = InitSC(state); in DRX_Start()
1929 status = InitFT(state); in DRX_Start()
1932 status = InitCP(state); in DRX_Start()
1935 status = InitCE(state); in DRX_Start()
1938 status = InitEQ(state); in DRX_Start()
1941 status = InitSC(state); in DRX_Start()
1948 status = SetCfgIfAgc(state, &state->if_agc_cfg); in DRX_Start()
1951 status = SetCfgRfAgc(state, &state->rf_agc_cfg); in DRX_Start()
1955 mirrorFreqSpect = (state->props.inversion == INVERSION_ON); in DRX_Start()
1963 if (state->type_A) { in DRX_Start()
1964 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000); in DRX_Start()
1974 if (state->type_A) { in DRX_Start()
1975 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000); in DRX_Start()
2008 if (state->type_A) { in DRX_Start()
2009 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000); in DRX_Start()
2012 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000); in DRX_Start()
2038 if (state->type_A) { in DRX_Start()
2039 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000); in DRX_Start()
2042 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000); in DRX_Start()
2067 if (state->type_A) { in DRX_Start()
2068 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000); in DRX_Start()
2071 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000); in DRX_Start()
2099 if (state->type_A) { in DRX_Start()
2100 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000); in DRX_Start()
2103 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000); in DRX_Start()
2136 if (state->type_A) { in DRX_Start()
2137 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000); in DRX_Start()
2140 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000); in DRX_Start()
2143 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000); in DRX_Start()
2146 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000); in DRX_Start()
2149 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000); in DRX_Start()
2153 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000); in DRX_Start()
2156 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000); in DRX_Start()
2159 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000); in DRX_Start()
2162 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000); in DRX_Start()
2169 if (state->type_A) { in DRX_Start()
2170 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000); in DRX_Start()
2173 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000); in DRX_Start()
2176 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); in DRX_Start()
2179 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000); in DRX_Start()
2182 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); in DRX_Start()
2186 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000); in DRX_Start()
2189 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000); in DRX_Start()
2192 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000); in DRX_Start()
2195 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000); in DRX_Start()
2203 if (state->type_A) { in DRX_Start()
2204 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000); in DRX_Start()
2207 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000); in DRX_Start()
2210 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); in DRX_Start()
2213 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000); in DRX_Start()
2216 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); in DRX_Start()
2220 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000); in DRX_Start()
2223 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000); in DRX_Start()
2226 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000); in DRX_Start()
2229 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000); in DRX_Start()
2244 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000); in DRX_Start()
2248 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000); in DRX_Start()
2255 if (state->type_A) in DRX_Start()
2256 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000); in DRX_Start()
2263 if (state->type_A) in DRX_Start()
2264 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000); in DRX_Start()
2268 if (state->type_A) in DRX_Start()
2269 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000); in DRX_Start()
2273 if (state->type_A) in DRX_Start()
2274 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000); in DRX_Start()
2278 if (state->type_A) in DRX_Start()
2279 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000); in DRX_Start()
2301 status = Write16(state, in DRX_Start()
2308 status = Write16(state, in DRX_Start()
2315 status = Write16(state, in DRX_Start()
2324 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000); in DRX_Start()
2330 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0); in DRX_Start()
2344 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0); in DRX_Start()
2349 status = SetCfgNoiseCalibration(state, &state->noise_cal); in DRX_Start()
2353 if (state->cscd_state == CSCD_INIT) { in DRX_Start()
2355 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000); in DRX_Start()
2359 state->cscd_state = CSCD_SET; in DRX_Start()
2365 feIfIncr = MulDiv32(state->sys_clock_freq * 1000, in DRX_Start()
2367 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000); in DRX_Start()
2370 …status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_IN… in DRX_Start()
2376 SetFrequencyShift(state, off, mirrorFreqSpect); in DRX_Start()
2381 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000); in DRX_Start()
2384 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000); in DRX_Start()
2396 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode); in DRX_Start()
2401 …status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_… in DRX_Start()
2405 status = StartOC(state); in DRX_Start()
2409 if (state->operation_mode != OM_Default) { in DRX_Start()
2410 status = StartDiversity(state); in DRX_Start()
2415 state->drxd_state = DRXD_STARTED; in DRX_Start()
2421 static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency) in CDRXD() argument
2441 u32 ulClock = state->config.clock; in CDRXD()
2451 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2452 state->if_agc_cfg.outputLevel = 0; in CDRXD()
2453 state->if_agc_cfg.settleLevel = 140; in CDRXD()
2454 state->if_agc_cfg.minOutputLevel = 0; in CDRXD()
2455 state->if_agc_cfg.maxOutputLevel = 1023; in CDRXD()
2456 state->if_agc_cfg.speed = 904; in CDRXD()
2459 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER; in CDRXD()
2460 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel); in CDRXD()
2468 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2469 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel); in CDRXD()
2470 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel); in CDRXD()
2471 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel); in CDRXD()
2472 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed); in CDRXD()
2475 state->if_agc_cfg.R1 = (u16) (ulIfAgcR1); in CDRXD()
2476 state->if_agc_cfg.R2 = (u16) (ulIfAgcR2); in CDRXD()
2477 state->if_agc_cfg.R3 = (u16) (ulIfAgcR3); in CDRXD()
2479 state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1); in CDRXD()
2480 state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2); in CDRXD()
2481 state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3); in CDRXD()
2483 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2486 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER; in CDRXD()
2487 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel); in CDRXD()
2495 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2496 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel); in CDRXD()
2497 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel); in CDRXD()
2498 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel); in CDRXD()
2499 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed); in CDRXD()
2503 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF; in CDRXD()
2506 state->app_env_default = (enum app_env) in CDRXD()
2509 state->app_env_diversity = (enum app_env) in CDRXD()
2514 state->noise_cal.cpOpt = 0; in CDRXD()
2515 state->noise_cal.cpNexpOfs = 40; in CDRXD()
2516 state->noise_cal.tdCal2k = -40; in CDRXD()
2517 state->noise_cal.tdCal8k = -24; in CDRXD()
2520 state->noise_cal.cpOpt = 1; in CDRXD()
2521 state->noise_cal.cpNexpOfs = 0; in CDRXD()
2522 state->noise_cal.tdCal2k = -21; in CDRXD()
2523 state->noise_cal.tdCal8k = -24; in CDRXD()
2525 state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop); in CDRXD()
2527 state->chip_adr = (state->config.demod_address << 1) | 1; in CDRXD()
2530 state->m_HiI2cPatch = DRXD_HiI2cPatch_1; in CDRXD()
2533 state->m_HiI2cPatch = DRXD_HiI2cPatch_3; in CDRXD()
2536 state->m_HiI2cPatch = NULL; in CDRXD()
2540 state->intermediate_freq = (u16) (IntermediateFrequency / 1000); in CDRXD()
2542 state->expected_sys_clock_freq = 48000; in CDRXD()
2544 state->sys_clock_freq = 48000; in CDRXD()
2545 state->osc_clock_freq = (u16) ulClock; in CDRXD()
2546 state->osc_clock_deviation = 0; in CDRXD()
2547 state->cscd_state = CSCD_INIT; in CDRXD()
2548 state->drxd_state = DRXD_UNINITIALIZED; in CDRXD()
2550 state->PGA = 0; in CDRXD()
2551 state->type_A = 0; in CDRXD()
2552 state->tuner_mirrors = 0; in CDRXD()
2555 state->insert_rs_byte = state->config.insert_rs_byte; in CDRXD()
2556 state->enable_parallel = (ulSerialMode != 1); in CDRXD()
2561 state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) * in CDRXD()
2565 state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) * in CDRXD()
2568 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; in CDRXD()
2570 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; in CDRXD()
2574 static int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size) in DRXD_init() argument
2579 if (state->init_done) in DRXD_init()
2582 CDRXD(state, state->config.IF ? state->config.IF : 36000000); in DRXD_init()
2585 state->operation_mode = OM_Default; in DRXD_init()
2587 status = SetDeviceTypeId(state); in DRXD_init()
2592 if (!state->type_A && state->m_HiI2cPatch) { in DRXD_init()
2593 status = WriteTable(state, state->m_HiI2cPatch); in DRXD_init()
2598 if (state->type_A) { in DRXD_init()
2601 status = Write16(state, 0x43012D, 0x047f, 0); in DRXD_init()
2606 status = HI_ResetCommand(state); in DRXD_init()
2610 status = StopAllProcessors(state); in DRXD_init()
2613 status = InitCC(state); in DRXD_init()
2617 state->osc_clock_deviation = 0; in DRXD_init()
2619 if (state->config.osc_deviation) in DRXD_init()
2620 state->osc_clock_deviation = in DRXD_init()
2621 state->config.osc_deviation(state->priv, 0, 0); in DRXD_init()
2625 s32 devA = (s32) (state->osc_clock_deviation) * in DRXD_init()
2626 (s32) (state->expected_sys_clock_freq); in DRXD_init()
2639 state->sys_clock_freq = in DRXD_init()
2640 (u16) ((state->expected_sys_clock_freq) + in DRXD_init()
2643 status = InitHI(state); in DRXD_init()
2646 status = InitAtomicRead(state); in DRXD_init()
2650 status = EnableAndResetMB(state); in DRXD_init()
2653 if (state->type_A) { in DRXD_init()
2654 status = ResetCEFR(state); in DRXD_init()
2659 status = DownloadMicrocode(state, fw, fw_size); in DRXD_init()
2663 status = DownloadMicrocode(state, state->microcode, state->microcode_length); in DRXD_init()
2668 if (state->PGA) { in DRXD_init()
2669 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; in DRXD_init()
2670 SetCfgPga(state, 0); /* PGA = 0 dB */ in DRXD_init()
2672 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; in DRXD_init()
2675 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; in DRXD_init()
2677 status = InitFE(state); in DRXD_init()
2680 status = InitFT(state); in DRXD_init()
2683 status = InitCP(state); in DRXD_init()
2686 status = InitCE(state); in DRXD_init()
2689 status = InitEQ(state); in DRXD_init()
2692 status = InitEC(state); in DRXD_init()
2695 status = InitSC(state); in DRXD_init()
2699 status = SetCfgIfAgc(state, &state->if_agc_cfg); in DRXD_init()
2702 status = SetCfgRfAgc(state, &state->rf_agc_cfg); in DRXD_init()
2706 state->cscd_state = CSCD_INIT; in DRXD_init()
2707 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRXD_init()
2710 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRXD_init()
2722 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0); in DRXD_init()
2726 status = StopOC(state); in DRXD_init()
2730 state->drxd_state = DRXD_STOPPED; in DRXD_init()
2731 state->init_done = 1; in DRXD_init()
2737 static int DRXD_status(struct drxd_state *state, u32 *pLockStatus) in DRXD_status() argument
2739 DRX_GetLockStatus(state, pLockStatus); in DRXD_status()
2743 ConfigureMPEGOutput(state, 1); in DRXD_status()
2757 struct drxd_state *state = fe->demodulator_priv; in drxd_read_signal_strength() local
2761 res = ReadIFAgc(state, &value); in drxd_read_signal_strength()
2771 struct drxd_state *state = fe->demodulator_priv; in drxd_read_status() local
2774 DRXD_status(state, &lock); in drxd_read_status()
2794 struct drxd_state *state = fe->demodulator_priv; in drxd_init() local
2796 return DRXD_init(state, NULL, 0); in drxd_init()
2801 struct drxd_state *state = fe->demodulator_priv; in drxd_config_i2c() local
2803 if (state->config.disable_i2c_gate_ctrl == 1) in drxd_config_i2c()
2806 return DRX_ConfigureI2CBridge(state, onoff); in drxd_config_i2c()
2838 struct drxd_state *state = fe->demodulator_priv; in drxd_sleep() local
2840 ConfigureMPEGOutput(state, 0); in drxd_sleep()
2852 struct drxd_state *state = fe->demodulator_priv; in drxd_set_frontend() local
2855 state->props = *p; in drxd_set_frontend()
2856 DRX_Stop(state); in drxd_set_frontend()
2866 return DRX_Start(state, off); in drxd_set_frontend()
2871 struct drxd_state *state = fe->demodulator_priv; in drxd_release() local
2873 kfree(state); in drxd_release()
2911 struct drxd_state *state = NULL; in drxd_attach() local
2913 state = kzalloc(sizeof(*state), GFP_KERNEL); in drxd_attach()
2914 if (!state) in drxd_attach()
2917 state->ops = drxd_ops; in drxd_attach()
2918 state->dev = dev; in drxd_attach()
2919 state->config = *config; in drxd_attach()
2920 state->i2c = i2c; in drxd_attach()
2921 state->priv = priv; in drxd_attach()
2923 mutex_init(&state->mutex); in drxd_attach()
2925 if (Read16(state, 0, NULL, 0) < 0) in drxd_attach()
2928 state->frontend.ops = drxd_ops; in drxd_attach()
2929 state->frontend.demodulator_priv = state; in drxd_attach()
2930 ConfigureMPEGOutput(state, 0); in drxd_attach()
2932 CDRXD(state, state->config.IF ? state->config.IF : 36000000); in drxd_attach()
2933 InitHI(state); in drxd_attach()
2935 return &state->frontend; in drxd_attach()
2939 kfree(state); in drxd_attach()