Lines Matching refs:rc
1421 int rc; in drxdap_fasi_read_block() local
1483 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, in drxdap_fasi_read_block()
1485 if (rc == 0) in drxdap_fasi_read_block()
1486 rc = drxbsp_i2c_write_read(NULL, 0, NULL, dev_addr, todo, data); in drxdap_fasi_read_block()
1489 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo, in drxdap_fasi_read_block()
1495 } while (datasize && rc == 0); in drxdap_fasi_read_block()
1497 return rc; in drxdap_fasi_read_block()
1524 int rc; in drxdap_fasi_read_reg16() local
1529 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags); in drxdap_fasi_read_reg16()
1531 return rc; in drxdap_fasi_read_reg16()
1557 int rc; in drxdap_fasi_read_reg32() local
1562 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags); in drxdap_fasi_read_reg32()
1566 return rc; in drxdap_fasi_read_reg32()
1767 int rc = -EIO; in drxdap_fasi_read_modify_write_reg16() local
1773 rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW); in drxdap_fasi_read_modify_write_reg16()
1774 if (rc == 0) in drxdap_fasi_read_modify_write_reg16()
1775 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0); in drxdap_fasi_read_modify_write_reg16()
1778 return rc; in drxdap_fasi_read_modify_write_reg16()
1840 int rc; in drxj_dap_rm_write_reg16short() local
1846 rc = drxdap_fasi_write_reg16(dev_addr, in drxj_dap_rm_write_reg16short()
1850 if (rc == 0) { in drxj_dap_rm_write_reg16short()
1852 rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, in drxj_dap_rm_write_reg16short()
1855 if (rc == 0) { in drxj_dap_rm_write_reg16short()
1857 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, in drxj_dap_rm_write_reg16short()
1860 if (rc == 0) { in drxj_dap_rm_write_reg16short()
1862 rc = drxdap_fasi_write_reg16(dev_addr, in drxj_dap_rm_write_reg16short()
1867 return rc; in drxj_dap_rm_write_reg16short()
2108 int rc; in drxj_dap_atomic_read_write_block() local
2145 rc = hi_command(dev_addr, &hi_cmd, &dummy); in drxj_dap_atomic_read_write_block()
2146 if (rc != 0) { in drxj_dap_atomic_read_write_block()
2147 pr_err("error %d\n", rc); in drxj_dap_atomic_read_write_block()
2154 rc = drxj_dap_read_reg16(dev_addr, in drxj_dap_atomic_read_write_block()
2157 if (rc) { in drxj_dap_atomic_read_write_block()
2158 pr_err("error %d\n", rc); in drxj_dap_atomic_read_write_block()
2169 return rc; in drxj_dap_atomic_read_write_block()
2185 int rc; in drxj_dap_atomic_read_reg32() local
2191 rc = drxj_dap_atomic_read_write_block(dev_addr, addr, in drxj_dap_atomic_read_reg32()
2194 if (rc < 0) in drxj_dap_atomic_read_reg32()
2207 return rc; in drxj_dap_atomic_read_reg32()
2238 int rc; in hi_cfg_command() local
2250 rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result); in hi_cfg_command()
2251 if (rc != 0) { in hi_cfg_command()
2252 pr_err("error %d\n", rc); in hi_cfg_command()
2262 return rc; in hi_cfg_command()
2282 int rc; in hi_command() local
2289 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0); in hi_command()
2290 if (rc != 0) { in hi_command()
2291 pr_err("error %d\n", rc); in hi_command()
2294 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0); in hi_command()
2295 if (rc != 0) { in hi_command()
2296 pr_err("error %d\n", rc); in hi_command()
2299 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0); in hi_command()
2300 if (rc != 0) { in hi_command()
2301 pr_err("error %d\n", rc); in hi_command()
2304 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0); in hi_command()
2305 if (rc != 0) { in hi_command()
2306 pr_err("error %d\n", rc); in hi_command()
2311 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0); in hi_command()
2312 if (rc != 0) { in hi_command()
2313 pr_err("error %d\n", rc); in hi_command()
2316 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0); in hi_command()
2317 if (rc != 0) { in hi_command()
2318 pr_err("error %d\n", rc); in hi_command()
2331 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0); in hi_command()
2332 if (rc != 0) { in hi_command()
2333 pr_err("error %d\n", rc); in hi_command()
2350 rc = -ETIMEDOUT; in hi_command()
2355 rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0); in hi_command()
2356 if (rc != 0) { in hi_command()
2357 pr_err("error %d\n", rc); in hi_command()
2363 rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_RES__A, result, 0); in hi_command()
2364 if (rc != 0) { in hi_command()
2365 pr_err("error %d\n", rc); in hi_command()
2373 return rc; in hi_command()
2394 int rc; in init_hi() local
2401 rc = drxj_dap_write_reg16(dev_addr, 0x4301D7, 0x801, 0); in init_hi()
2402 if (rc != 0) { in init_hi()
2403 pr_err("error %d\n", rc); in init_hi()
2435 rc = hi_cfg_command(demod); in init_hi()
2436 if (rc != 0) { in init_hi()
2437 pr_err("error %d\n", rc); in init_hi()
2444 return rc; in init_hi()
2481 int rc; in get_device_capabilities() local
2487 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in get_device_capabilities()
2488 if (rc != 0) { in get_device_capabilities()
2489 pr_err("error %d\n", rc); in get_device_capabilities()
2492 rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0); in get_device_capabilities()
2493 if (rc != 0) { in get_device_capabilities()
2494 pr_err("error %d\n", rc); in get_device_capabilities()
2497 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); in get_device_capabilities()
2498 if (rc != 0) { in get_device_capabilities()
2499 pr_err("error %d\n", rc); in get_device_capabilities()
2527 rc = drxdap_fasi_read_reg32(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0); in get_device_capabilities()
2528 if (rc != 0) { in get_device_capabilities()
2529 pr_err("error %d\n", rc); in get_device_capabilities()
2536 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in get_device_capabilities()
2537 if (rc != 0) { in get_device_capabilities()
2538 pr_err("error %d\n", rc); in get_device_capabilities()
2541 rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0); in get_device_capabilities()
2542 if (rc != 0) { in get_device_capabilities()
2543 pr_err("error %d\n", rc); in get_device_capabilities()
2547 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); in get_device_capabilities()
2548 if (rc != 0) { in get_device_capabilities()
2549 pr_err("error %d\n", rc); in get_device_capabilities()
2660 return rc; in get_device_capabilities()
2733 int rc; in ctrl_set_cfg_mpeg_output() local
2769 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0); in ctrl_set_cfg_mpeg_output()
2770 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2771 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2776 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, 7, 0); in ctrl_set_cfg_mpeg_output()
2777 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2778 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2781 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10, 0); in ctrl_set_cfg_mpeg_output()
2782 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2783 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2786 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10, 0); in ctrl_set_cfg_mpeg_output()
2787 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2788 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2791 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, 5, 0); in ctrl_set_cfg_mpeg_output()
2792 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2793 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2796 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, 7, 0); in ctrl_set_cfg_mpeg_output()
2797 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2798 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2801 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 10, 0); in ctrl_set_cfg_mpeg_output()
2802 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2803 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2807 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 3, 0); in ctrl_set_cfg_mpeg_output()
2808 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2809 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2813 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 5, 0); in ctrl_set_cfg_mpeg_output()
2814 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2815 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2846 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0); in ctrl_set_cfg_mpeg_output()
2847 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2848 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2851 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0); in ctrl_set_cfg_mpeg_output()
2852 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2853 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2856 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5, 0); in ctrl_set_cfg_mpeg_output()
2857 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2858 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2861 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE, 0); in ctrl_set_cfg_mpeg_output()
2862 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2863 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2866 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE, 0); in ctrl_set_cfg_mpeg_output()
2867 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2868 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2872 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 0xD, 0); in ctrl_set_cfg_mpeg_output()
2873 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2874 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2878 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE, 0); in ctrl_set_cfg_mpeg_output()
2879 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2880 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2884 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 2, 0); in ctrl_set_cfg_mpeg_output()
2885 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2886 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2889 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 12, 0); in ctrl_set_cfg_mpeg_output()
2890 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2891 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2900 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0); in ctrl_set_cfg_mpeg_output()
2901 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2902 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2905 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode, 0); in ctrl_set_cfg_mpeg_output()
2906 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2907 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3062 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RAT… in ctrl_set_cfg_mpeg_output()
3063 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3064 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3067 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RAT… in ctrl_set_cfg_mpeg_output()
3068 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3069 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3072 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MO… in ctrl_set_cfg_mpeg_output()
3073 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3074 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3077 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MO… in ctrl_set_cfg_mpeg_output()
3078 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3079 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3082 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len, 0); in ctrl_set_cfg_mpeg_output()
3083 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3084 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3089 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0); in ctrl_set_cfg_mpeg_output()
3090 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3091 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3096 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M, 0); in ctrl_set_cfg_mpeg_output()
3097 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3098 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3101 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, 0, 0); in ctrl_set_cfg_mpeg_output()
3102 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3103 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3108 rc = drxdap_fasi_write_reg32(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate, 0); in ctrl_set_cfg_mpeg_output()
3109 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3110 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3115 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode, 0); in ctrl_set_cfg_mpeg_output()
3116 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3117 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3120 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode, 0); in ctrl_set_cfg_mpeg_output()
3121 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3122 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3125 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert, 0); in ctrl_set_cfg_mpeg_output()
3126 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3127 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3133 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); in ctrl_set_cfg_mpeg_output()
3134 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3135 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3139 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013, 0); in ctrl_set_cfg_mpeg_output()
3140 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3141 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3144 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013, 0); in ctrl_set_cfg_mpeg_output()
3145 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3146 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3149 …rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR… in ctrl_set_cfg_mpeg_output()
3150 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3151 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3154 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013, 0); in ctrl_set_cfg_mpeg_output()
3155 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3156 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3162 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3163 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3164 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3172 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3173 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3174 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3177 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3178 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3179 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3182 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3183 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3184 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3187 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3188 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3189 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3192 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3193 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3194 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3197 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3198 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3199 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3202 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3203 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3204 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3207 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3208 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3209 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3213 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3214 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3215 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3218 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3219 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3220 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3223 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3224 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3225 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3228 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3229 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3230 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3233 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3234 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3235 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3238 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3239 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3240 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3243 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3244 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3245 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3250 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3251 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3252 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3256 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3257 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3258 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3263 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); in ctrl_set_cfg_mpeg_output()
3264 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3265 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3269 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3270 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3271 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3274 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3275 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3276 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3279 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3280 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3281 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3284 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3285 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3286 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3289 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3290 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3291 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3294 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3295 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3296 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3299 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3300 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3301 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3304 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3305 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3306 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3309 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3310 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3311 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3314 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3315 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3316 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3319 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3320 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3321 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3324 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3325 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3326 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3330 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3331 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3332 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3336 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3337 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3338 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3348 return rc; in ctrl_set_cfg_mpeg_output()
3375 int rc; in set_mpegtei_handling() local
3383 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0); in set_mpegtei_handling()
3384 if (rc != 0) { in set_mpegtei_handling()
3385 pr_err("error %d\n", rc); in set_mpegtei_handling()
3388 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0); in set_mpegtei_handling()
3389 if (rc != 0) { in set_mpegtei_handling()
3390 pr_err("error %d\n", rc); in set_mpegtei_handling()
3393 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0); in set_mpegtei_handling()
3394 if (rc != 0) { in set_mpegtei_handling()
3395 pr_err("error %d\n", rc); in set_mpegtei_handling()
3413 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0); in set_mpegtei_handling()
3414 if (rc != 0) { in set_mpegtei_handling()
3415 pr_err("error %d\n", rc); in set_mpegtei_handling()
3418 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0); in set_mpegtei_handling()
3419 if (rc != 0) { in set_mpegtei_handling()
3420 pr_err("error %d\n", rc); in set_mpegtei_handling()
3423 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0); in set_mpegtei_handling()
3424 if (rc != 0) { in set_mpegtei_handling()
3425 pr_err("error %d\n", rc); in set_mpegtei_handling()
3431 return rc; in set_mpegtei_handling()
3448 int rc; in bit_reverse_mpeg_output() local
3454 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0); in bit_reverse_mpeg_output()
3455 if (rc != 0) { in bit_reverse_mpeg_output()
3456 pr_err("error %d\n", rc); in bit_reverse_mpeg_output()
3466 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0); in bit_reverse_mpeg_output()
3467 if (rc != 0) { in bit_reverse_mpeg_output()
3468 pr_err("error %d\n", rc); in bit_reverse_mpeg_output()
3474 return rc; in bit_reverse_mpeg_output()
3492 int rc; in set_mpeg_start_width() local
3501 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0); in set_mpeg_start_width()
3502 if (rc != 0) { in set_mpeg_start_width()
3503 pr_err("error %d\n", rc); in set_mpeg_start_width()
3509 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0); in set_mpeg_start_width()
3510 if (rc != 0) { in set_mpeg_start_width()
3511 pr_err("error %d\n", rc); in set_mpeg_start_width()
3518 return rc; in set_mpeg_start_width()
3538 int rc; in ctrl_set_uio_cfg() local
3546 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in ctrl_set_uio_cfg()
3547 if (rc != 0) { in ctrl_set_uio_cfg()
3548 pr_err("error %d\n", rc); in ctrl_set_uio_cfg()
3566 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3567 if (rc != 0) { in ctrl_set_uio_cfg()
3568 pr_err("error %d\n", rc); in ctrl_set_uio_cfg()
3589 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3590 if (rc != 0) { in ctrl_set_uio_cfg()
3591 pr_err("error %d\n", rc); in ctrl_set_uio_cfg()
3612 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3613 if (rc != 0) { in ctrl_set_uio_cfg()
3614 pr_err("error %d\n", rc); in ctrl_set_uio_cfg()
3633 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3634 if (rc != 0) { in ctrl_set_uio_cfg()
3635 pr_err("error %d\n", rc); in ctrl_set_uio_cfg()
3651 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in ctrl_set_uio_cfg()
3652 if (rc != 0) { in ctrl_set_uio_cfg()
3653 pr_err("error %d\n", rc); in ctrl_set_uio_cfg()
3659 return rc; in ctrl_set_uio_cfg()
3673 int rc; in ctrl_uio_write() local
3683 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in ctrl_uio_write()
3684 if (rc != 0) { in ctrl_uio_write()
3685 pr_err("error %d\n", rc); in ctrl_uio_write()
3705 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3706 if (rc != 0) { in ctrl_uio_write()
3707 pr_err("error %d\n", rc); in ctrl_uio_write()
3712 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); in ctrl_uio_write()
3713 if (rc != 0) { in ctrl_uio_write()
3714 pr_err("error %d\n", rc); in ctrl_uio_write()
3723 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); in ctrl_uio_write()
3724 if (rc != 0) { in ctrl_uio_write()
3725 pr_err("error %d\n", rc); in ctrl_uio_write()
3744 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3745 if (rc != 0) { in ctrl_uio_write()
3746 pr_err("error %d\n", rc); in ctrl_uio_write()
3751 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); in ctrl_uio_write()
3752 if (rc != 0) { in ctrl_uio_write()
3753 pr_err("error %d\n", rc); in ctrl_uio_write()
3762 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); in ctrl_uio_write()
3763 if (rc != 0) { in ctrl_uio_write()
3764 pr_err("error %d\n", rc); in ctrl_uio_write()
3783 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3784 if (rc != 0) { in ctrl_uio_write()
3785 pr_err("error %d\n", rc); in ctrl_uio_write()
3790 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0); in ctrl_uio_write()
3791 if (rc != 0) { in ctrl_uio_write()
3792 pr_err("error %d\n", rc); in ctrl_uio_write()
3801 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0); in ctrl_uio_write()
3802 if (rc != 0) { in ctrl_uio_write()
3803 pr_err("error %d\n", rc); in ctrl_uio_write()
3823 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3824 if (rc != 0) { in ctrl_uio_write()
3825 pr_err("error %d\n", rc); in ctrl_uio_write()
3830 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); in ctrl_uio_write()
3831 if (rc != 0) { in ctrl_uio_write()
3832 pr_err("error %d\n", rc); in ctrl_uio_write()
3841 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); in ctrl_uio_write()
3842 if (rc != 0) { in ctrl_uio_write()
3843 pr_err("error %d\n", rc); in ctrl_uio_write()
3853 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in ctrl_uio_write()
3854 if (rc != 0) { in ctrl_uio_write()
3855 pr_err("error %d\n", rc); in ctrl_uio_write()
3861 return rc; in ctrl_uio_write()
3918 int rc; in smart_ant_init() local
3925 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in smart_ant_init()
3926 if (rc != 0) { in smart_ant_init()
3927 pr_err("error %d\n", rc); in smart_ant_init()
3931 rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0); in smart_ant_init()
3932 if (rc != 0) { in smart_ant_init()
3933 pr_err("error %d\n", rc); in smart_ant_init()
3937 …rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) … in smart_ant_init()
3938 if (rc != 0) { in smart_ant_init()
3939 pr_err("error %d\n", rc); in smart_ant_init()
3943 …rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M… in smart_ant_init()
3944 if (rc != 0) { in smart_ant_init()
3945 pr_err("error %d\n", rc); in smart_ant_init()
3951 rc = ctrl_set_uio_cfg(demod, &uio_cfg); in smart_ant_init()
3952 if (rc != 0) { in smart_ant_init()
3953 pr_err("error %d\n", rc); in smart_ant_init()
3956 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0); in smart_ant_init()
3957 if (rc != 0) { in smart_ant_init()
3958 pr_err("error %d\n", rc); in smart_ant_init()
3961 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0); in smart_ant_init()
3962 if (rc != 0) { in smart_ant_init()
3963 pr_err("error %d\n", rc); in smart_ant_init()
3968 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in smart_ant_init()
3969 if (rc != 0) { in smart_ant_init()
3970 pr_err("error %d\n", rc); in smart_ant_init()
3976 return rc; in smart_ant_init()
3981 int rc; in scu_command() local
3990 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); in scu_command()
3991 if (rc != 0) { in scu_command()
3992 pr_err("error %d\n", rc); in scu_command()
4000 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0); in scu_command()
4001 if (rc != 0) { in scu_command()
4002 pr_err("error %d\n", rc); in scu_command()
4007 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0); in scu_command()
4008 if (rc != 0) { in scu_command()
4009 pr_err("error %d\n", rc); in scu_command()
4014 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0); in scu_command()
4015 if (rc != 0) { in scu_command()
4016 pr_err("error %d\n", rc); in scu_command()
4021 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0); in scu_command()
4022 if (rc != 0) { in scu_command()
4023 pr_err("error %d\n", rc); in scu_command()
4028 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0); in scu_command()
4029 if (rc != 0) { in scu_command()
4030 pr_err("error %d\n", rc); in scu_command()
4041 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0); in scu_command()
4042 if (rc != 0) { in scu_command()
4043 pr_err("error %d\n", rc); in scu_command()
4050 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); in scu_command()
4051 if (rc != 0) { in scu_command()
4052 pr_err("error %d\n", rc); in scu_command()
4069 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0); in scu_command()
4070 if (rc != 0) { in scu_command()
4071 pr_err("error %d\n", rc); in scu_command()
4076 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0); in scu_command()
4077 if (rc != 0) { in scu_command()
4078 pr_err("error %d\n", rc); in scu_command()
4083 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0); in scu_command()
4084 if (rc != 0) { in scu_command()
4085 pr_err("error %d\n", rc); in scu_command()
4090 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0); in scu_command()
4091 if (rc != 0) { in scu_command()
4092 pr_err("error %d\n", rc); in scu_command()
4125 return rc; in scu_command()
4146 int rc; in drxj_dap_scu_atomic_read_write_block() local
4176 rc = scu_command(dev_addr, &scu_cmd); in drxj_dap_scu_atomic_read_write_block()
4177 if (rc != 0) { in drxj_dap_scu_atomic_read_write_block()
4178 pr_err("error %d\n", rc); in drxj_dap_scu_atomic_read_write_block()
4194 return rc; in drxj_dap_scu_atomic_read_write_block()
4210 int rc; in drxj_dap_scu_atomic_read_reg16() local
4216 rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true); in drxj_dap_scu_atomic_read_reg16()
4217 if (rc < 0) in drxj_dap_scu_atomic_read_reg16()
4218 return rc; in drxj_dap_scu_atomic_read_reg16()
4224 return rc; in drxj_dap_scu_atomic_read_reg16()
4238 int rc; in drxj_dap_scu_atomic_write_reg16() local
4243 rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, false); in drxj_dap_scu_atomic_write_reg16()
4245 return rc; in drxj_dap_scu_atomic_write_reg16()
4261 int rc; in adc_sync_measurement() local
4267 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0); in adc_sync_measurement()
4268 if (rc != 0) { in adc_sync_measurement()
4269 pr_err("error %d\n", rc); in adc_sync_measurement()
4272 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_START_LOCK__A, 1, 0); in adc_sync_measurement()
4273 if (rc != 0) { in adc_sync_measurement()
4274 pr_err("error %d\n", rc); in adc_sync_measurement()
4282 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE0__A, &data, 0); in adc_sync_measurement()
4283 if (rc != 0) { in adc_sync_measurement()
4284 pr_err("error %d\n", rc); in adc_sync_measurement()
4289 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE1__A, &data, 0); in adc_sync_measurement()
4290 if (rc != 0) { in adc_sync_measurement()
4291 pr_err("error %d\n", rc); in adc_sync_measurement()
4296 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE2__A, &data, 0); in adc_sync_measurement()
4297 if (rc != 0) { in adc_sync_measurement()
4298 pr_err("error %d\n", rc); in adc_sync_measurement()
4306 return rc; in adc_sync_measurement()
4324 int rc; in adc_synchronization() local
4329 rc = adc_sync_measurement(demod, &count); in adc_synchronization()
4330 if (rc != 0) { in adc_synchronization()
4331 pr_err("error %d\n", rc); in adc_synchronization()
4339 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_CLKNEG__A, &clk_neg, 0); in adc_synchronization()
4340 if (rc != 0) { in adc_synchronization()
4341 pr_err("error %d\n", rc); in adc_synchronization()
4346 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLKNEG__A, clk_neg, 0); in adc_synchronization()
4347 if (rc != 0) { in adc_synchronization()
4348 pr_err("error %d\n", rc); in adc_synchronization()
4352 rc = adc_sync_measurement(demod, &count); in adc_synchronization()
4353 if (rc != 0) { in adc_synchronization()
4354 pr_err("error %d\n", rc); in adc_synchronization()
4365 return rc; in adc_synchronization()
4391 int rc; in init_agc() local
4425 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0); in init_agc()
4426 if (rc != 0) { in init_agc()
4427 pr_err("error %d\n", rc); in init_agc()
4430 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0); in init_agc()
4431 if (rc != 0) { in init_agc()
4432 pr_err("error %d\n", rc); in init_agc()
4435 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0); in init_agc()
4436 if (rc != 0) { in init_agc()
4437 pr_err("error %d\n", rc); in init_agc()
4440 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0); in init_agc()
4441 if (rc != 0) { in init_agc()
4442 pr_err("error %d\n", rc); in init_agc()
4445 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0); in init_agc()
4446 if (rc != 0) { in init_agc()
4447 pr_err("error %d\n", rc); in init_agc()
4450 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0); in init_agc()
4451 if (rc != 0) { in init_agc()
4452 pr_err("error %d\n", rc); in init_agc()
4455 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0); in init_agc()
4456 if (rc != 0) { in init_agc()
4457 pr_err("error %d\n", rc); in init_agc()
4460 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0); in init_agc()
4461 if (rc != 0) { in init_agc()
4462 pr_err("error %d\n", rc); in init_agc()
4465 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0); in init_agc()
4466 if (rc != 0) { in init_agc()
4467 pr_err("error %d\n", rc); in init_agc()
4470 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0); in init_agc()
4471 if (rc != 0) { in init_agc()
4472 pr_err("error %d\n", rc); in init_agc()
4475 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0); in init_agc()
4476 if (rc != 0) { in init_agc()
4477 pr_err("error %d\n", rc); in init_agc()
4480 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0); in init_agc()
4481 if (rc != 0) { in init_agc()
4482 pr_err("error %d\n", rc); in init_agc()
4485 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0); in init_agc()
4486 if (rc != 0) { in init_agc()
4487 pr_err("error %d\n", rc); in init_agc()
4508 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0); in init_agc()
4509 if (rc != 0) { in init_agc()
4510 pr_err("error %d\n", rc); in init_agc()
4513 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0); in init_agc()
4514 if (rc != 0) { in init_agc()
4515 pr_err("error %d\n", rc); in init_agc()
4518 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0); in init_agc()
4519 if (rc != 0) { in init_agc()
4520 pr_err("error %d\n", rc); in init_agc()
4523 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0); in init_agc()
4524 if (rc != 0) { in init_agc()
4525 pr_err("error %d\n", rc); in init_agc()
4528 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0); in init_agc()
4529 if (rc != 0) { in init_agc()
4530 pr_err("error %d\n", rc); in init_agc()
4533 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0); in init_agc()
4534 if (rc != 0) { in init_agc()
4535 pr_err("error %d\n", rc); in init_agc()
4538 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0); in init_agc()
4539 if (rc != 0) { in init_agc()
4540 pr_err("error %d\n", rc); in init_agc()
4543 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0); in init_agc()
4544 if (rc != 0) { in init_agc()
4545 pr_err("error %d\n", rc); in init_agc()
4548 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0); in init_agc()
4549 if (rc != 0) { in init_agc()
4550 pr_err("error %d\n", rc); in init_agc()
4553 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0); in init_agc()
4554 if (rc != 0) { in init_agc()
4555 pr_err("error %d\n", rc); in init_agc()
4560 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); in init_agc()
4561 if (rc != 0) { in init_agc()
4562 pr_err("error %d\n", rc); in init_agc()
4566 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0); in init_agc()
4567 if (rc != 0) { in init_agc()
4568 pr_err("error %d\n", rc); in init_agc()
4572 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0); in init_agc()
4573 if (rc != 0) { in init_agc()
4574 pr_err("error %d\n", rc); in init_agc()
4584 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0); in init_agc()
4585 if (rc != 0) { in init_agc()
4586 pr_err("error %d\n", rc); in init_agc()
4589 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0); in init_agc()
4590 if (rc != 0) { in init_agc()
4591 pr_err("error %d\n", rc); in init_agc()
4594 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0); in init_agc()
4595 if (rc != 0) { in init_agc()
4596 pr_err("error %d\n", rc); in init_agc()
4599 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0); in init_agc()
4600 if (rc != 0) { in init_agc()
4601 pr_err("error %d\n", rc); in init_agc()
4604 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0); in init_agc()
4605 if (rc != 0) { in init_agc()
4606 pr_err("error %d\n", rc); in init_agc()
4609 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0); in init_agc()
4610 if (rc != 0) { in init_agc()
4611 pr_err("error %d\n", rc); in init_agc()
4614 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0); in init_agc()
4615 if (rc != 0) { in init_agc()
4616 pr_err("error %d\n", rc); in init_agc()
4619 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0); in init_agc()
4620 if (rc != 0) { in init_agc()
4621 pr_err("error %d\n", rc); in init_agc()
4624 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0); in init_agc()
4625 if (rc != 0) { in init_agc()
4626 pr_err("error %d\n", rc); in init_agc()
4629 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0); in init_agc()
4630 if (rc != 0) { in init_agc()
4631 pr_err("error %d\n", rc); in init_agc()
4634 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0); in init_agc()
4635 if (rc != 0) { in init_agc()
4636 pr_err("error %d\n", rc); in init_agc()
4639 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0); in init_agc()
4640 if (rc != 0) { in init_agc()
4641 pr_err("error %d\n", rc); in init_agc()
4644 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0); in init_agc()
4645 if (rc != 0) { in init_agc()
4646 pr_err("error %d\n", rc); in init_agc()
4649 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0); in init_agc()
4650 if (rc != 0) { in init_agc()
4651 pr_err("error %d\n", rc); in init_agc()
4654 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0); in init_agc()
4655 if (rc != 0) { in init_agc()
4656 pr_err("error %d\n", rc); in init_agc()
4659 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0); in init_agc()
4660 if (rc != 0) { in init_agc()
4661 pr_err("error %d\n", rc); in init_agc()
4664 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0); in init_agc()
4665 if (rc != 0) { in init_agc()
4666 pr_err("error %d\n", rc); in init_agc()
4669 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0); in init_agc()
4670 if (rc != 0) { in init_agc()
4671 pr_err("error %d\n", rc); in init_agc()
4674 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0); in init_agc()
4675 if (rc != 0) { in init_agc()
4676 pr_err("error %d\n", rc); in init_agc()
4679 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0); in init_agc()
4680 if (rc != 0) { in init_agc()
4681 pr_err("error %d\n", rc); in init_agc()
4684 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0); in init_agc()
4685 if (rc != 0) { in init_agc()
4686 pr_err("error %d\n", rc); in init_agc()
4689 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0); in init_agc()
4690 if (rc != 0) { in init_agc()
4691 pr_err("error %d\n", rc); in init_agc()
4694 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0); in init_agc()
4695 if (rc != 0) { in init_agc()
4696 pr_err("error %d\n", rc); in init_agc()
4699 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0); in init_agc()
4700 if (rc != 0) { in init_agc()
4701 pr_err("error %d\n", rc); in init_agc()
4704 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0); in init_agc()
4705 if (rc != 0) { in init_agc()
4706 pr_err("error %d\n", rc); in init_agc()
4709 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0); in init_agc()
4710 if (rc != 0) { in init_agc()
4711 pr_err("error %d\n", rc); in init_agc()
4723 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0); in init_agc()
4724 if (rc != 0) { in init_agc()
4725 pr_err("error %d\n", rc); in init_agc()
4728 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0); in init_agc()
4729 if (rc != 0) { in init_agc()
4730 pr_err("error %d\n", rc); in init_agc()
4735 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); in init_agc()
4736 if (rc != 0) { in init_agc()
4737 pr_err("error %d\n", rc); in init_agc()
4742 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, data, 0); in init_agc()
4743 if (rc != 0) { in init_agc()
4744 pr_err("error %d\n", rc); in init_agc()
4750 return rc; in init_agc()
4767 int rc; in set_frequency() local
4838 rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0); in set_frequency()
4839 if (rc != 0) { in set_frequency()
4840 pr_err("error %d\n", rc); in set_frequency()
4848 return rc; in set_frequency()
4864 int rc; in get_acc_pkt_err() local
4874 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0); in get_acc_pkt_err()
4875 if (rc != 0) { in get_acc_pkt_err()
4876 pr_err("error %d\n", rc); in get_acc_pkt_err()
4896 return rc; in get_acc_pkt_err()
4917 int rc; in set_agc_rf() local
4945 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); in set_agc_rf()
4946 if (rc != 0) { in set_agc_rf()
4947 pr_err("error %d\n", rc); in set_agc_rf()
4951 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); in set_agc_rf()
4952 if (rc != 0) { in set_agc_rf()
4953 pr_err("error %d\n", rc); in set_agc_rf()
4958 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); in set_agc_rf()
4959 if (rc != 0) { in set_agc_rf()
4960 pr_err("error %d\n", rc); in set_agc_rf()
4975 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); in set_agc_rf()
4976 if (rc != 0) { in set_agc_rf()
4977 pr_err("error %d\n", rc); in set_agc_rf()
4982 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0); in set_agc_rf()
4983 if (rc != 0) { in set_agc_rf()
4984 pr_err("error %d\n", rc); in set_agc_rf()
4988 …rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAG… in set_agc_rf()
4989 if (rc != 0) { in set_agc_rf()
4990 pr_err("error %d\n", rc); in set_agc_rf()
5005 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0); in set_agc_rf()
5006 if (rc != 0) { in set_agc_rf()
5007 pr_err("error %d\n", rc); in set_agc_rf()
5010 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0); in set_agc_rf()
5011 if (rc != 0) { in set_agc_rf()
5012 pr_err("error %d\n", rc); in set_agc_rf()
5018 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0); in set_agc_rf()
5019 if (rc != 0) { in set_agc_rf()
5020 pr_err("error %d\n", rc); in set_agc_rf()
5027 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); in set_agc_rf()
5028 if (rc != 0) { in set_agc_rf()
5029 pr_err("error %d\n", rc); in set_agc_rf()
5033 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); in set_agc_rf()
5034 if (rc != 0) { in set_agc_rf()
5035 pr_err("error %d\n", rc); in set_agc_rf()
5040 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); in set_agc_rf()
5041 if (rc != 0) { in set_agc_rf()
5042 pr_err("error %d\n", rc); in set_agc_rf()
5050 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); in set_agc_rf()
5051 if (rc != 0) { in set_agc_rf()
5052 pr_err("error %d\n", rc); in set_agc_rf()
5057 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0); in set_agc_rf()
5058 if (rc != 0) { in set_agc_rf()
5059 pr_err("error %d\n", rc); in set_agc_rf()
5066 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); in set_agc_rf()
5067 if (rc != 0) { in set_agc_rf()
5068 pr_err("error %d\n", rc); in set_agc_rf()
5072 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); in set_agc_rf()
5073 if (rc != 0) { in set_agc_rf()
5074 pr_err("error %d\n", rc); in set_agc_rf()
5079 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); in set_agc_rf()
5080 if (rc != 0) { in set_agc_rf()
5081 pr_err("error %d\n", rc); in set_agc_rf()
5085 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); in set_agc_rf()
5086 if (rc != 0) { in set_agc_rf()
5087 pr_err("error %d\n", rc); in set_agc_rf()
5114 return rc; in set_agc_rf()
5133 int rc; in set_agc_if() local
5158 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); in set_agc_if()
5159 if (rc != 0) { in set_agc_if()
5160 pr_err("error %d\n", rc); in set_agc_if()
5164 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); in set_agc_if()
5165 if (rc != 0) { in set_agc_if()
5166 pr_err("error %d\n", rc); in set_agc_if()
5171 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); in set_agc_if()
5172 if (rc != 0) { in set_agc_if()
5173 pr_err("error %d\n", rc); in set_agc_if()
5189 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); in set_agc_if()
5190 if (rc != 0) { in set_agc_if()
5191 pr_err("error %d\n", rc); in set_agc_if()
5196 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0); in set_agc_if()
5197 if (rc != 0) { in set_agc_if()
5198 pr_err("error %d\n", rc); in set_agc_if()
5202 …rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IA… in set_agc_if()
5203 if (rc != 0) { in set_agc_if()
5204 pr_err("error %d\n", rc); in set_agc_if()
5219 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0); in set_agc_if()
5220 if (rc != 0) { in set_agc_if()
5221 pr_err("error %d\n", rc); in set_agc_if()
5224 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0); in set_agc_if()
5225 if (rc != 0) { in set_agc_if()
5226 pr_err("error %d\n", rc); in set_agc_if()
5230 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0); in set_agc_if()
5231 if (rc != 0) { in set_agc_if()
5232 pr_err("error %d\n", rc); in set_agc_if()
5235 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0); in set_agc_if()
5236 if (rc != 0) { in set_agc_if()
5237 pr_err("error %d\n", rc); in set_agc_if()
5246 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); in set_agc_if()
5247 if (rc != 0) { in set_agc_if()
5248 pr_err("error %d\n", rc); in set_agc_if()
5252 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); in set_agc_if()
5253 if (rc != 0) { in set_agc_if()
5254 pr_err("error %d\n", rc); in set_agc_if()
5259 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); in set_agc_if()
5260 if (rc != 0) { in set_agc_if()
5261 pr_err("error %d\n", rc); in set_agc_if()
5270 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); in set_agc_if()
5271 if (rc != 0) { in set_agc_if()
5272 pr_err("error %d\n", rc); in set_agc_if()
5277 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0); in set_agc_if()
5278 if (rc != 0) { in set_agc_if()
5279 pr_err("error %d\n", rc); in set_agc_if()
5287 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); in set_agc_if()
5288 if (rc != 0) { in set_agc_if()
5289 pr_err("error %d\n", rc); in set_agc_if()
5293 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); in set_agc_if()
5294 if (rc != 0) { in set_agc_if()
5295 pr_err("error %d\n", rc); in set_agc_if()
5300 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); in set_agc_if()
5301 if (rc != 0) { in set_agc_if()
5302 pr_err("error %d\n", rc); in set_agc_if()
5307 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); in set_agc_if()
5308 if (rc != 0) { in set_agc_if()
5309 pr_err("error %d\n", rc); in set_agc_if()
5318 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0); in set_agc_if()
5319 if (rc != 0) { in set_agc_if()
5320 pr_err("error %d\n", rc); in set_agc_if()
5343 return rc; in set_agc_if()
5357 int rc; in set_iqm_af() local
5362 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); in set_iqm_af()
5363 if (rc != 0) { in set_iqm_af()
5364 pr_err("error %d\n", rc); in set_iqm_af()
5371 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); in set_iqm_af()
5372 if (rc != 0) { in set_iqm_af()
5373 pr_err("error %d\n", rc); in set_iqm_af()
5379 return rc; in set_iqm_af()
5409 int rc; in power_down_vsb() local
5422 rc = scu_command(dev_addr, &cmd_scu); in power_down_vsb()
5423 if (rc != 0) { in power_down_vsb()
5424 pr_err("error %d\n", rc); in power_down_vsb()
5429 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); in power_down_vsb()
5430 if (rc != 0) { in power_down_vsb()
5431 pr_err("error %d\n", rc); in power_down_vsb()
5434 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0); in power_down_vsb()
5435 if (rc != 0) { in power_down_vsb()
5436 pr_err("error %d\n", rc); in power_down_vsb()
5440 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); in power_down_vsb()
5441 if (rc != 0) { in power_down_vsb()
5442 pr_err("error %d\n", rc); in power_down_vsb()
5445 rc = set_iqm_af(demod, false); in power_down_vsb()
5446 if (rc != 0) { in power_down_vsb()
5447 pr_err("error %d\n", rc); in power_down_vsb()
5451 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); in power_down_vsb()
5452 if (rc != 0) { in power_down_vsb()
5453 pr_err("error %d\n", rc); in power_down_vsb()
5456 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); in power_down_vsb()
5457 if (rc != 0) { in power_down_vsb()
5458 pr_err("error %d\n", rc); in power_down_vsb()
5461 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); in power_down_vsb()
5462 if (rc != 0) { in power_down_vsb()
5463 pr_err("error %d\n", rc); in power_down_vsb()
5466 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); in power_down_vsb()
5467 if (rc != 0) { in power_down_vsb()
5468 pr_err("error %d\n", rc); in power_down_vsb()
5471 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); in power_down_vsb()
5472 if (rc != 0) { in power_down_vsb()
5473 pr_err("error %d\n", rc); in power_down_vsb()
5479 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); in power_down_vsb()
5480 if (rc != 0) { in power_down_vsb()
5481 pr_err("error %d\n", rc); in power_down_vsb()
5487 return rc; in power_down_vsb()
5499 int rc; in set_vsb_leak_n_gain() local
5690 …rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_g… in set_vsb_leak_n_gain()
5691 if (rc != 0) { in set_vsb_leak_n_gain()
5692 pr_err("error %d\n", rc); in set_vsb_leak_n_gain()
5695 …rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_… in set_vsb_leak_n_gain()
5696 if (rc != 0) { in set_vsb_leak_n_gain()
5697 pr_err("error %d\n", rc); in set_vsb_leak_n_gain()
5703 return rc; in set_vsb_leak_n_gain()
5716 int rc; in set_vsb() local
5758 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); in set_vsb()
5759 if (rc != 0) { in set_vsb()
5760 pr_err("error %d\n", rc); in set_vsb()
5763 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0); in set_vsb()
5764 if (rc != 0) { in set_vsb()
5765 pr_err("error %d\n", rc); in set_vsb()
5768 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); in set_vsb()
5769 if (rc != 0) { in set_vsb()
5770 pr_err("error %d\n", rc); in set_vsb()
5773 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); in set_vsb()
5774 if (rc != 0) { in set_vsb()
5775 pr_err("error %d\n", rc); in set_vsb()
5778 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); in set_vsb()
5779 if (rc != 0) { in set_vsb()
5780 pr_err("error %d\n", rc); in set_vsb()
5783 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); in set_vsb()
5784 if (rc != 0) { in set_vsb()
5785 pr_err("error %d\n", rc); in set_vsb()
5788 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); in set_vsb()
5789 if (rc != 0) { in set_vsb()
5790 pr_err("error %d\n", rc); in set_vsb()
5801 rc = scu_command(dev_addr, &cmd_scu); in set_vsb()
5802 if (rc != 0) { in set_vsb()
5803 pr_err("error %d\n", rc); in set_vsb()
5807 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0); in set_vsb()
5808 if (rc != 0) { in set_vsb()
5809 pr_err("error %d\n", rc); in set_vsb()
5812 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0); in set_vsb()
5813 if (rc != 0) { in set_vsb()
5814 pr_err("error %d\n", rc); in set_vsb()
5817 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0); in set_vsb()
5818 if (rc != 0) { in set_vsb()
5819 pr_err("error %d\n", rc); in set_vsb()
5823 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0); in set_vsb()
5824 if (rc != 0) { in set_vsb()
5825 pr_err("error %d\n", rc); in set_vsb()
5828 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0); in set_vsb()
5829 if (rc != 0) { in set_vsb()
5830 pr_err("error %d\n", rc); in set_vsb()
5833 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0); in set_vsb()
5834 if (rc != 0) { in set_vsb()
5835 pr_err("error %d\n", rc); in set_vsb()
5839 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0); in set_vsb()
5840 if (rc != 0) { in set_vsb()
5841 pr_err("error %d\n", rc); in set_vsb()
5844 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, 28, 0); in set_vsb()
5845 if (rc != 0) { in set_vsb()
5846 pr_err("error %d\n", rc); in set_vsb()
5849 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, 0, 0); in set_vsb()
5850 if (rc != 0) { in set_vsb()
5851 pr_err("error %d\n", rc); in set_vsb()
5854 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0); in set_vsb()
5855 if (rc != 0) { in set_vsb()
5856 pr_err("error %d\n", rc); in set_vsb()
5859 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0); in set_vsb()
5860 if (rc != 0) { in set_vsb()
5861 pr_err("error %d\n", rc); in set_vsb()
5864 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0); in set_vsb()
5865 if (rc != 0) { in set_vsb()
5866 pr_err("error %d\n", rc); in set_vsb()
5869 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE__A, 1393, 0); in set_vsb()
5870 if (rc != 0) { in set_vsb()
5871 pr_err("error %d\n", rc); in set_vsb()
5874 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0); in set_vsb()
5875 if (rc != 0) { in set_vsb()
5876 pr_err("error %d\n", rc); in set_vsb()
5879 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0); in set_vsb()
5880 if (rc != 0) { in set_vsb()
5881 pr_err("error %d\n", rc); in set_vsb()
5885 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re)… in set_vsb()
5886 if (rc != 0) { in set_vsb()
5887 pr_err("error %d\n", rc); in set_vsb()
5890 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re)… in set_vsb()
5891 if (rc != 0) { in set_vsb()
5892 pr_err("error %d\n", rc); in set_vsb()
5896 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0); in set_vsb()
5897 if (rc != 0) { in set_vsb()
5898 pr_err("error %d\n", rc); in set_vsb()
5901 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0); in set_vsb()
5902 if (rc != 0) { in set_vsb()
5903 pr_err("error %d\n", rc); in set_vsb()
5906 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0); in set_vsb()
5907 if (rc != 0) { in set_vsb()
5908 pr_err("error %d\n", rc); in set_vsb()
5911 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0); in set_vsb()
5912 if (rc != 0) { in set_vsb()
5913 pr_err("error %d\n", rc); in set_vsb()
5916 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0); in set_vsb()
5917 if (rc != 0) { in set_vsb()
5918 pr_err("error %d\n", rc); in set_vsb()
5921 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0); in set_vsb()
5922 if (rc != 0) { in set_vsb()
5923 pr_err("error %d\n", rc); in set_vsb()
5928 rc = drxj_dap_write_reg16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0); in set_vsb()
5929 if (rc != 0) { in set_vsb()
5930 pr_err("error %d\n", rc); in set_vsb()
5935 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0); in set_vsb()
5936 if (rc != 0) { in set_vsb()
5937 pr_err("error %d\n", rc); in set_vsb()
5941 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_E… in set_vsb()
5942 if (rc != 0) { in set_vsb()
5943 pr_err("error %d\n", rc); in set_vsb()
5949 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0); in set_vsb()
5950 if (rc != 0) { in set_vsb()
5951 pr_err("error %d\n", rc); in set_vsb()
5954 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 470, 0); in set_vsb()
5955 if (rc != 0) { in set_vsb()
5956 pr_err("error %d\n", rc); in set_vsb()
5959 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0); in set_vsb()
5960 if (rc != 0) { in set_vsb()
5961 pr_err("error %d\n", rc); in set_vsb()
5964 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0); in set_vsb()
5965 if (rc != 0) { in set_vsb()
5966 pr_err("error %d\n", rc); in set_vsb()
5972 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0); in set_vsb()
5973 if (rc != 0) { in set_vsb()
5974 pr_err("error %d\n", rc); in set_vsb()
5977 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__… in set_vsb()
5978 if (rc != 0) { in set_vsb()
5979 pr_err("error %d\n", rc); in set_vsb()
5984 rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0); in set_vsb()
5985 if (rc != 0) { in set_vsb()
5986 pr_err("error %d\n", rc); in set_vsb()
5989 rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0); in set_vsb()
5990 if (rc != 0) { in set_vsb()
5991 pr_err("error %d\n", rc); in set_vsb()
5994 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MODE__A, 0, 0); in set_vsb()
5995 if (rc != 0) { in set_vsb()
5996 pr_err("error %d\n", rc); in set_vsb()
6000 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0); in set_vsb()
6001 if (rc != 0) { in set_vsb()
6002 pr_err("error %d\n", rc); in set_vsb()
6005 …rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0… in set_vsb()
6006 if (rc != 0) { in set_vsb()
6007 pr_err("error %d\n", rc); in set_vsb()
6012 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0); in set_vsb()
6013 if (rc != 0) { in set_vsb()
6014 pr_err("error %d\n", rc); in set_vsb()
6017 rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0); in set_vsb()
6018 if (rc != 0) { in set_vsb()
6019 pr_err("error %d\n", rc); in set_vsb()
6022 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0); in set_vsb()
6023 if (rc != 0) { in set_vsb()
6024 pr_err("error %d\n", rc); in set_vsb()
6027 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0); in set_vsb()
6028 if (rc != 0) { in set_vsb()
6029 pr_err("error %d\n", rc); in set_vsb()
6033 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0); in set_vsb()
6034 if (rc != 0) { in set_vsb()
6035 pr_err("error %d\n", rc); in set_vsb()
6040 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0); in set_vsb()
6041 if (rc != 0) { in set_vsb()
6042 pr_err("error %d\n", rc); in set_vsb()
6048 rc = set_iqm_af(demod, true); in set_vsb()
6049 if (rc != 0) { in set_vsb()
6050 pr_err("error %d\n", rc); in set_vsb()
6053 rc = adc_synchronization(demod); in set_vsb()
6054 if (rc != 0) { in set_vsb()
6055 pr_err("error %d\n", rc); in set_vsb()
6059 rc = init_agc(demod); in set_vsb()
6060 if (rc != 0) { in set_vsb()
6061 pr_err("error %d\n", rc); in set_vsb()
6064 rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false); in set_vsb()
6065 if (rc != 0) { in set_vsb()
6066 pr_err("error %d\n", rc); in set_vsb()
6069 rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false); in set_vsb()
6070 if (rc != 0) { in set_vsb()
6071 pr_err("error %d\n", rc); in set_vsb()
6080 rc = ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg); in set_vsb()
6081 if (rc != 0) { in set_vsb()
6082 pr_err("error %d\n", rc); in set_vsb()
6086 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg)); in set_vsb()
6087 if (rc != 0) { in set_vsb()
6088 pr_err("error %d\n", rc); in set_vsb()
6093 rc = set_mpegtei_handling(demod); in set_vsb()
6094 if (rc != 0) { in set_vsb()
6095 pr_err("error %d\n", rc); in set_vsb()
6098 rc = bit_reverse_mpeg_output(demod); in set_vsb()
6099 if (rc != 0) { in set_vsb()
6100 pr_err("error %d\n", rc); in set_vsb()
6103 rc = set_mpeg_start_width(demod); in set_vsb()
6104 if (rc != 0) { in set_vsb()
6105 pr_err("error %d\n", rc); in set_vsb()
6116 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); in set_vsb()
6117 if (rc != 0) { in set_vsb()
6118 pr_err("error %d\n", rc); in set_vsb()
6131 rc = scu_command(dev_addr, &cmd_scu); in set_vsb()
6132 if (rc != 0) { in set_vsb()
6133 pr_err("error %d\n", rc); in set_vsb()
6137 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0); in set_vsb()
6138 if (rc != 0) { in set_vsb()
6139 pr_err("error %d\n", rc); in set_vsb()
6142 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0); in set_vsb()
6143 if (rc != 0) { in set_vsb()
6144 pr_err("error %d\n", rc); in set_vsb()
6147 …rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_S… in set_vsb()
6148 if (rc != 0) { in set_vsb()
6149 pr_err("error %d\n", rc); in set_vsb()
6152 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0); in set_vsb()
6153 if (rc != 0) { in set_vsb()
6154 pr_err("error %d\n", rc); in set_vsb()
6157 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0); in set_vsb()
6158 if (rc != 0) { in set_vsb()
6159 pr_err("error %d\n", rc); in set_vsb()
6162 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0); in set_vsb()
6163 if (rc != 0) { in set_vsb()
6164 pr_err("error %d\n", rc); in set_vsb()
6167 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0); in set_vsb()
6168 if (rc != 0) { in set_vsb()
6169 pr_err("error %d\n", rc); in set_vsb()
6172 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0); in set_vsb()
6173 if (rc != 0) { in set_vsb()
6174 pr_err("error %d\n", rc); in set_vsb()
6185 rc = scu_command(dev_addr, &cmd_scu); in set_vsb()
6186 if (rc != 0) { in set_vsb()
6187 pr_err("error %d\n", rc); in set_vsb()
6191 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); in set_vsb()
6192 if (rc != 0) { in set_vsb()
6193 pr_err("error %d\n", rc); in set_vsb()
6196 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0); in set_vsb()
6197 if (rc != 0) { in set_vsb()
6198 pr_err("error %d\n", rc); in set_vsb()
6201 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0); in set_vsb()
6202 if (rc != 0) { in set_vsb()
6203 pr_err("error %d\n", rc); in set_vsb()
6209 return rc; in set_vsb()
6220 int rc; in get_vsb_post_rs_pck_err() local
6227 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0); in get_vsb_post_rs_pck_err()
6228 if (rc != 0) { in get_vsb_post_rs_pck_err()
6229 pr_err("error %d\n", rc); in get_vsb_post_rs_pck_err()
6248 return rc; in get_vsb_post_rs_pck_err()
6259 int rc; in get_vs_bpost_viterbi_ber() local
6266 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0); in get_vs_bpost_viterbi_ber()
6267 if (rc != 0) { in get_vs_bpost_viterbi_ber()
6268 pr_err("error %d\n", rc); in get_vs_bpost_viterbi_ber()
6293 return rc; in get_vs_bpost_viterbi_ber()
6305 int rc; in get_vs_bpre_viterbi_ber() local
6307 rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0); in get_vs_bpre_viterbi_ber()
6308 if (rc != 0) { in get_vs_bpre_viterbi_ber()
6309 pr_err("error %d\n", rc); in get_vs_bpre_viterbi_ber()
6325 int rc; in get_vsbmer() local
6328 rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0); in get_vsbmer()
6329 if (rc != 0) { in get_vsbmer()
6330 pr_err("error %d\n", rc); in get_vsbmer()
6338 return rc; in get_vsbmer()
6367 int rc; in power_down_qam() local
6378 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); in power_down_qam()
6379 if (rc != 0) { in power_down_qam()
6380 pr_err("error %d\n", rc); in power_down_qam()
6383 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0); in power_down_qam()
6384 if (rc != 0) { in power_down_qam()
6385 pr_err("error %d\n", rc); in power_down_qam()
6395 rc = scu_command(dev_addr, &cmd_scu); in power_down_qam()
6396 if (rc != 0) { in power_down_qam()
6397 pr_err("error %d\n", rc); in power_down_qam()
6402 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); in power_down_qam()
6403 if (rc != 0) { in power_down_qam()
6404 pr_err("error %d\n", rc); in power_down_qam()
6407 rc = set_iqm_af(demod, false); in power_down_qam()
6408 if (rc != 0) { in power_down_qam()
6409 pr_err("error %d\n", rc); in power_down_qam()
6413 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); in power_down_qam()
6414 if (rc != 0) { in power_down_qam()
6415 pr_err("error %d\n", rc); in power_down_qam()
6418 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); in power_down_qam()
6419 if (rc != 0) { in power_down_qam()
6420 pr_err("error %d\n", rc); in power_down_qam()
6423 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); in power_down_qam()
6424 if (rc != 0) { in power_down_qam()
6425 pr_err("error %d\n", rc); in power_down_qam()
6428 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); in power_down_qam()
6429 if (rc != 0) { in power_down_qam()
6430 pr_err("error %d\n", rc); in power_down_qam()
6433 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); in power_down_qam()
6434 if (rc != 0) { in power_down_qam()
6435 pr_err("error %d\n", rc); in power_down_qam()
6443 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); in power_down_qam()
6444 if (rc != 0) { in power_down_qam()
6445 pr_err("error %d\n", rc); in power_down_qam()
6451 return rc; in power_down_qam()
6479 int rc; in set_qam_measurement() local
6573 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0); in set_qam_measurement()
6574 if (rc != 0) { in set_qam_measurement()
6575 pr_err("error %d\n", rc); in set_qam_measurement()
6578 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16)fec_rs_period, 0); in set_qam_measurement()
6579 if (rc != 0) { in set_qam_measurement()
6580 pr_err("error %d\n", rc); in set_qam_measurement()
6583 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale, 0); in set_qam_measurement()
6584 if (rc != 0) { in set_qam_measurement()
6585 pr_err("error %d\n", rc); in set_qam_measurement()
6590 rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0); in set_qam_measurement()
6591 if (rc != 0) { in set_qam_measurement()
6592 pr_err("error %d\n", rc); in set_qam_measurement()
6595 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0); in set_qam_measurement()
6596 if (rc != 0) { in set_qam_measurement()
6597 pr_err("error %d\n", rc); in set_qam_measurement()
6600 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0); in set_qam_measurement()
6601 if (rc != 0) { in set_qam_measurement()
6602 pr_err("error %d\n", rc); in set_qam_measurement()
6647 rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, (u16)qam_vd_period, 0); in set_qam_measurement()
6648 if (rc != 0) { in set_qam_measurement()
6649 pr_err("error %d\n", rc); in set_qam_measurement()
6652 rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale, 0); in set_qam_measurement()
6653 if (rc != 0) { in set_qam_measurement()
6654 pr_err("error %d\n", rc); in set_qam_measurement()
6663 return rc; in set_qam_measurement()
6677 int rc; in set_qam16() local
6695 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq… in set_qam16()
6696 if (rc != 0) { in set_qam16()
6697 pr_err("error %d\n", rc); in set_qam16()
6700 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)… in set_qam16()
6701 if (rc != 0) { in set_qam16()
6702 pr_err("error %d\n", rc); in set_qam16()
6706 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140, 0); in set_qam16()
6707 if (rc != 0) { in set_qam16()
6708 pr_err("error %d\n", rc); in set_qam16()
6711 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0); in set_qam16()
6712 if (rc != 0) { in set_qam16()
6713 pr_err("error %d\n", rc); in set_qam16()
6716 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120, 0); in set_qam16()
6717 if (rc != 0) { in set_qam16()
6718 pr_err("error %d\n", rc); in set_qam16()
6721 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230, 0); in set_qam16()
6722 if (rc != 0) { in set_qam16()
6723 pr_err("error %d\n", rc); in set_qam16()
6726 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95, 0); in set_qam16()
6727 if (rc != 0) { in set_qam16()
6728 pr_err("error %d\n", rc); in set_qam16()
6731 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105, 0); in set_qam16()
6732 if (rc != 0) { in set_qam16()
6733 pr_err("error %d\n", rc); in set_qam16()
6737 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); in set_qam16()
6738 if (rc != 0) { in set_qam16()
6739 pr_err("error %d\n", rc); in set_qam16()
6742 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0); in set_qam16()
6743 if (rc != 0) { in set_qam16()
6744 pr_err("error %d\n", rc); in set_qam16()
6747 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); in set_qam16()
6748 if (rc != 0) { in set_qam16()
6749 pr_err("error %d\n", rc); in set_qam16()
6753 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16, 0); in set_qam16()
6754 if (rc != 0) { in set_qam16()
6755 pr_err("error %d\n", rc); in set_qam16()
6758 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220, 0); in set_qam16()
6759 if (rc != 0) { in set_qam16()
6760 pr_err("error %d\n", rc); in set_qam16()
6763 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25, 0); in set_qam16()
6764 if (rc != 0) { in set_qam16()
6765 pr_err("error %d\n", rc); in set_qam16()
6768 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6, 0); in set_qam16()
6769 if (rc != 0) { in set_qam16()
6770 pr_err("error %d\n", rc); in set_qam16()
6773 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0); in set_qam16()
6774 if (rc != 0) { in set_qam16()
6775 pr_err("error %d\n", rc); in set_qam16()
6778 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0); in set_qam16()
6779 if (rc != 0) { in set_qam16()
6780 pr_err("error %d\n", rc); in set_qam16()
6783 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0); in set_qam16()
6784 if (rc != 0) { in set_qam16()
6785 pr_err("error %d\n", rc); in set_qam16()
6789 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); in set_qam16()
6790 if (rc != 0) { in set_qam16()
6791 pr_err("error %d\n", rc); in set_qam16()
6794 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); in set_qam16()
6795 if (rc != 0) { in set_qam16()
6796 pr_err("error %d\n", rc); in set_qam16()
6799 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); in set_qam16()
6800 if (rc != 0) { in set_qam16()
6801 pr_err("error %d\n", rc); in set_qam16()
6804 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0); in set_qam16()
6805 if (rc != 0) { in set_qam16()
6806 pr_err("error %d\n", rc); in set_qam16()
6809 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); in set_qam16()
6810 if (rc != 0) { in set_qam16()
6811 pr_err("error %d\n", rc); in set_qam16()
6814 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); in set_qam16()
6815 if (rc != 0) { in set_qam16()
6816 pr_err("error %d\n", rc); in set_qam16()
6819 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0); in set_qam16()
6820 if (rc != 0) { in set_qam16()
6821 pr_err("error %d\n", rc); in set_qam16()
6824 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0); in set_qam16()
6825 if (rc != 0) { in set_qam16()
6826 pr_err("error %d\n", rc); in set_qam16()
6829 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); in set_qam16()
6830 if (rc != 0) { in set_qam16()
6831 pr_err("error %d\n", rc); in set_qam16()
6834 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); in set_qam16()
6835 if (rc != 0) { in set_qam16()
6836 pr_err("error %d\n", rc); in set_qam16()
6839 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); in set_qam16()
6840 if (rc != 0) { in set_qam16()
6841 pr_err("error %d\n", rc); in set_qam16()
6844 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); in set_qam16()
6845 if (rc != 0) { in set_qam16()
6846 pr_err("error %d\n", rc); in set_qam16()
6849 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); in set_qam16()
6850 if (rc != 0) { in set_qam16()
6851 pr_err("error %d\n", rc); in set_qam16()
6854 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); in set_qam16()
6855 if (rc != 0) { in set_qam16()
6856 pr_err("error %d\n", rc); in set_qam16()
6859 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); in set_qam16()
6860 if (rc != 0) { in set_qam16()
6861 pr_err("error %d\n", rc); in set_qam16()
6864 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); in set_qam16()
6865 if (rc != 0) { in set_qam16()
6866 pr_err("error %d\n", rc); in set_qam16()
6869 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240, 0); in set_qam16()
6870 if (rc != 0) { in set_qam16()
6871 pr_err("error %d\n", rc); in set_qam16()
6874 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); in set_qam16()
6875 if (rc != 0) { in set_qam16()
6876 pr_err("error %d\n", rc); in set_qam16()
6879 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); in set_qam16()
6880 if (rc != 0) { in set_qam16()
6881 pr_err("error %d\n", rc); in set_qam16()
6884 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0); in set_qam16()
6885 if (rc != 0) { in set_qam16()
6886 pr_err("error %d\n", rc); in set_qam16()
6890 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960, 0); in set_qam16()
6891 if (rc != 0) { in set_qam16()
6892 pr_err("error %d\n", rc); in set_qam16()
6898 return rc; in set_qam16()
6912 int rc; in set_qam32() local
6930 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq… in set_qam32()
6931 if (rc != 0) { in set_qam32()
6932 pr_err("error %d\n", rc); in set_qam32()
6935 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)… in set_qam32()
6936 if (rc != 0) { in set_qam32()
6937 pr_err("error %d\n", rc); in set_qam32()
6941 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90, 0); in set_qam32()
6942 if (rc != 0) { in set_qam32()
6943 pr_err("error %d\n", rc); in set_qam32()
6946 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0); in set_qam32()
6947 if (rc != 0) { in set_qam32()
6948 pr_err("error %d\n", rc); in set_qam32()
6951 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); in set_qam32()
6952 if (rc != 0) { in set_qam32()
6953 pr_err("error %d\n", rc); in set_qam32()
6956 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170, 0); in set_qam32()
6957 if (rc != 0) { in set_qam32()
6958 pr_err("error %d\n", rc); in set_qam32()
6961 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); in set_qam32()
6962 if (rc != 0) { in set_qam32()
6963 pr_err("error %d\n", rc); in set_qam32()
6966 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0); in set_qam32()
6967 if (rc != 0) { in set_qam32()
6968 pr_err("error %d\n", rc); in set_qam32()
6972 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); in set_qam32()
6973 if (rc != 0) { in set_qam32()
6974 pr_err("error %d\n", rc); in set_qam32()
6977 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0); in set_qam32()
6978 if (rc != 0) { in set_qam32()
6979 pr_err("error %d\n", rc); in set_qam32()
6982 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); in set_qam32()
6983 if (rc != 0) { in set_qam32()
6984 pr_err("error %d\n", rc); in set_qam32()
6988 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0); in set_qam32()
6989 if (rc != 0) { in set_qam32()
6990 pr_err("error %d\n", rc); in set_qam32()
6993 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140, 0); in set_qam32()
6994 if (rc != 0) { in set_qam32()
6995 pr_err("error %d\n", rc); in set_qam32()
6998 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0); in set_qam32()
6999 if (rc != 0) { in set_qam32()
7000 pr_err("error %d\n", rc); in set_qam32()
7003 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0); in set_qam32()
7004 if (rc != 0) { in set_qam32()
7005 pr_err("error %d\n", rc); in set_qam32()
7008 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0); in set_qam32()
7009 if (rc != 0) { in set_qam32()
7010 pr_err("error %d\n", rc); in set_qam32()
7013 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0); in set_qam32()
7014 if (rc != 0) { in set_qam32()
7015 pr_err("error %d\n", rc); in set_qam32()
7018 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0); in set_qam32()
7019 if (rc != 0) { in set_qam32()
7020 pr_err("error %d\n", rc); in set_qam32()
7024 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); in set_qam32()
7025 if (rc != 0) { in set_qam32()
7026 pr_err("error %d\n", rc); in set_qam32()
7029 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); in set_qam32()
7030 if (rc != 0) { in set_qam32()
7031 pr_err("error %d\n", rc); in set_qam32()
7034 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); in set_qam32()
7035 if (rc != 0) { in set_qam32()
7036 pr_err("error %d\n", rc); in set_qam32()
7039 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0); in set_qam32()
7040 if (rc != 0) { in set_qam32()
7041 pr_err("error %d\n", rc); in set_qam32()
7044 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); in set_qam32()
7045 if (rc != 0) { in set_qam32()
7046 pr_err("error %d\n", rc); in set_qam32()
7049 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); in set_qam32()
7050 if (rc != 0) { in set_qam32()
7051 pr_err("error %d\n", rc); in set_qam32()
7054 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0); in set_qam32()
7055 if (rc != 0) { in set_qam32()
7056 pr_err("error %d\n", rc); in set_qam32()
7059 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0); in set_qam32()
7060 if (rc != 0) { in set_qam32()
7061 pr_err("error %d\n", rc); in set_qam32()
7064 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); in set_qam32()
7065 if (rc != 0) { in set_qam32()
7066 pr_err("error %d\n", rc); in set_qam32()
7069 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); in set_qam32()
7070 if (rc != 0) { in set_qam32()
7071 pr_err("error %d\n", rc); in set_qam32()
7074 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); in set_qam32()
7075 if (rc != 0) { in set_qam32()
7076 pr_err("error %d\n", rc); in set_qam32()
7079 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); in set_qam32()
7080 if (rc != 0) { in set_qam32()
7081 pr_err("error %d\n", rc); in set_qam32()
7084 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); in set_qam32()
7085 if (rc != 0) { in set_qam32()
7086 pr_err("error %d\n", rc); in set_qam32()
7089 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); in set_qam32()
7090 if (rc != 0) { in set_qam32()
7091 pr_err("error %d\n", rc); in set_qam32()
7094 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); in set_qam32()
7095 if (rc != 0) { in set_qam32()
7096 pr_err("error %d\n", rc); in set_qam32()
7099 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); in set_qam32()
7100 if (rc != 0) { in set_qam32()
7101 pr_err("error %d\n", rc); in set_qam32()
7104 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176, 0); in set_qam32()
7105 if (rc != 0) { in set_qam32()
7106 pr_err("error %d\n", rc); in set_qam32()
7109 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); in set_qam32()
7110 if (rc != 0) { in set_qam32()
7111 pr_err("error %d\n", rc); in set_qam32()
7114 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); in set_qam32()
7115 if (rc != 0) { in set_qam32()
7116 pr_err("error %d\n", rc); in set_qam32()
7119 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8, 0); in set_qam32()
7120 if (rc != 0) { in set_qam32()
7121 pr_err("error %d\n", rc); in set_qam32()
7125 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480, 0); in set_qam32()
7126 if (rc != 0) { in set_qam32()
7127 pr_err("error %d\n", rc); in set_qam32()
7133 return rc; in set_qam32()
7147 int rc; in set_qam64() local
7166 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq… in set_qam64()
7167 if (rc != 0) { in set_qam64()
7168 pr_err("error %d\n", rc); in set_qam64()
7171 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)… in set_qam64()
7172 if (rc != 0) { in set_qam64()
7173 pr_err("error %d\n", rc); in set_qam64()
7177 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0); in set_qam64()
7178 if (rc != 0) { in set_qam64()
7179 pr_err("error %d\n", rc); in set_qam64()
7182 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); in set_qam64()
7183 if (rc != 0) { in set_qam64()
7184 pr_err("error %d\n", rc); in set_qam64()
7187 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); in set_qam64()
7188 if (rc != 0) { in set_qam64()
7189 pr_err("error %d\n", rc); in set_qam64()
7192 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0); in set_qam64()
7193 if (rc != 0) { in set_qam64()
7194 pr_err("error %d\n", rc); in set_qam64()
7197 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); in set_qam64()
7198 if (rc != 0) { in set_qam64()
7199 pr_err("error %d\n", rc); in set_qam64()
7202 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0); in set_qam64()
7203 if (rc != 0) { in set_qam64()
7204 pr_err("error %d\n", rc); in set_qam64()
7208 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); in set_qam64()
7209 if (rc != 0) { in set_qam64()
7210 pr_err("error %d\n", rc); in set_qam64()
7213 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0); in set_qam64()
7214 if (rc != 0) { in set_qam64()
7215 pr_err("error %d\n", rc); in set_qam64()
7218 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); in set_qam64()
7219 if (rc != 0) { in set_qam64()
7220 pr_err("error %d\n", rc); in set_qam64()
7224 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0); in set_qam64()
7225 if (rc != 0) { in set_qam64()
7226 pr_err("error %d\n", rc); in set_qam64()
7229 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0); in set_qam64()
7230 if (rc != 0) { in set_qam64()
7231 pr_err("error %d\n", rc); in set_qam64()
7234 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0); in set_qam64()
7235 if (rc != 0) { in set_qam64()
7236 pr_err("error %d\n", rc); in set_qam64()
7239 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0); in set_qam64()
7240 if (rc != 0) { in set_qam64()
7241 pr_err("error %d\n", rc); in set_qam64()
7244 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0); in set_qam64()
7245 if (rc != 0) { in set_qam64()
7246 pr_err("error %d\n", rc); in set_qam64()
7249 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0); in set_qam64()
7250 if (rc != 0) { in set_qam64()
7251 pr_err("error %d\n", rc); in set_qam64()
7254 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0); in set_qam64()
7255 if (rc != 0) { in set_qam64()
7256 pr_err("error %d\n", rc); in set_qam64()
7260 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); in set_qam64()
7261 if (rc != 0) { in set_qam64()
7262 pr_err("error %d\n", rc); in set_qam64()
7265 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); in set_qam64()
7266 if (rc != 0) { in set_qam64()
7267 pr_err("error %d\n", rc); in set_qam64()
7270 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); in set_qam64()
7271 if (rc != 0) { in set_qam64()
7272 pr_err("error %d\n", rc); in set_qam64()
7275 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0); in set_qam64()
7276 if (rc != 0) { in set_qam64()
7277 pr_err("error %d\n", rc); in set_qam64()
7280 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); in set_qam64()
7281 if (rc != 0) { in set_qam64()
7282 pr_err("error %d\n", rc); in set_qam64()
7285 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); in set_qam64()
7286 if (rc != 0) { in set_qam64()
7287 pr_err("error %d\n", rc); in set_qam64()
7290 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0); in set_qam64()
7291 if (rc != 0) { in set_qam64()
7292 pr_err("error %d\n", rc); in set_qam64()
7295 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); in set_qam64()
7296 if (rc != 0) { in set_qam64()
7297 pr_err("error %d\n", rc); in set_qam64()
7300 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); in set_qam64()
7301 if (rc != 0) { in set_qam64()
7302 pr_err("error %d\n", rc); in set_qam64()
7305 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); in set_qam64()
7306 if (rc != 0) { in set_qam64()
7307 pr_err("error %d\n", rc); in set_qam64()
7310 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); in set_qam64()
7311 if (rc != 0) { in set_qam64()
7312 pr_err("error %d\n", rc); in set_qam64()
7315 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); in set_qam64()
7316 if (rc != 0) { in set_qam64()
7317 pr_err("error %d\n", rc); in set_qam64()
7320 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); in set_qam64()
7321 if (rc != 0) { in set_qam64()
7322 pr_err("error %d\n", rc); in set_qam64()
7325 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); in set_qam64()
7326 if (rc != 0) { in set_qam64()
7327 pr_err("error %d\n", rc); in set_qam64()
7330 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); in set_qam64()
7331 if (rc != 0) { in set_qam64()
7332 pr_err("error %d\n", rc); in set_qam64()
7335 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0); in set_qam64()
7336 if (rc != 0) { in set_qam64()
7337 pr_err("error %d\n", rc); in set_qam64()
7340 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0); in set_qam64()
7341 if (rc != 0) { in set_qam64()
7342 pr_err("error %d\n", rc); in set_qam64()
7345 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); in set_qam64()
7346 if (rc != 0) { in set_qam64()
7347 pr_err("error %d\n", rc); in set_qam64()
7350 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); in set_qam64()
7351 if (rc != 0) { in set_qam64()
7352 pr_err("error %d\n", rc); in set_qam64()
7355 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0); in set_qam64()
7356 if (rc != 0) { in set_qam64()
7357 pr_err("error %d\n", rc); in set_qam64()
7361 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0); in set_qam64()
7362 if (rc != 0) { in set_qam64()
7363 pr_err("error %d\n", rc); in set_qam64()
7369 return rc; in set_qam64()
7383 int rc; in set_qam128() local
7401 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq… in set_qam128()
7402 if (rc != 0) { in set_qam128()
7403 pr_err("error %d\n", rc); in set_qam128()
7406 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)… in set_qam128()
7407 if (rc != 0) { in set_qam128()
7408 pr_err("error %d\n", rc); in set_qam128()
7412 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0); in set_qam128()
7413 if (rc != 0) { in set_qam128()
7414 pr_err("error %d\n", rc); in set_qam128()
7417 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); in set_qam128()
7418 if (rc != 0) { in set_qam128()
7419 pr_err("error %d\n", rc); in set_qam128()
7422 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); in set_qam128()
7423 if (rc != 0) { in set_qam128()
7424 pr_err("error %d\n", rc); in set_qam128()
7427 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140, 0); in set_qam128()
7428 if (rc != 0) { in set_qam128()
7429 pr_err("error %d\n", rc); in set_qam128()
7432 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); in set_qam128()
7433 if (rc != 0) { in set_qam128()
7434 pr_err("error %d\n", rc); in set_qam128()
7437 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0); in set_qam128()
7438 if (rc != 0) { in set_qam128()
7439 pr_err("error %d\n", rc); in set_qam128()
7443 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); in set_qam128()
7444 if (rc != 0) { in set_qam128()
7445 pr_err("error %d\n", rc); in set_qam128()
7448 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0); in set_qam128()
7449 if (rc != 0) { in set_qam128()
7450 pr_err("error %d\n", rc); in set_qam128()
7453 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); in set_qam128()
7454 if (rc != 0) { in set_qam128()
7455 pr_err("error %d\n", rc); in set_qam128()
7459 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0); in set_qam128()
7460 if (rc != 0) { in set_qam128()
7461 pr_err("error %d\n", rc); in set_qam128()
7464 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65, 0); in set_qam128()
7465 if (rc != 0) { in set_qam128()
7466 pr_err("error %d\n", rc); in set_qam128()
7469 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5, 0); in set_qam128()
7470 if (rc != 0) { in set_qam128()
7471 pr_err("error %d\n", rc); in set_qam128()
7474 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3, 0); in set_qam128()
7475 if (rc != 0) { in set_qam128()
7476 pr_err("error %d\n", rc); in set_qam128()
7479 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0); in set_qam128()
7480 if (rc != 0) { in set_qam128()
7481 pr_err("error %d\n", rc); in set_qam128()
7484 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12, 0); in set_qam128()
7485 if (rc != 0) { in set_qam128()
7486 pr_err("error %d\n", rc); in set_qam128()
7489 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0); in set_qam128()
7490 if (rc != 0) { in set_qam128()
7491 pr_err("error %d\n", rc); in set_qam128()
7495 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); in set_qam128()
7496 if (rc != 0) { in set_qam128()
7497 pr_err("error %d\n", rc); in set_qam128()
7500 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); in set_qam128()
7501 if (rc != 0) { in set_qam128()
7502 pr_err("error %d\n", rc); in set_qam128()
7505 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); in set_qam128()
7506 if (rc != 0) { in set_qam128()
7507 pr_err("error %d\n", rc); in set_qam128()
7510 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40, 0); in set_qam128()
7511 if (rc != 0) { in set_qam128()
7512 pr_err("error %d\n", rc); in set_qam128()
7515 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); in set_qam128()
7516 if (rc != 0) { in set_qam128()
7517 pr_err("error %d\n", rc); in set_qam128()
7520 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); in set_qam128()
7521 if (rc != 0) { in set_qam128()
7522 pr_err("error %d\n", rc); in set_qam128()
7525 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20, 0); in set_qam128()
7526 if (rc != 0) { in set_qam128()
7527 pr_err("error %d\n", rc); in set_qam128()
7530 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); in set_qam128()
7531 if (rc != 0) { in set_qam128()
7532 pr_err("error %d\n", rc); in set_qam128()
7535 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); in set_qam128()
7536 if (rc != 0) { in set_qam128()
7537 pr_err("error %d\n", rc); in set_qam128()
7540 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); in set_qam128()
7541 if (rc != 0) { in set_qam128()
7542 pr_err("error %d\n", rc); in set_qam128()
7545 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); in set_qam128()
7546 if (rc != 0) { in set_qam128()
7547 pr_err("error %d\n", rc); in set_qam128()
7550 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); in set_qam128()
7551 if (rc != 0) { in set_qam128()
7552 pr_err("error %d\n", rc); in set_qam128()
7555 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); in set_qam128()
7556 if (rc != 0) { in set_qam128()
7557 pr_err("error %d\n", rc); in set_qam128()
7560 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); in set_qam128()
7561 if (rc != 0) { in set_qam128()
7562 pr_err("error %d\n", rc); in set_qam128()
7565 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); in set_qam128()
7566 if (rc != 0) { in set_qam128()
7567 pr_err("error %d\n", rc); in set_qam128()
7570 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); in set_qam128()
7571 if (rc != 0) { in set_qam128()
7572 pr_err("error %d\n", rc); in set_qam128()
7575 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144, 0); in set_qam128()
7576 if (rc != 0) { in set_qam128()
7577 pr_err("error %d\n", rc); in set_qam128()
7580 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); in set_qam128()
7581 if (rc != 0) { in set_qam128()
7582 pr_err("error %d\n", rc); in set_qam128()
7585 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); in set_qam128()
7586 if (rc != 0) { in set_qam128()
7587 pr_err("error %d\n", rc); in set_qam128()
7590 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0); in set_qam128()
7591 if (rc != 0) { in set_qam128()
7592 pr_err("error %d\n", rc); in set_qam128()
7596 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992, 0); in set_qam128()
7597 if (rc != 0) { in set_qam128()
7598 pr_err("error %d\n", rc); in set_qam128()
7604 return rc; in set_qam128()
7618 int rc; in set_qam256() local
7636 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq… in set_qam256()
7637 if (rc != 0) { in set_qam256()
7638 pr_err("error %d\n", rc); in set_qam256()
7641 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)… in set_qam256()
7642 if (rc != 0) { in set_qam256()
7643 pr_err("error %d\n", rc); in set_qam256()
7647 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0); in set_qam256()
7648 if (rc != 0) { in set_qam256()
7649 pr_err("error %d\n", rc); in set_qam256()
7652 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); in set_qam256()
7653 if (rc != 0) { in set_qam256()
7654 pr_err("error %d\n", rc); in set_qam256()
7657 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); in set_qam256()
7658 if (rc != 0) { in set_qam256()
7659 pr_err("error %d\n", rc); in set_qam256()
7662 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150, 0); in set_qam256()
7663 if (rc != 0) { in set_qam256()
7664 pr_err("error %d\n", rc); in set_qam256()
7667 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); in set_qam256()
7668 if (rc != 0) { in set_qam256()
7669 pr_err("error %d\n", rc); in set_qam256()
7672 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110, 0); in set_qam256()
7673 if (rc != 0) { in set_qam256()
7674 pr_err("error %d\n", rc); in set_qam256()
7678 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); in set_qam256()
7679 if (rc != 0) { in set_qam256()
7680 pr_err("error %d\n", rc); in set_qam256()
7683 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16, 0); in set_qam256()
7684 if (rc != 0) { in set_qam256()
7685 pr_err("error %d\n", rc); in set_qam256()
7688 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); in set_qam256()
7689 if (rc != 0) { in set_qam256()
7690 pr_err("error %d\n", rc); in set_qam256()
7694 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0); in set_qam256()
7695 if (rc != 0) { in set_qam256()
7696 pr_err("error %d\n", rc); in set_qam256()
7699 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74, 0); in set_qam256()
7700 if (rc != 0) { in set_qam256()
7701 pr_err("error %d\n", rc); in set_qam256()
7704 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18, 0); in set_qam256()
7705 if (rc != 0) { in set_qam256()
7706 pr_err("error %d\n", rc); in set_qam256()
7709 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13, 0); in set_qam256()
7710 if (rc != 0) { in set_qam256()
7711 pr_err("error %d\n", rc); in set_qam256()
7714 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7, 0); in set_qam256()
7715 if (rc != 0) { in set_qam256()
7716 pr_err("error %d\n", rc); in set_qam256()
7719 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0, 0); in set_qam256()
7720 if (rc != 0) { in set_qam256()
7721 pr_err("error %d\n", rc); in set_qam256()
7724 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0); in set_qam256()
7725 if (rc != 0) { in set_qam256()
7726 pr_err("error %d\n", rc); in set_qam256()
7730 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); in set_qam256()
7731 if (rc != 0) { in set_qam256()
7732 pr_err("error %d\n", rc); in set_qam256()
7735 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); in set_qam256()
7736 if (rc != 0) { in set_qam256()
7737 pr_err("error %d\n", rc); in set_qam256()
7740 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); in set_qam256()
7741 if (rc != 0) { in set_qam256()
7742 pr_err("error %d\n", rc); in set_qam256()
7745 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50, 0); in set_qam256()
7746 if (rc != 0) { in set_qam256()
7747 pr_err("error %d\n", rc); in set_qam256()
7750 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); in set_qam256()
7751 if (rc != 0) { in set_qam256()
7752 pr_err("error %d\n", rc); in set_qam256()
7755 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); in set_qam256()
7756 if (rc != 0) { in set_qam256()
7757 pr_err("error %d\n", rc); in set_qam256()
7760 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25, 0); in set_qam256()
7761 if (rc != 0) { in set_qam256()
7762 pr_err("error %d\n", rc); in set_qam256()
7765 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); in set_qam256()
7766 if (rc != 0) { in set_qam256()
7767 pr_err("error %d\n", rc); in set_qam256()
7770 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); in set_qam256()
7771 if (rc != 0) { in set_qam256()
7772 pr_err("error %d\n", rc); in set_qam256()
7775 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); in set_qam256()
7776 if (rc != 0) { in set_qam256()
7777 pr_err("error %d\n", rc); in set_qam256()
7780 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); in set_qam256()
7781 if (rc != 0) { in set_qam256()
7782 pr_err("error %d\n", rc); in set_qam256()
7785 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); in set_qam256()
7786 if (rc != 0) { in set_qam256()
7787 pr_err("error %d\n", rc); in set_qam256()
7790 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); in set_qam256()
7791 if (rc != 0) { in set_qam256()
7792 pr_err("error %d\n", rc); in set_qam256()
7795 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); in set_qam256()
7796 if (rc != 0) { in set_qam256()
7797 pr_err("error %d\n", rc); in set_qam256()
7800 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); in set_qam256()
7801 if (rc != 0) { in set_qam256()
7802 pr_err("error %d\n", rc); in set_qam256()
7805 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0); in set_qam256()
7806 if (rc != 0) { in set_qam256()
7807 pr_err("error %d\n", rc); in set_qam256()
7810 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80, 0); in set_qam256()
7811 if (rc != 0) { in set_qam256()
7812 pr_err("error %d\n", rc); in set_qam256()
7815 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); in set_qam256()
7816 if (rc != 0) { in set_qam256()
7817 pr_err("error %d\n", rc); in set_qam256()
7820 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); in set_qam256()
7821 if (rc != 0) { in set_qam256()
7822 pr_err("error %d\n", rc); in set_qam256()
7825 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0); in set_qam256()
7826 if (rc != 0) { in set_qam256()
7827 pr_err("error %d\n", rc); in set_qam256()
7831 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520, 0); in set_qam256()
7832 if (rc != 0) { in set_qam256()
7833 pr_err("error %d\n", rc); in set_qam256()
7839 return rc; in set_qam256()
7861 int rc; in set_qam() local
8065 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); in set_qam()
8066 if (rc != 0) { in set_qam()
8067 pr_err("error %d\n", rc); in set_qam()
8070 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0); in set_qam()
8071 if (rc != 0) { in set_qam()
8072 pr_err("error %d\n", rc); in set_qam()
8075 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); in set_qam()
8076 if (rc != 0) { in set_qam()
8077 pr_err("error %d\n", rc); in set_qam()
8080 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); in set_qam()
8081 if (rc != 0) { in set_qam()
8082 pr_err("error %d\n", rc); in set_qam()
8085 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); in set_qam()
8086 if (rc != 0) { in set_qam()
8087 pr_err("error %d\n", rc); in set_qam()
8090 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); in set_qam()
8091 if (rc != 0) { in set_qam()
8092 pr_err("error %d\n", rc); in set_qam()
8095 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); in set_qam()
8096 if (rc != 0) { in set_qam()
8097 pr_err("error %d\n", rc); in set_qam()
8107 rc = scu_command(dev_addr, &cmd_scu); in set_qam()
8108 if (rc != 0) { in set_qam()
8109 pr_err("error %d\n", rc); in set_qam()
8126 rc = scu_command(dev_addr, &cmd_scu); in set_qam()
8127 if (rc != 0) { in set_qam()
8128 pr_err("error %d\n", rc); in set_qam()
8138 rc = scu_command(dev_addr, &cmd_scu); in set_qam()
8139 if (rc != 0) { in set_qam()
8140 pr_err("error %d\n", rc); in set_qam()
8144 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate, 0); in set_qam()
8145 if (rc != 0) { in set_qam()
8146 pr_err("error %d\n", rc); in set_qam()
8150 rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate); in set_qam()
8151 if (rc != 0) { in set_qam()
8152 pr_err("error %d\n", rc); in set_qam()
8161 rc = set_frequency(demod, channel, tuner_freq_offset); in set_qam()
8162 if (rc != 0) { in set_qam()
8163 pr_err("error %d\n", rc); in set_qam()
8170 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq, 0); in set_qam()
8171 if (rc != 0) { in set_qam()
8172 pr_err("error %d\n", rc); in set_qam()
8175 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch, 0); in set_qam()
8176 if (rc != 0) { in set_qam()
8177 pr_err("error %d\n", rc); in set_qam()
8184 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0); in set_qam()
8185 if (rc != 0) { in set_qam()
8186 pr_err("error %d\n", rc); in set_qam()
8190 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0); in set_qam()
8191 if (rc != 0) { in set_qam()
8192 pr_err("error %d\n", rc); in set_qam()
8195 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0); in set_qam()
8196 if (rc != 0) { in set_qam()
8197 pr_err("error %d\n", rc); in set_qam()
8200 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M, 0); in set_qam()
8201 if (rc != 0) { in set_qam()
8202 pr_err("error %d\n", rc); in set_qam()
8206 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f, 0); in set_qam()
8207 if (rc != 0) { in set_qam()
8208 pr_err("error %d\n", rc); in set_qam()
8212 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SYNC_SEL__A, 3, 0); in set_qam()
8213 if (rc != 0) { in set_qam()
8214 pr_err("error %d\n", rc); in set_qam()
8217 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0); in set_qam()
8218 if (rc != 0) { in set_qam()
8219 pr_err("error %d\n", rc); in set_qam()
8222 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 448, 0); in set_qam()
8223 if (rc != 0) { in set_qam()
8224 pr_err("error %d\n", rc); in set_qam()
8227 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0); in set_qam()
8228 if (rc != 0) { in set_qam()
8229 pr_err("error %d\n", rc); in set_qam()
8232 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, 4, 0); in set_qam()
8233 if (rc != 0) { in set_qam()
8234 pr_err("error %d\n", rc); in set_qam()
8237 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, 0x10, 0); in set_qam()
8238 if (rc != 0) { in set_qam()
8239 pr_err("error %d\n", rc); in set_qam()
8242 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, 11, 0); in set_qam()
8243 if (rc != 0) { in set_qam()
8244 pr_err("error %d\n", rc); in set_qam()
8248 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0); in set_qam()
8249 if (rc != 0) { in set_qam()
8250 pr_err("error %d\n", rc); in set_qam()
8253 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE, 0); in set_qam()
8254 if (rc != 0) { in set_qam()
8255 pr_err("error %d\n", rc); in set_qam()
8259 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE, 0); in set_qam()
8260 if (rc != 0) { in set_qam()
8261 pr_err("error %d\n", rc); in set_qam()
8265 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE, 0); in set_qam()
8266 if (rc != 0) { in set_qam()
8267 pr_err("error %d\n", rc); in set_qam()
8270 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE, 0); in set_qam()
8271 if (rc != 0) { in set_qam()
8272 pr_err("error %d\n", rc); in set_qam()
8275 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0); in set_qam()
8276 if (rc != 0) { in set_qam()
8277 pr_err("error %d\n", rc); in set_qam()
8285 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0); in set_qam()
8286 if (rc != 0) { in set_qam()
8287 pr_err("error %d\n", rc); in set_qam()
8290 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x04, 0); in set_qam()
8291 if (rc != 0) { in set_qam()
8292 pr_err("error %d\n", rc); in set_qam()
8295 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0); in set_qam()
8296 if (rc != 0) { in set_qam()
8297 pr_err("error %d\n", rc); in set_qam()
8303 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0); in set_qam()
8304 if (rc != 0) { in set_qam()
8305 pr_err("error %d\n", rc); in set_qam()
8308 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x05, 0); in set_qam()
8309 if (rc != 0) { in set_qam()
8310 pr_err("error %d\n", rc); in set_qam()
8313 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, 0x06, 0); in set_qam()
8314 if (rc != 0) { in set_qam()
8315 pr_err("error %d\n", rc); in set_qam()
8324 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE, 0); in set_qam()
8325 if (rc != 0) { in set_qam()
8326 pr_err("error %d\n", rc); in set_qam()
8329 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_RATE_LIMIT__A, 3, 0); in set_qam()
8330 if (rc != 0) { in set_qam()
8331 pr_err("error %d\n", rc); in set_qam()
8334 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORP__A, 4, 0); in set_qam()
8335 if (rc != 0) { in set_qam()
8336 pr_err("error %d\n", rc); in set_qam()
8339 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORI__A, 4, 0); in set_qam()
8340 if (rc != 0) { in set_qam()
8341 pr_err("error %d\n", rc); in set_qam()
8344 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, 7, 0); in set_qam()
8345 if (rc != 0) { in set_qam()
8346 pr_err("error %d\n", rc); in set_qam()
8349 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB0__A, 1, 0); in set_qam()
8350 if (rc != 0) { in set_qam()
8351 pr_err("error %d\n", rc); in set_qam()
8354 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB1__A, 1, 0); in set_qam()
8355 if (rc != 0) { in set_qam()
8356 pr_err("error %d\n", rc); in set_qam()
8359 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB2__A, 1, 0); in set_qam()
8360 if (rc != 0) { in set_qam()
8361 pr_err("error %d\n", rc); in set_qam()
8364 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB3__A, 1, 0); in set_qam()
8365 if (rc != 0) { in set_qam()
8366 pr_err("error %d\n", rc); in set_qam()
8369 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB4__A, 2, 0); in set_qam()
8370 if (rc != 0) { in set_qam()
8371 pr_err("error %d\n", rc); in set_qam()
8374 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB5__A, 2, 0); in set_qam()
8375 if (rc != 0) { in set_qam()
8376 pr_err("error %d\n", rc); in set_qam()
8379 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB6__A, 2, 0); in set_qam()
8380 if (rc != 0) { in set_qam()
8381 pr_err("error %d\n", rc); in set_qam()
8384 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB8__A, 2, 0); in set_qam()
8385 if (rc != 0) { in set_qam()
8386 pr_err("error %d\n", rc); in set_qam()
8389 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB9__A, 2, 0); in set_qam()
8390 if (rc != 0) { in set_qam()
8391 pr_err("error %d\n", rc); in set_qam()
8394 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB10__A, 2, 0); in set_qam()
8395 if (rc != 0) { in set_qam()
8396 pr_err("error %d\n", rc); in set_qam()
8399 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB12__A, 2, 0); in set_qam()
8400 if (rc != 0) { in set_qam()
8401 pr_err("error %d\n", rc); in set_qam()
8404 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB15__A, 3, 0); in set_qam()
8405 if (rc != 0) { in set_qam()
8406 pr_err("error %d\n", rc); in set_qam()
8409 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB16__A, 3, 0); in set_qam()
8410 if (rc != 0) { in set_qam()
8411 pr_err("error %d\n", rc); in set_qam()
8414 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB20__A, 4, 0); in set_qam()
8415 if (rc != 0) { in set_qam()
8416 pr_err("error %d\n", rc); in set_qam()
8419 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB25__A, 4, 0); in set_qam()
8420 if (rc != 0) { in set_qam()
8421 pr_err("error %d\n", rc); in set_qam()
8425 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, 1, 0); in set_qam()
8426 if (rc != 0) { in set_qam()
8427 pr_err("error %d\n", rc); in set_qam()
8430 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, 1, 0); in set_qam()
8431 if (rc != 0) { in set_qam()
8432 pr_err("error %d\n", rc); in set_qam()
8435 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_ADJ_SEL__A, 1, 0); in set_qam()
8436 if (rc != 0) { in set_qam()
8437 pr_err("error %d\n", rc); in set_qam()
8440 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0, 0); in set_qam()
8441 if (rc != 0) { in set_qam()
8442 pr_err("error %d\n", rc); in set_qam()
8445 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0); in set_qam()
8446 if (rc != 0) { in set_qam()
8447 pr_err("error %d\n", rc); in set_qam()
8454 rc = set_iqm_af(demod, true); in set_qam()
8455 if (rc != 0) { in set_qam()
8456 pr_err("error %d\n", rc); in set_qam()
8459 rc = adc_synchronization(demod); in set_qam()
8460 if (rc != 0) { in set_qam()
8461 pr_err("error %d\n", rc); in set_qam()
8465 rc = init_agc(demod); in set_qam()
8466 if (rc != 0) { in set_qam()
8467 pr_err("error %d\n", rc); in set_qam()
8470 rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false); in set_qam()
8471 if (rc != 0) { in set_qam()
8472 pr_err("error %d\n", rc); in set_qam()
8475 rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false); in set_qam()
8476 if (rc != 0) { in set_qam()
8477 pr_err("error %d\n", rc); in set_qam()
8486 rc = ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg); in set_qam()
8487 if (rc != 0) { in set_qam()
8488 pr_err("error %d\n", rc); in set_qam()
8492 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg)); in set_qam()
8493 if (rc != 0) { in set_qam()
8494 pr_err("error %d\n", rc); in set_qam()
8501 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), … in set_qam()
8502 if (rc != 0) { in set_qam()
8503 pr_err("error %d\n", rc); in set_qam()
8506 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), … in set_qam()
8507 if (rc != 0) { in set_qam()
8508 pr_err("error %d\n", rc); in set_qam()
8514 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_tap… in set_qam()
8515 if (rc != 0) { in set_qam()
8516 pr_err("error %d\n", rc); in set_qam()
8519 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_tap… in set_qam()
8520 if (rc != 0) { in set_qam()
8521 pr_err("error %d\n", rc); in set_qam()
8526 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_t… in set_qam()
8527 if (rc != 0) { in set_qam()
8528 pr_err("error %d\n", rc); in set_qam()
8531 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_t… in set_qam()
8532 if (rc != 0) { in set_qam()
8533 pr_err("error %d\n", rc); in set_qam()
8541 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), … in set_qam()
8542 if (rc != 0) { in set_qam()
8543 pr_err("error %d\n", rc); in set_qam()
8546 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), … in set_qam()
8547 if (rc != 0) { in set_qam()
8548 pr_err("error %d\n", rc); in set_qam()
8556 rc = set_qam16(demod); in set_qam()
8557 if (rc != 0) { in set_qam()
8558 pr_err("error %d\n", rc); in set_qam()
8563 rc = set_qam32(demod); in set_qam()
8564 if (rc != 0) { in set_qam()
8565 pr_err("error %d\n", rc); in set_qam()
8570 rc = set_qam64(demod); in set_qam()
8571 if (rc != 0) { in set_qam()
8572 pr_err("error %d\n", rc); in set_qam()
8577 rc = set_qam128(demod); in set_qam()
8578 if (rc != 0) { in set_qam()
8579 pr_err("error %d\n", rc); in set_qam()
8584 rc = set_qam256(demod); in set_qam()
8585 if (rc != 0) { in set_qam()
8586 pr_err("error %d\n", rc); in set_qam()
8596 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0); in set_qam()
8597 if (rc != 0) { in set_qam()
8598 pr_err("error %d\n", rc); in set_qam()
8603 rc = set_mpegtei_handling(demod); in set_qam()
8604 if (rc != 0) { in set_qam()
8605 pr_err("error %d\n", rc); in set_qam()
8608 rc = bit_reverse_mpeg_output(demod); in set_qam()
8609 if (rc != 0) { in set_qam()
8610 pr_err("error %d\n", rc); in set_qam()
8613 rc = set_mpeg_start_width(demod); in set_qam()
8614 if (rc != 0) { in set_qam()
8615 pr_err("error %d\n", rc); in set_qam()
8626 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); in set_qam()
8627 if (rc != 0) { in set_qam()
8628 pr_err("error %d\n", rc); in set_qam()
8643 rc = scu_command(dev_addr, &cmd_scu); in set_qam()
8644 if (rc != 0) { in set_qam()
8645 pr_err("error %d\n", rc); in set_qam()
8650 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); in set_qam()
8651 if (rc != 0) { in set_qam()
8652 pr_err("error %d\n", rc); in set_qam()
8655 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE, 0); in set_qam()
8656 if (rc != 0) { in set_qam()
8657 pr_err("error %d\n", rc); in set_qam()
8660 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0); in set_qam()
8661 if (rc != 0) { in set_qam()
8662 pr_err("error %d\n", rc); in set_qam()
8668 return rc; in set_qam()
8678 int rc; in qam_flip_spec() local
8689 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0); in qam_flip_spec()
8690 if (rc != 0) { in qam_flip_spec()
8691 pr_err("error %d\n", rc); in qam_flip_spec()
8694 …rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_AC… in qam_flip_spec()
8695 if (rc != 0) { in qam_flip_spec()
8696 pr_err("error %d\n", rc); in qam_flip_spec()
8701 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF__A, 0, 0); in qam_flip_spec()
8702 if (rc != 0) { in qam_flip_spec()
8703 pr_err("error %d\n", rc); in qam_flip_spec()
8706 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF1__A, 0, 0); in qam_flip_spec()
8707 if (rc != 0) { in qam_flip_spec()
8708 pr_err("error %d\n", rc); in qam_flip_spec()
8712 rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs, 0); in qam_flip_spec()
8713 if (rc != 0) { in qam_flip_spec()
8714 pr_err("error %d\n", rc); in qam_flip_spec()
8717 rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo, 0); in qam_flip_spec()
8718 if (rc != 0) { in qam_flip_spec()
8719 pr_err("error %d\n", rc); in qam_flip_spec()
8727 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0); in qam_flip_spec()
8728 if (rc != 0) { in qam_flip_spec()
8729 pr_err("error %d\n", rc); in qam_flip_spec()
8733 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0); in qam_flip_spec()
8734 if (rc != 0) { in qam_flip_spec()
8735 pr_err("error %d\n", rc); in qam_flip_spec()
8738 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0); in qam_flip_spec()
8739 if (rc != 0) { in qam_flip_spec()
8740 pr_err("error %d\n", rc); in qam_flip_spec()
8745 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CI__A, 0, 0); in qam_flip_spec()
8746 if (rc != 0) { in qam_flip_spec()
8747 pr_err("error %d\n", rc); in qam_flip_spec()
8750 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_EP__A, 0, 0); in qam_flip_spec()
8751 if (rc != 0) { in qam_flip_spec()
8752 pr_err("error %d\n", rc); in qam_flip_spec()
8755 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0); in qam_flip_spec()
8756 if (rc != 0) { in qam_flip_spec()
8757 pr_err("error %d\n", rc); in qam_flip_spec()
8762 rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0); in qam_flip_spec()
8763 if (rc != 0) { in qam_flip_spec()
8764 pr_err("error %d\n", rc); in qam_flip_spec()
8771 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0); in qam_flip_spec()
8772 if (rc != 0) { in qam_flip_spec()
8773 pr_err("error %d\n", rc); in qam_flip_spec()
8778 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0); in qam_flip_spec()
8779 if (rc != 0) { in qam_flip_spec()
8780 pr_err("error %d\n", rc); in qam_flip_spec()
8783 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0); in qam_flip_spec()
8784 if (rc != 0) { in qam_flip_spec()
8785 pr_err("error %d\n", rc); in qam_flip_spec()
8790 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0); in qam_flip_spec()
8791 if (rc != 0) { in qam_flip_spec()
8792 pr_err("error %d\n", rc); in qam_flip_spec()
8795 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0); in qam_flip_spec()
8796 if (rc != 0) { in qam_flip_spec()
8797 pr_err("error %d\n", rc); in qam_flip_spec()
8803 rc = drxj_dap_read_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0); in qam_flip_spec()
8804 if (rc != 0) { in qam_flip_spec()
8805 pr_err("error %d\n", rc); in qam_flip_spec()
8808 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0); in qam_flip_spec()
8809 if (rc != 0) { in qam_flip_spec()
8810 pr_err("error %d\n", rc); in qam_flip_spec()
8816 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0); in qam_flip_spec()
8817 if (rc != 0) { in qam_flip_spec()
8818 pr_err("error %d\n", rc); in qam_flip_spec()
8821 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0); in qam_flip_spec()
8822 if (rc != 0) { in qam_flip_spec()
8823 pr_err("error %d\n", rc); in qam_flip_spec()
8827 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0); in qam_flip_spec()
8828 if (rc != 0) { in qam_flip_spec()
8829 pr_err("error %d\n", rc); in qam_flip_spec()
8835 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0); in qam_flip_spec()
8836 if (rc != 0) { in qam_flip_spec()
8837 pr_err("error %d\n", rc); in qam_flip_spec()
8841 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0); in qam_flip_spec()
8842 if (rc != 0) { in qam_flip_spec()
8843 pr_err("error %d\n", rc); in qam_flip_spec()
8849 return rc; in qam_flip_spec()
8875 int rc; in qam64auto() local
8887 rc = ctrl_lock_status(demod, lock_status); in qam64auto()
8888 if (rc != 0) { in qam64auto()
8889 pr_err("error %d\n", rc); in qam64auto()
8896 rc = ctrl_get_qam_sig_quality(demod); in qam64auto()
8897 if (rc != 0) { in qam64auto()
8898 pr_err("error %d\n", rc); in qam64auto()
8913 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); in qam64auto()
8914 if (rc != 0) { in qam64auto()
8915 pr_err("error %d\n", rc); in qam64auto()
8918 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); in qam64auto()
8919 if (rc != 0) { in qam64auto()
8920 pr_err("error %d\n", rc); in qam64auto()
8931 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); in qam64auto()
8932 if (rc != 0) { in qam64auto()
8933 pr_err("error %d\n", rc); in qam64auto()
8936 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0); in qam64auto()
8937 if (rc != 0) { in qam64auto()
8938 pr_err("error %d\n", rc); in qam64auto()
8943 rc = qam_flip_spec(demod, channel); in qam64auto()
8944 if (rc != 0) { in qam64auto()
8945 pr_err("error %d\n", rc); in qam64auto()
8965 rc = ctrl_get_qam_sig_quality(demod); in qam64auto()
8966 if (rc != 0) { in qam64auto()
8967 pr_err("error %d\n", rc); in qam64auto()
8971 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); in qam64auto()
8972 if (rc != 0) { in qam64auto()
8973 pr_err("error %d\n", rc); in qam64auto()
8976 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); in qam64auto()
8977 if (rc != 0) { in qam64auto()
8978 pr_err("error %d\n", rc); in qam64auto()
9002 return rc; in qam64auto()
9023 int rc; in qam256auto() local
9034 rc = ctrl_lock_status(demod, lock_status); in qam256auto()
9035 if (rc != 0) { in qam256auto()
9036 pr_err("error %d\n", rc); in qam256auto()
9042 rc = ctrl_get_qam_sig_quality(demod); in qam256auto()
9043 if (rc != 0) { in qam256auto()
9044 pr_err("error %d\n", rc); in qam256auto()
9060 rc = qam_flip_spec(demod, channel); in qam256auto()
9061 if (rc != 0) { in qam256auto()
9062 pr_err("error %d\n", rc); in qam256auto()
9086 return rc; in qam256auto()
9101 int rc; in set_qam_channel() local
9125 rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL); in set_qam_channel()
9126 if (rc != 0) { in set_qam_channel()
9127 pr_err("error %d\n", rc); in set_qam_channel()
9132 rc = qam64auto(demod, channel, tuner_freq_offset, in set_qam_channel()
9135 rc = qam256auto(demod, channel, tuner_freq_offset, in set_qam_channel()
9137 if (rc != 0) { in set_qam_channel()
9138 pr_err("error %d\n", rc); in set_qam_channel()
9155 rc = set_qam(demod, channel, tuner_freq_offset, in set_qam_channel()
9157 if (rc != 0) { in set_qam_channel()
9158 pr_err("error %d\n", rc); in set_qam_channel()
9161 rc = qam256auto(demod, channel, tuner_freq_offset, in set_qam_channel()
9163 if (rc != 0) { in set_qam_channel()
9164 pr_err("error %d\n", rc); in set_qam_channel()
9181 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9184 if (rc != 0) { in set_qam_channel()
9185 pr_err("error %d\n", rc); in set_qam_channel()
9188 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9191 if (rc != 0) { in set_qam_channel()
9192 pr_err("error %d\n", rc); in set_qam_channel()
9195 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9198 if (rc != 0) { in set_qam_channel()
9199 pr_err("error %d\n", rc); in set_qam_channel()
9203 rc = set_qam(demod, channel, tuner_freq_offset, in set_qam_channel()
9205 if (rc != 0) { in set_qam_channel()
9206 pr_err("error %d\n", rc); in set_qam_channel()
9209 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9212 if (rc != 0) { in set_qam_channel()
9213 pr_err("error %d\n", rc); in set_qam_channel()
9217 rc = qam64auto(demod, channel, tuner_freq_offset, in set_qam_channel()
9219 if (rc != 0) { in set_qam_channel()
9220 pr_err("error %d\n", rc); in set_qam_channel()
9236 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9239 if (rc != 0) { in set_qam_channel()
9240 pr_err("error %d\n", rc); in set_qam_channel()
9243 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9246 if (rc != 0) { in set_qam_channel()
9247 pr_err("error %d\n", rc); in set_qam_channel()
9250 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9253 if (rc != 0) { in set_qam_channel()
9254 pr_err("error %d\n", rc); in set_qam_channel()
9258 rc = set_qam(demod, channel, tuner_freq_offset, in set_qam_channel()
9260 if (rc != 0) { in set_qam_channel()
9261 pr_err("error %d\n", rc); in set_qam_channel()
9264 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9267 if (rc != 0) { in set_qam_channel()
9268 pr_err("error %d\n", rc); in set_qam_channel()
9271 rc = qam64auto(demod, channel, tuner_freq_offset, in set_qam_channel()
9273 if (rc != 0) { in set_qam_channel()
9274 pr_err("error %d\n", rc); in set_qam_channel()
9291 return rc; in set_qam_channel()
9308 int rc; in get_qamrs_err_count() local
9320 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0); in get_qamrs_err_count()
9321 if (rc != 0) { in get_qamrs_err_count()
9322 pr_err("error %d\n", rc); in get_qamrs_err_count()
9326 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors, 0); in get_qamrs_err_count()
9327 if (rc != 0) { in get_qamrs_err_count()
9328 pr_err("error %d\n", rc); in get_qamrs_err_count()
9332 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors, 0); in get_qamrs_err_count()
9333 if (rc != 0) { in get_qamrs_err_count()
9334 pr_err("error %d\n", rc); in get_qamrs_err_count()
9338 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures, 0); in get_qamrs_err_count()
9339 if (rc != 0) { in get_qamrs_err_count()
9340 pr_err("error %d\n", rc); in get_qamrs_err_count()
9344 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count, 0); in get_qamrs_err_count()
9345 if (rc != 0) { in get_qamrs_err_count()
9346 pr_err("error %d\n", rc); in get_qamrs_err_count()
9362 return rc; in get_qamrs_err_count()
9385 int rc; in get_sig_strength() local
9393 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0); in get_sig_strength()
9394 if (rc != 0) { in get_sig_strength()
9395 pr_err("error %d\n", rc); in get_sig_strength()
9399 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0); in get_sig_strength()
9400 if (rc != 0) { in get_sig_strength()
9401 pr_err("error %d\n", rc); in get_sig_strength()
9444 return rc; in get_sig_strength()
9468 int rc; in ctrl_get_qam_sig_quality() local
9498 rc = get_qamrs_err_count(dev_addr, &measuredrs_errors); in ctrl_get_qam_sig_quality()
9499 if (rc != 0) { in ctrl_get_qam_sig_quality()
9500 pr_err("error %d\n", rc); in ctrl_get_qam_sig_quality()
9504 rc = drxj_dap_read_reg16(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power, 0); in ctrl_get_qam_sig_quality()
9505 if (rc != 0) { in ctrl_get_qam_sig_quality()
9506 pr_err("error %d\n", rc); in ctrl_get_qam_sig_quality()
9510 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period, 0); in ctrl_get_qam_sig_quality()
9511 if (rc != 0) { in ctrl_get_qam_sig_quality()
9512 pr_err("error %d\n", rc); in ctrl_get_qam_sig_quality()
9542 rc = -EIO; in ctrl_get_qam_sig_quality()
9564 rc = drxj_dap_read_reg16(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd, 0); in ctrl_get_qam_sig_quality()
9565 if (rc != 0) { in ctrl_get_qam_sig_quality()
9566 pr_err("error %d\n", rc); in ctrl_get_qam_sig_quality()
9647 rc = get_acc_pkt_err(demod, &sig_quality->packet_error); in ctrl_get_qam_sig_quality()
9648 if (rc != 0) { in ctrl_get_qam_sig_quality()
9649 pr_err("error %d\n", rc); in ctrl_get_qam_sig_quality()
9663 return rc; in ctrl_get_qam_sig_quality()
9755 int rc; in power_down_atv() local
9767 rc = scu_command(dev_addr, &cmd_scu); in power_down_atv()
9768 if (rc != 0) { in power_down_atv()
9769 pr_err("error %d\n", rc); in power_down_atv()
9773 …rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP… in power_down_atv()
9774 if (rc != 0) { in power_down_atv()
9775 pr_err("error %d\n", rc); in power_down_atv()
9779 rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0); in power_down_atv()
9780 if (rc != 0) { in power_down_atv()
9781 pr_err("error %d\n", rc); in power_down_atv()
9785 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); in power_down_atv()
9786 if (rc != 0) { in power_down_atv()
9787 pr_err("error %d\n", rc); in power_down_atv()
9790 rc = set_iqm_af(demod, false); in power_down_atv()
9791 if (rc != 0) { in power_down_atv()
9792 pr_err("error %d\n", rc); in power_down_atv()
9796 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); in power_down_atv()
9797 if (rc != 0) { in power_down_atv()
9798 pr_err("error %d\n", rc); in power_down_atv()
9801 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); in power_down_atv()
9802 if (rc != 0) { in power_down_atv()
9803 pr_err("error %d\n", rc); in power_down_atv()
9806 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); in power_down_atv()
9807 if (rc != 0) { in power_down_atv()
9808 pr_err("error %d\n", rc); in power_down_atv()
9811 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); in power_down_atv()
9812 if (rc != 0) { in power_down_atv()
9813 pr_err("error %d\n", rc); in power_down_atv()
9816 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); in power_down_atv()
9817 if (rc != 0) { in power_down_atv()
9818 pr_err("error %d\n", rc); in power_down_atv()
9822 rc = power_down_aud(demod); in power_down_atv()
9823 if (rc != 0) { in power_down_atv()
9824 pr_err("error %d\n", rc); in power_down_atv()
9830 return rc; in power_down_atv()
9845 int rc; in power_down_aud() local
9850 rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0); in power_down_aud()
9851 if (rc != 0) { in power_down_aud()
9852 pr_err("error %d\n", rc); in power_down_aud()
9860 return rc; in power_down_aud()
9873 int rc; in set_orx_nsu_aox() local
9877 rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0); in set_orx_nsu_aox()
9878 if (rc != 0) { in set_orx_nsu_aox()
9879 pr_err("error %d\n", rc); in set_orx_nsu_aox()
9886 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0); in set_orx_nsu_aox()
9887 if (rc != 0) { in set_orx_nsu_aox()
9888 pr_err("error %d\n", rc); in set_orx_nsu_aox()
9894 return rc; in set_orx_nsu_aox()
9923 int rc; in ctrl_set_oob() local
9960 rc = scu_command(dev_addr, &scu_cmd); in ctrl_set_oob()
9961 if (rc != 0) { in ctrl_set_oob()
9962 pr_err("error %d\n", rc); in ctrl_set_oob()
9965 rc = set_orx_nsu_aox(demod, false); in ctrl_set_oob()
9966 if (rc != 0) { in ctrl_set_oob()
9967 pr_err("error %d\n", rc); in ctrl_set_oob()
9970 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); in ctrl_set_oob()
9971 if (rc != 0) { in ctrl_set_oob()
9972 pr_err("error %d\n", rc); in ctrl_set_oob()
10002 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); in ctrl_set_oob()
10003 if (rc != 0) { in ctrl_set_oob()
10004 pr_err("error %d\n", rc); in ctrl_set_oob()
10012 rc = scu_command(dev_addr, &scu_cmd); in ctrl_set_oob()
10013 if (rc != 0) { in ctrl_set_oob()
10014 pr_err("error %d\n", rc); in ctrl_set_oob()
10025 rc = scu_command(dev_addr, &scu_cmd); in ctrl_set_oob()
10026 if (rc != 0) { in ctrl_set_oob()
10027 pr_err("error %d\n", rc); in ctrl_set_oob()
10101 rc = scu_command(dev_addr, &scu_cmd); in ctrl_set_oob()
10102 if (rc != 0) { in ctrl_set_oob()
10103 pr_err("error %d\n", rc); in ctrl_set_oob()
10107 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); in ctrl_set_oob()
10108 if (rc != 0) { in ctrl_set_oob()
10109 pr_err("error %d\n", rc); in ctrl_set_oob()
10112 …rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_… in ctrl_set_oob()
10113 if (rc != 0) { in ctrl_set_oob()
10114 pr_err("error %d\n", rc); in ctrl_set_oob()
10117 …rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_… in ctrl_set_oob()
10118 if (rc != 0) { in ctrl_set_oob()
10119 pr_err("error %d\n", rc); in ctrl_set_oob()
10122 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in ctrl_set_oob()
10123 if (rc != 0) { in ctrl_set_oob()
10124 pr_err("error %d\n", rc); in ctrl_set_oob()
10128 rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0); in ctrl_set_oob()
10129 if (rc != 0) { in ctrl_set_oob()
10130 pr_err("error %d\n", rc); in ctrl_set_oob()
10133 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0); in ctrl_set_oob()
10134 if (rc != 0) { in ctrl_set_oob()
10135 pr_err("error %d\n", rc); in ctrl_set_oob()
10138 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0); in ctrl_set_oob()
10139 if (rc != 0) { in ctrl_set_oob()
10140 pr_err("error %d\n", rc); in ctrl_set_oob()
10145 rc = drxj_dap_write_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0); in ctrl_set_oob()
10146 if (rc != 0) { in ctrl_set_oob()
10147 pr_err("error %d\n", rc); in ctrl_set_oob()
10152 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0); in ctrl_set_oob()
10153 if (rc != 0) { in ctrl_set_oob()
10154 pr_err("error %d\n", rc); in ctrl_set_oob()
10159 …rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_S… in ctrl_set_oob()
10160 if (rc != 0) { in ctrl_set_oob()
10161 pr_err("error %d\n", rc); in ctrl_set_oob()
10164 …rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048… in ctrl_set_oob()
10165 if (rc != 0) { in ctrl_set_oob()
10166 pr_err("error %d\n", rc); in ctrl_set_oob()
10171 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0); in ctrl_set_oob()
10172 if (rc != 0) { in ctrl_set_oob()
10173 pr_err("error %d\n", rc); in ctrl_set_oob()
10176 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0); in ctrl_set_oob()
10177 if (rc != 0) { in ctrl_set_oob()
10178 pr_err("error %d\n", rc); in ctrl_set_oob()
10181 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0); in ctrl_set_oob()
10182 if (rc != 0) { in ctrl_set_oob()
10183 pr_err("error %d\n", rc); in ctrl_set_oob()
10186 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0); in ctrl_set_oob()
10187 if (rc != 0) { in ctrl_set_oob()
10188 pr_err("error %d\n", rc); in ctrl_set_oob()
10193 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0); in ctrl_set_oob()
10194 if (rc != 0) { in ctrl_set_oob()
10195 pr_err("error %d\n", rc); in ctrl_set_oob()
10198 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10199 if (rc != 0) { in ctrl_set_oob()
10200 pr_err("error %d\n", rc); in ctrl_set_oob()
10203 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0); in ctrl_set_oob()
10204 if (rc != 0) { in ctrl_set_oob()
10205 pr_err("error %d\n", rc); in ctrl_set_oob()
10208 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10209 if (rc != 0) { in ctrl_set_oob()
10210 pr_err("error %d\n", rc); in ctrl_set_oob()
10213 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0); in ctrl_set_oob()
10214 if (rc != 0) { in ctrl_set_oob()
10215 pr_err("error %d\n", rc); in ctrl_set_oob()
10220 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0); in ctrl_set_oob()
10221 if (rc != 0) { in ctrl_set_oob()
10222 pr_err("error %d\n", rc); in ctrl_set_oob()
10225 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10226 if (rc != 0) { in ctrl_set_oob()
10227 pr_err("error %d\n", rc); in ctrl_set_oob()
10230 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0); in ctrl_set_oob()
10231 if (rc != 0) { in ctrl_set_oob()
10232 pr_err("error %d\n", rc); in ctrl_set_oob()
10235 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10236 if (rc != 0) { in ctrl_set_oob()
10237 pr_err("error %d\n", rc); in ctrl_set_oob()
10240 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0); in ctrl_set_oob()
10241 if (rc != 0) { in ctrl_set_oob()
10242 pr_err("error %d\n", rc); in ctrl_set_oob()
10247 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0); in ctrl_set_oob()
10248 if (rc != 0) { in ctrl_set_oob()
10249 pr_err("error %d\n", rc); in ctrl_set_oob()
10252 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10253 if (rc != 0) { in ctrl_set_oob()
10254 pr_err("error %d\n", rc); in ctrl_set_oob()
10257 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0); in ctrl_set_oob()
10258 if (rc != 0) { in ctrl_set_oob()
10259 pr_err("error %d\n", rc); in ctrl_set_oob()
10262 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10263 if (rc != 0) { in ctrl_set_oob()
10264 pr_err("error %d\n", rc); in ctrl_set_oob()
10267 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0); in ctrl_set_oob()
10268 if (rc != 0) { in ctrl_set_oob()
10269 pr_err("error %d\n", rc); in ctrl_set_oob()
10274 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0); in ctrl_set_oob()
10275 if (rc != 0) { in ctrl_set_oob()
10276 pr_err("error %d\n", rc); in ctrl_set_oob()
10279 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10280 if (rc != 0) { in ctrl_set_oob()
10281 pr_err("error %d\n", rc); in ctrl_set_oob()
10284 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0); in ctrl_set_oob()
10285 if (rc != 0) { in ctrl_set_oob()
10286 pr_err("error %d\n", rc); in ctrl_set_oob()
10289 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10290 if (rc != 0) { in ctrl_set_oob()
10291 pr_err("error %d\n", rc); in ctrl_set_oob()
10294 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0); in ctrl_set_oob()
10295 if (rc != 0) { in ctrl_set_oob()
10296 pr_err("error %d\n", rc); in ctrl_set_oob()
10301 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0); in ctrl_set_oob()
10302 if (rc != 0) { in ctrl_set_oob()
10303 pr_err("error %d\n", rc); in ctrl_set_oob()
10306 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10307 if (rc != 0) { in ctrl_set_oob()
10308 pr_err("error %d\n", rc); in ctrl_set_oob()
10311 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0); in ctrl_set_oob()
10312 if (rc != 0) { in ctrl_set_oob()
10313 pr_err("error %d\n", rc); in ctrl_set_oob()
10316 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10317 if (rc != 0) { in ctrl_set_oob()
10318 pr_err("error %d\n", rc); in ctrl_set_oob()
10321 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0); in ctrl_set_oob()
10322 if (rc != 0) { in ctrl_set_oob()
10323 pr_err("error %d\n", rc); in ctrl_set_oob()
10328 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0); in ctrl_set_oob()
10329 if (rc != 0) { in ctrl_set_oob()
10330 pr_err("error %d\n", rc); in ctrl_set_oob()
10333 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10334 if (rc != 0) { in ctrl_set_oob()
10335 pr_err("error %d\n", rc); in ctrl_set_oob()
10338 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0); in ctrl_set_oob()
10339 if (rc != 0) { in ctrl_set_oob()
10340 pr_err("error %d\n", rc); in ctrl_set_oob()
10343 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0); in ctrl_set_oob()
10344 if (rc != 0) { in ctrl_set_oob()
10345 pr_err("error %d\n", rc); in ctrl_set_oob()
10348 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0); in ctrl_set_oob()
10349 if (rc != 0) { in ctrl_set_oob()
10350 pr_err("error %d\n", rc); in ctrl_set_oob()
10355 …rc = drxdap_fasi_write_block(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)… in ctrl_set_oob()
10356 if (rc != 0) { in ctrl_set_oob()
10357 pr_err("error %d\n", rc); in ctrl_set_oob()
10360 rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0); in ctrl_set_oob()
10361 if (rc != 0) { in ctrl_set_oob()
10362 pr_err("error %d\n", rc); in ctrl_set_oob()
10368 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0); in ctrl_set_oob()
10369 if (rc != 0) { in ctrl_set_oob()
10370 pr_err("error %d\n", rc); in ctrl_set_oob()
10373 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0); in ctrl_set_oob()
10374 if (rc != 0) { in ctrl_set_oob()
10375 pr_err("error %d\n", rc); in ctrl_set_oob()
10379 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0); in ctrl_set_oob()
10380 if (rc != 0) { in ctrl_set_oob()
10381 pr_err("error %d\n", rc); in ctrl_set_oob()
10384 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0); in ctrl_set_oob()
10385 if (rc != 0) { in ctrl_set_oob()
10386 pr_err("error %d\n", rc); in ctrl_set_oob()
10397 rc = scu_command(dev_addr, &scu_cmd); in ctrl_set_oob()
10398 if (rc != 0) { in ctrl_set_oob()
10399 pr_err("error %d\n", rc); in ctrl_set_oob()
10403 rc = set_orx_nsu_aox(demod, true); in ctrl_set_oob()
10404 if (rc != 0) { in ctrl_set_oob()
10405 pr_err("error %d\n", rc); in ctrl_set_oob()
10408 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0); in ctrl_set_oob()
10409 if (rc != 0) { in ctrl_set_oob()
10410 pr_err("error %d\n", rc); in ctrl_set_oob()
10418 return rc; in ctrl_set_oob()
10446 int rc; in ctrl_set_channel() local
10509 rc = ctrl_set_uio_cfg(demod, &uio_cfg); in ctrl_set_channel()
10510 if (rc != 0) { in ctrl_set_channel()
10511 pr_err("error %d\n", rc); in ctrl_set_channel()
10604 rc = ctrl_uio_write(demod, &uio1); in ctrl_set_channel()
10605 if (rc != 0) { in ctrl_set_channel()
10606 pr_err("error %d\n", rc); in ctrl_set_channel()
10611 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); in ctrl_set_channel()
10612 if (rc != 0) { in ctrl_set_channel()
10613 pr_err("error %d\n", rc); in ctrl_set_channel()
10626 rc = set_vsb(demod); in ctrl_set_channel()
10627 if (rc != 0) { in ctrl_set_channel()
10628 pr_err("error %d\n", rc); in ctrl_set_channel()
10631 rc = set_frequency(demod, channel, tuner_freq_offset); in ctrl_set_channel()
10632 if (rc != 0) { in ctrl_set_channel()
10633 pr_err("error %d\n", rc); in ctrl_set_channel()
10641 rc = set_qam_channel(demod, channel, tuner_freq_offset); in ctrl_set_channel()
10642 if (rc != 0) { in ctrl_set_channel()
10643 pr_err("error %d\n", rc); in ctrl_set_channel()
10658 return rc; in ctrl_set_channel()
10685 int rc; in ctrl_sig_quality() local
10689 rc = get_sig_strength(demod, &strength); in ctrl_sig_quality()
10690 if (rc < 0) { in ctrl_sig_quality()
10691 pr_err("error getting signal strength %d\n", rc); in ctrl_sig_quality()
10701 rc = get_acc_pkt_err(demod, &pkt); in ctrl_sig_quality()
10702 if (rc != 0) { in ctrl_sig_quality()
10703 pr_err("error %d\n", rc); in ctrl_sig_quality()
10716 rc = get_vsb_post_rs_pck_err(dev_addr, &err, &pkt); in ctrl_sig_quality()
10717 if (rc != 0) { in ctrl_sig_quality()
10718 pr_err("error %d getting UCB\n", rc); in ctrl_sig_quality()
10728 rc = get_vs_bpre_viterbi_ber(dev_addr, &ber, &cnt); in ctrl_sig_quality()
10729 if (rc != 0) { in ctrl_sig_quality()
10730 pr_err("error %d getting pre-ber\n", rc); in ctrl_sig_quality()
10739 rc = get_vs_bpost_viterbi_ber(dev_addr, &ber, &cnt); in ctrl_sig_quality()
10740 if (rc != 0) { in ctrl_sig_quality()
10741 pr_err("error %d getting post-ber\n", rc); in ctrl_sig_quality()
10749 rc = get_vsbmer(dev_addr, &mer); in ctrl_sig_quality()
10750 if (rc != 0) { in ctrl_sig_quality()
10751 pr_err("error %d getting MER\n", rc); in ctrl_sig_quality()
10763 rc = ctrl_get_qam_sig_quality(demod); in ctrl_sig_quality()
10764 if (rc != 0) { in ctrl_sig_quality()
10765 pr_err("error %d\n", rc); in ctrl_sig_quality()
10776 return rc; in ctrl_sig_quality()
10801 int rc; in ctrl_lock_status() local
10840 rc = scu_command(dev_addr, &cmd_scu); in ctrl_lock_status()
10841 if (rc != 0) { in ctrl_lock_status()
10842 pr_err("error %d\n", rc); in ctrl_lock_status()
10864 return rc; in ctrl_lock_status()
10883 int rc; in ctrl_set_standard() local
10901 rc = power_down_qam(demod, false); in ctrl_set_standard()
10902 if (rc != 0) { in ctrl_set_standard()
10903 pr_err("error %d\n", rc); in ctrl_set_standard()
10909 rc = power_down_vsb(demod, false); in ctrl_set_standard()
10910 if (rc != 0) { in ctrl_set_standard()
10911 pr_err("error %d\n", rc); in ctrl_set_standard()
10920 rc = -EINVAL; in ctrl_set_standard()
10937 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); in ctrl_set_standard()
10938 if (rc != 0) { in ctrl_set_standard()
10939 pr_err("error %d\n", rc); in ctrl_set_standard()
10946 rc = set_vsb_leak_n_gain(demod); in ctrl_set_standard()
10947 if (rc != 0) { in ctrl_set_standard()
10948 pr_err("error %d\n", rc); in ctrl_set_standard()
10961 return rc; in ctrl_set_standard()
11043 int rc; in ctrl_power_mode() local
11079 rc = power_up_device(demod); in ctrl_power_mode()
11080 if (rc != 0) { in ctrl_power_mode()
11081 pr_err("error %d\n", rc); in ctrl_power_mode()
11107 rc = power_down_qam(demod, true); in ctrl_power_mode()
11108 if (rc != 0) { in ctrl_power_mode()
11109 pr_err("error %d\n", rc); in ctrl_power_mode()
11114 rc = power_down_vsb(demod, true); in ctrl_power_mode()
11115 if (rc != 0) { in ctrl_power_mode()
11116 pr_err("error %d\n", rc); in ctrl_power_mode()
11127 rc = power_down_atv(demod, ext_attr->standard, true); in ctrl_power_mode()
11128 if (rc != 0) { in ctrl_power_mode()
11129 pr_err("error %d\n", rc); in ctrl_power_mode()
11144 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0); in ctrl_power_mode()
11145 if (rc != 0) { in ctrl_power_mode()
11146 pr_err("error %d\n", rc); in ctrl_power_mode()
11149 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); in ctrl_power_mode()
11150 if (rc != 0) { in ctrl_power_mode()
11151 pr_err("error %d\n", rc); in ctrl_power_mode()
11157 rc = init_hi(demod); in ctrl_power_mode()
11158 if (rc != 0) { in ctrl_power_mode()
11159 pr_err("error %d\n", rc); in ctrl_power_mode()
11164 rc = hi_cfg_command(demod); in ctrl_power_mode()
11165 if (rc != 0) { in ctrl_power_mode()
11166 pr_err("error %d\n", rc); in ctrl_power_mode()
11176 return rc; in ctrl_power_mode()
11199 int rc; in ctrl_set_cfg_pre_saw() local
11216 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0); in ctrl_set_cfg_pre_saw()
11217 if (rc != 0) { in ctrl_set_cfg_pre_saw()
11218 pr_err("error %d\n", rc); in ctrl_set_cfg_pre_saw()
11241 return rc; in ctrl_set_cfg_pre_saw()
11262 int rc; in ctrl_set_cfg_afe_gain() local
11297 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0); in ctrl_set_cfg_afe_gain()
11298 if (rc != 0) { in ctrl_set_cfg_afe_gain()
11299 pr_err("error %d\n", rc); in ctrl_set_cfg_afe_gain()
11322 return rc; in ctrl_set_cfg_afe_gain()
11355 int rc; in drxj_open() local
11374 rc = ctrl_power_mode(demod, &power_mode); in drxj_open()
11375 if (rc != 0) { in drxj_open()
11376 pr_err("error %d\n", rc); in drxj_open()
11380 rc = -EINVAL; in drxj_open()
11386 rc = get_device_capabilities(demod); in drxj_open()
11387 if (rc != 0) { in drxj_open()
11388 pr_err("error %d\n", rc); in drxj_open()
11400 …rc = drxj_dap_write_reg16(dev_addr, SIO_CC_SOFT_RST__A, (0x04 | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SO… in drxj_open()
11401 if (rc != 0) { in drxj_open()
11402 pr_err("error %d\n", rc); in drxj_open()
11405 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); in drxj_open()
11406 if (rc != 0) { in drxj_open()
11407 pr_err("error %d\n", rc); in drxj_open()
11414 …rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_… in drxj_open()
11415 if (rc != 0) { in drxj_open()
11416 pr_err("error %d\n", rc); in drxj_open()
11420 rc = set_iqm_af(demod, false); in drxj_open()
11421 if (rc != 0) { in drxj_open()
11422 pr_err("error %d\n", rc); in drxj_open()
11425 rc = set_orx_nsu_aox(demod, false); in drxj_open()
11426 if (rc != 0) { in drxj_open()
11427 pr_err("error %d\n", rc); in drxj_open()
11431 rc = init_hi(demod); in drxj_open()
11432 if (rc != 0) { in drxj_open()
11433 pr_err("error %d\n", rc); in drxj_open()
11441 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); in drxj_open()
11442 if (rc != 0) { in drxj_open()
11443 pr_err("error %d\n", rc); in drxj_open()
11447 rc = power_down_aud(demod); in drxj_open()
11448 if (rc != 0) { in drxj_open()
11449 pr_err("error %d\n", rc); in drxj_open()
11453 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0); in drxj_open()
11454 if (rc != 0) { in drxj_open()
11455 pr_err("error %d\n", rc); in drxj_open()
11468 rc = -EINVAL; in drxj_open()
11472 rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_UPLOAD); in drxj_open()
11473 if (rc != 0) { in drxj_open()
11474 pr_err("error %d while uploading the firmware\n", rc); in drxj_open()
11478 rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_VERIFY); in drxj_open()
11479 if (rc != 0) { in drxj_open()
11481 rc); in drxj_open()
11489 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); in drxj_open()
11490 if (rc != 0) { in drxj_open()
11491 pr_err("error %d\n", rc); in drxj_open()
11502 rc = smart_ant_init(demod); in drxj_open()
11503 if (rc != 0) { in drxj_open()
11504 pr_err("error %d\n", rc); in drxj_open()
11527 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0); in drxj_open()
11528 if (rc != 0) { in drxj_open()
11529 pr_err("error %d\n", rc); in drxj_open()
11532 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0); in drxj_open()
11533 if (rc != 0) { in drxj_open()
11534 pr_err("error %d\n", rc); in drxj_open()
11538 rc = ctrl_set_oob(demod, NULL); in drxj_open()
11539 if (rc != 0) { in drxj_open()
11540 pr_err("error %d\n", rc); in drxj_open()
11552 return rc; in drxj_open()
11565 int rc; in drxj_close() local
11576 rc = ctrl_power_mode(demod, &power_mode); in drxj_close()
11577 if (rc != 0) { in drxj_close()
11578 pr_err("error %d\n", rc); in drxj_close()
11582 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); in drxj_close()
11583 if (rc != 0) { in drxj_close()
11584 pr_err("error %d\n", rc); in drxj_close()
11588 rc = ctrl_power_mode(demod, &power_mode); in drxj_close()
11589 if (rc != 0) { in drxj_close()
11590 pr_err("error %d\n", rc); in drxj_close()
11600 return rc; in drxj_close()
11745 int rc; in drx_ctrl_u_code() local
11763 rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent); in drx_ctrl_u_code()
11764 if (rc < 0) { in drx_ctrl_u_code()
11766 return rc; in drx_ctrl_u_code()
11771 rc = -EINVAL; in drx_ctrl_u_code()
11791 rc = -EINVAL; in drx_ctrl_u_code()
11797 rc = drx_check_firmware(demod, (u8 *)mc_data_init, size); in drx_ctrl_u_code()
11798 if (rc) in drx_ctrl_u_code()
11833 rc = -EINVAL; in drx_ctrl_u_code()
11850 rc = -EIO; in drx_ctrl_u_code()
11908 return rc; in drx_ctrl_u_code()
12223 int rc = 0; in drx39xxj_init() local
12228 rc = drxj_open(demod); in drx39xxj_init()
12229 if (rc != 0) in drx39xxj_init()
12230 pr_err("drx39xxj_init(): DRX open failed rc=%d!\n", rc); in drx39xxj_init()
12234 return rc; in drx39xxj_init()