117 	struct intel_iommu *iommu;  in iommu_regset_show()  local
123 	for_each_active_iommu(iommu, drhd) {  in iommu_regset_show()
131 			   iommu->name, drhd->reg_base_addr);  in iommu_regset_show()
137 		raw_spin_lock_irqsave(&iommu->register_lock, flag);  in iommu_regset_show()
139 			value = dmar_readl(iommu->reg + iommu_regs_32[i].offset);  in iommu_regset_show()
145 			value = dmar_readq(iommu->reg + iommu_regs_64[i].offset);  in iommu_regset_show()
150 		raw_spin_unlock_irqrestore(&iommu->register_lock, flag);  in iommu_regset_show()
218 static void ctx_tbl_walk(struct seq_file *m, struct intel_iommu *iommu, u16 bus)  in ctx_tbl_walk()  argument
240 		context = iommu_context_addr(iommu, bus, devfn, 0);  in ctx_tbl_walk()
249 		tbl_wlk.rt_entry = &iommu->root_entry[bus];  in ctx_tbl_walk()
253 		if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) {  in ctx_tbl_walk()
264 static void root_tbl_walk(struct seq_file *m, struct intel_iommu *iommu)  in root_tbl_walk()  argument
268 	spin_lock(&iommu->lock);  in root_tbl_walk()
269 	seq_printf(m, "IOMMU %s: Root Table Address: 0x%llx\n", iommu->name,  in root_tbl_walk()
270 		   (u64)virt_to_phys(iommu->root_entry));  in root_tbl_walk()
279 		ctx_tbl_walk(m, iommu, bus);  in root_tbl_walk()
280 	spin_unlock(&iommu->lock);  in root_tbl_walk()
286 	struct intel_iommu *iommu;  in dmar_translation_struct_show()  local
290 	for_each_active_iommu(iommu, drhd) {  in dmar_translation_struct_show()
291 		sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);  in dmar_translation_struct_show()
294 				   iommu->name);  in dmar_translation_struct_show()
297 		root_tbl_walk(m, iommu);  in dmar_translation_struct_show()
397 					  struct intel_iommu *iommu)  in invalidation_queue_entry_show()  argument
399 	int index, shift = qi_shift(iommu);  in invalidation_queue_entry_show()
403 	if (ecap_smts(iommu->ecap))  in invalidation_queue_entry_show()
410 		desc = iommu->qi->desc + offset;  in invalidation_queue_entry_show()
411 		if (ecap_smts(iommu->ecap))  in invalidation_queue_entry_show()
415 				   iommu->qi->desc_status[index]);  in invalidation_queue_entry_show()
419 				   iommu->qi->desc_status[index]);  in invalidation_queue_entry_show()
426 	struct intel_iommu *iommu;  in invalidation_queue_show()  local
432 	for_each_active_iommu(iommu, drhd) {  in invalidation_queue_show()
433 		qi = iommu->qi;  in invalidation_queue_show()
434 		shift = qi_shift(iommu);  in invalidation_queue_show()
436 		if (!qi || !ecap_qis(iommu->ecap))  in invalidation_queue_show()
439 		seq_printf(m, "Invalidation queue on IOMMU: %s\n", iommu->name);  in invalidation_queue_show()
444 			   dmar_readq(iommu->reg + DMAR_IQH_REG) >> shift,  in invalidation_queue_show()
445 			   dmar_readq(iommu->reg + DMAR_IQT_REG) >> shift);  in invalidation_queue_show()
446 		invalidation_queue_entry_show(m, iommu);  in invalidation_queue_show()
458 				    struct intel_iommu *iommu)  in ir_tbl_remap_entry_show()  argument
468 		ri_entry = &iommu->ir_table->base[idx];  in ir_tbl_remap_entry_show()
482 				     struct intel_iommu *iommu)  in ir_tbl_posted_entry_show()  argument
492 		pi_entry = &iommu->ir_table->base[idx];  in ir_tbl_posted_entry_show()
514 	struct intel_iommu *iommu;  in ir_translation_struct_show()  local
519 	for_each_active_iommu(iommu, drhd) {  in ir_translation_struct_show()
520 		if (!ecap_ir_support(iommu->ecap))  in ir_translation_struct_show()
524 			   iommu->name);  in ir_translation_struct_show()
526 		sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);  in ir_translation_struct_show()
527 		if (iommu->ir_table && (sts & DMA_GSTS_IRES)) {  in ir_translation_struct_show()
528 			irta = virt_to_phys(iommu->ir_table->base);  in ir_translation_struct_show()
530 			ir_tbl_remap_entry_show(m, iommu);  in ir_translation_struct_show()
539 	for_each_active_iommu(iommu, drhd) {  in ir_translation_struct_show()
540 		if (!cap_pi_support(iommu->cap))  in ir_translation_struct_show()
544 			   iommu->name);  in ir_translation_struct_show()
546 		if (iommu->ir_table) {  in ir_translation_struct_show()
547 			irta = virt_to_phys(iommu->ir_table->base);  in ir_translation_struct_show()
549 			ir_tbl_posted_entry_show(m, iommu);  in ir_translation_struct_show()
562 static void latency_show_one(struct seq_file *m, struct intel_iommu *iommu,  in latency_show_one()  argument
568 		   iommu->name, drhd->reg_base_addr);  in latency_show_one()
570 	ret = dmar_latency_snapshot(iommu, debug_buf, DEBUG_BUFFER_SIZE);  in latency_show_one()
581 	struct intel_iommu *iommu;  in latency_show()  local
584 	for_each_active_iommu(iommu, drhd)  in latency_show()
585 		latency_show_one(m, iommu, drhd);  in latency_show()
601 	struct intel_iommu *iommu;  in dmar_perf_latency_write()  local
619 		for_each_active_iommu(iommu, drhd) {  in dmar_perf_latency_write()
620 			dmar_latency_disable(iommu, DMAR_LATENCY_INV_IOTLB);  in dmar_perf_latency_write()
621 			dmar_latency_disable(iommu, DMAR_LATENCY_INV_DEVTLB);  in dmar_perf_latency_write()
622 			dmar_latency_disable(iommu, DMAR_LATENCY_INV_IEC);  in dmar_perf_latency_write()
623 			dmar_latency_disable(iommu, DMAR_LATENCY_PRQ);  in dmar_perf_latency_write()
629 		for_each_active_iommu(iommu, drhd)  in dmar_perf_latency_write()
630 			dmar_latency_enable(iommu, DMAR_LATENCY_INV_IOTLB);  in dmar_perf_latency_write()
635 		for_each_active_iommu(iommu, drhd)  in dmar_perf_latency_write()
636 			dmar_latency_enable(iommu, DMAR_LATENCY_INV_DEVTLB);  in dmar_perf_latency_write()
641 		for_each_active_iommu(iommu, drhd)  in dmar_perf_latency_write()
642 			dmar_latency_enable(iommu, DMAR_LATENCY_INV_IEC);  in dmar_perf_latency_write()
647 		for_each_active_iommu(iommu, drhd)  in dmar_perf_latency_write()
648 			dmar_latency_enable(iommu, DMAR_LATENCY_PRQ);  in dmar_perf_latency_write()