Lines Matching refs:GENMASK_ULL
134 #define STRTAB_BASE_ADDR_MASK GENMASK_ULL(51, 6)
164 #define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2)
184 #define Q_BASE_ADDR_MASK GENMASK_ULL(51, 5)
205 #define STRTAB_L1_DESC_SPAN GENMASK_ULL(4, 0)
206 #define STRTAB_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 6)
210 #define STRTAB_STE_0_CFG GENMASK_ULL(3, 1)
216 #define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4)
219 #define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6)
220 #define STRTAB_STE_0_S1CDMAX GENMASK_ULL(63, 59)
222 #define STRTAB_STE_1_S1DSS GENMASK_ULL(1, 0)
231 #define STRTAB_STE_1_S1CIR GENMASK_ULL(3, 2)
232 #define STRTAB_STE_1_S1COR GENMASK_ULL(5, 4)
233 #define STRTAB_STE_1_S1CSH GENMASK_ULL(7, 6)
237 #define STRTAB_STE_1_EATS GENMASK_ULL(29, 28)
242 #define STRTAB_STE_1_STRW GENMASK_ULL(31, 30)
246 #define STRTAB_STE_1_SHCFG GENMASK_ULL(45, 44)
249 #define STRTAB_STE_2_S2VMID GENMASK_ULL(15, 0)
250 #define STRTAB_STE_2_VTCR GENMASK_ULL(50, 32)
251 #define STRTAB_STE_2_VTCR_S2T0SZ GENMASK_ULL(5, 0)
252 #define STRTAB_STE_2_VTCR_S2SL0 GENMASK_ULL(7, 6)
253 #define STRTAB_STE_2_VTCR_S2IR0 GENMASK_ULL(9, 8)
254 #define STRTAB_STE_2_VTCR_S2OR0 GENMASK_ULL(11, 10)
255 #define STRTAB_STE_2_VTCR_S2SH0 GENMASK_ULL(13, 12)
256 #define STRTAB_STE_2_VTCR_S2TG GENMASK_ULL(15, 14)
257 #define STRTAB_STE_2_VTCR_S2PS GENMASK_ULL(18, 16)
263 #define STRTAB_STE_3_S2TTB_MASK GENMASK_ULL(51, 4)
277 #define CTXDESC_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 12)
280 #define CTXDESC_CD_0_TCR_T0SZ GENMASK_ULL(5, 0)
281 #define CTXDESC_CD_0_TCR_TG0 GENMASK_ULL(7, 6)
282 #define CTXDESC_CD_0_TCR_IRGN0 GENMASK_ULL(9, 8)
283 #define CTXDESC_CD_0_TCR_ORGN0 GENMASK_ULL(11, 10)
284 #define CTXDESC_CD_0_TCR_SH0 GENMASK_ULL(13, 12)
291 #define CTXDESC_CD_0_TCR_IPS GENMASK_ULL(34, 32)
299 #define CTXDESC_CD_0_ASID GENMASK_ULL(63, 48)
301 #define CTXDESC_CD_1_TTB0_MASK GENMASK_ULL(51, 4)
329 #define CMDQ_0_OP GENMASK_ULL(7, 0)
332 #define CMDQ_PREFETCH_0_SID GENMASK_ULL(63, 32)
333 #define CMDQ_PREFETCH_1_SIZE GENMASK_ULL(4, 0)
334 #define CMDQ_PREFETCH_1_ADDR_MASK GENMASK_ULL(63, 12)
336 #define CMDQ_CFGI_0_SSID GENMASK_ULL(31, 12)
337 #define CMDQ_CFGI_0_SID GENMASK_ULL(63, 32)
339 #define CMDQ_CFGI_1_RANGE GENMASK_ULL(4, 0)
341 #define CMDQ_TLBI_0_NUM GENMASK_ULL(16, 12)
343 #define CMDQ_TLBI_0_SCALE GENMASK_ULL(24, 20)
344 #define CMDQ_TLBI_0_VMID GENMASK_ULL(47, 32)
345 #define CMDQ_TLBI_0_ASID GENMASK_ULL(63, 48)
347 #define CMDQ_TLBI_1_TTL GENMASK_ULL(9, 8)
348 #define CMDQ_TLBI_1_TG GENMASK_ULL(11, 10)
349 #define CMDQ_TLBI_1_VA_MASK GENMASK_ULL(63, 12)
350 #define CMDQ_TLBI_1_IPA_MASK GENMASK_ULL(51, 12)
352 #define CMDQ_ATC_0_SSID GENMASK_ULL(31, 12)
353 #define CMDQ_ATC_0_SID GENMASK_ULL(63, 32)
355 #define CMDQ_ATC_1_SIZE GENMASK_ULL(5, 0)
356 #define CMDQ_ATC_1_ADDR_MASK GENMASK_ULL(63, 12)
358 #define CMDQ_PRI_0_SSID GENMASK_ULL(31, 12)
359 #define CMDQ_PRI_0_SID GENMASK_ULL(63, 32)
360 #define CMDQ_PRI_1_GRPID GENMASK_ULL(8, 0)
361 #define CMDQ_PRI_1_RESP GENMASK_ULL(13, 12)
366 #define CMDQ_RESUME_0_RESP GENMASK_ULL(13, 12)
367 #define CMDQ_RESUME_0_SID GENMASK_ULL(63, 32)
368 #define CMDQ_RESUME_1_STAG GENMASK_ULL(15, 0)
370 #define CMDQ_SYNC_0_CS GENMASK_ULL(13, 12)
374 #define CMDQ_SYNC_0_MSH GENMASK_ULL(23, 22)
375 #define CMDQ_SYNC_0_MSIATTR GENMASK_ULL(27, 24)
376 #define CMDQ_SYNC_0_MSIDATA GENMASK_ULL(63, 32)
377 #define CMDQ_SYNC_1_MSIADDR_MASK GENMASK_ULL(51, 2)
384 #define EVTQ_0_ID GENMASK_ULL(7, 0)
392 #define EVTQ_0_SSID GENMASK_ULL(31, 12)
393 #define EVTQ_0_SID GENMASK_ULL(63, 32)
394 #define EVTQ_1_STAG GENMASK_ULL(15, 0)
400 #define EVTQ_1_CLASS GENMASK_ULL(41, 40)
402 #define EVTQ_2_ADDR GENMASK_ULL(63, 0)
403 #define EVTQ_3_IPA GENMASK_ULL(51, 12)
410 #define PRIQ_0_SID GENMASK_ULL(31, 0)
411 #define PRIQ_0_SSID GENMASK_ULL(51, 32)
419 #define PRIQ_1_PRG_IDX GENMASK_ULL(8, 0)
420 #define PRIQ_1_ADDR_MASK GENMASK_ULL(63, 12)