Lines Matching refs:GENMASK_ULL

375 #define IRDMA_CQPSQ_QHASH_VLANID GENMASK_ULL(43, 32)
376 #define IRDMA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32)
377 #define IRDMA_CQPSQ_QHASH_QS_HANDLE GENMASK_ULL(9, 0)
378 #define IRDMA_CQPSQ_QHASH_SRC_PORT GENMASK_ULL(31, 16)
379 #define IRDMA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0)
380 #define IRDMA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)
381 #define IRDMA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0)
382 #define IRDMA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)
383 #define IRDMA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0)
385 #define IRDMA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32)
386 #define IRDMA_CQPSQ_QHASH_MANAGE GENMASK_ULL(62, 61)
389 #define IRDMA_CQPSQ_QHASH_ENTRYTYPE GENMASK_ULL(44, 42)
394 #define IRDMA_CQPSQ_STATS_OP GENMASK_ULL(37, 32)
395 #define IRDMA_CQPSQ_STATS_INST_INDEX GENMASK_ULL(6, 0)
396 #define IRDMA_CQPSQ_STATS_HMC_FCN_INDEX GENMASK_ULL(5, 0)
398 #define IRDMA_CQPSQ_WS_NODEOP GENMASK_ULL(53, 52)
402 #define IRDMA_CQPSQ_WS_PRIOTYPE GENMASK_ULL(60, 59)
403 #define IRDMA_CQPSQ_WS_TC GENMASK_ULL(58, 56)
404 #define IRDMA_CQPSQ_WS_VMVFTYPE GENMASK_ULL(55, 54)
405 #define IRDMA_CQPSQ_WS_VMVFNUM GENMASK_ULL(51, 42)
406 #define IRDMA_CQPSQ_WS_OP GENMASK_ULL(37, 32)
407 #define IRDMA_CQPSQ_WS_PARENTID GENMASK_ULL(25, 16)
408 #define IRDMA_CQPSQ_WS_NODEID GENMASK_ULL(9, 0)
409 #define IRDMA_CQPSQ_WS_VSI GENMASK_ULL(57, 48)
410 #define IRDMA_CQPSQ_WS_WEIGHT GENMASK_ULL(38, 32)
415 #define IRDMA_CQPSQ_UP_OP GENMASK_ULL(37, 32)
416 #define IRDMA_CQPSQ_UP_HMCFCNIDX GENMASK_ULL(5, 0)
417 #define IRDMA_CQPSQ_UP_CNPOVERRIDE GENMASK_ULL(37, 32)
419 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN GENMASK_ULL(31, 0)
420 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP GENMASK_ULL(37, 32)
421 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED GENMASK_ULL(47, 32)
422 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MAJOR_VERSION GENMASK_ULL(23, 16)
423 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MINOR_VERSION GENMASK_ULL(7, 0)
424 #define IRDMA_CQPHC_SQSIZE GENMASK_ULL(11, 8)
427 #define IRDMA_CQPHC_PROTOCOL_USED GENMASK_ULL(4, 3)
428 #define IRDMA_CQPHC_MIN_RATE GENMASK_ULL(51, 48)
429 #define IRDMA_CQPHC_MIN_DEC_FACTOR GENMASK_ULL(59, 56)
430 #define IRDMA_CQPHC_DCQCN_T GENMASK_ULL(15, 0)
431 #define IRDMA_CQPHC_HAI_FACTOR GENMASK_ULL(47, 32)
432 #define IRDMA_CQPHC_RAI_FACTOR GENMASK_ULL(63, 48)
433 #define IRDMA_CQPHC_DCQCN_B GENMASK_ULL(24, 0)
434 #define IRDMA_CQPHC_DCQCN_F GENMASK_ULL(27, 25)
436 #define IRDMA_CQPHC_RREDUCE_MPERIOD GENMASK_ULL(63, 32)
437 #define IRDMA_CQPHC_HW_MINVER GENMASK_ULL(15, 0)
442 #define IRDMA_CQPHC_HW_MAJVER GENMASK_ULL(31, 16)
443 #define IRDMA_CQPHC_CEQPERVF GENMASK_ULL(39, 32)
445 #define IRDMA_CQPHC_ENABLED_VFS GENMASK_ULL(37, 32)
447 #define IRDMA_CQPHC_HMC_PROFILE GENMASK_ULL(2, 0)
448 #define IRDMA_CQPHC_SVER GENMASK_ULL(31, 24)
449 #define IRDMA_CQPHC_SQBASE GENMASK_ULL(63, 9)
451 #define IRDMA_CQPHC_QPCTX GENMASK_ULL(63, 0)
452 #define IRDMA_QP_DBSA_HW_SQ_TAIL GENMASK_ULL(14, 0)
453 #define IRDMA_CQ_DBSA_CQEIDX GENMASK_ULL(19, 0)
454 #define IRDMA_CQ_DBSA_SW_CQ_SELECT GENMASK_ULL(13, 0)
457 #define IRDMA_CQ_DBSA_ARM_SEQ_NUM GENMASK_ULL(17, 16)
462 #define IRDMA_CCQ_OPRETVAL GENMASK_ULL(31, 0)
464 #define IRDMA_CQ_MINERR GENMASK_ULL(15, 0)
465 #define IRDMA_CQ_MAJERR GENMASK_ULL(31, 16)
466 #define IRDMA_CQ_WQEIDX GENMASK_ULL(46, 32)
476 #define IRDMA_CQ_UDSMAC GENMASK_ULL(47, 0)
477 #define IRDMA_CQ_UDVLAN GENMASK_ULL(63, 48)
481 #define IRDMA_CQ_IMMDATALOW32 GENMASK_ULL(31, 0)
482 #define IRDMA_CQ_IMMDATAUP32 GENMASK_ULL(63, 32)
483 #define IRDMACQ_PAYLDLEN GENMASK_ULL(31, 0)
484 #define IRDMACQ_TCPSEQNUMRTT GENMASK_ULL(63, 32)
485 #define IRDMACQ_INVSTAG GENMASK_ULL(31, 0)
486 #define IRDMACQ_QPID GENMASK_ULL(55, 32)
488 #define IRDMACQ_UDSRCQPN GENMASK_ULL(31, 0)
493 #define IRDMACQ_OP GENMASK_ULL(61, 56)
495 #define IRDMA_CEQE_CQCTX GENMASK_ULL(62, 0)
500 #define IRDMA_AEQE_QPCQID_LOW GENMASK_ULL(17, 0)
502 #define IRDMA_AEQE_WQDESCIDX GENMASK_ULL(32, 18)
504 #define IRDMA_AEQE_AECODE GENMASK_ULL(45, 34)
505 #define IRDMA_AEQE_AESRC GENMASK_ULL(53, 50)
506 #define IRDMA_AEQE_IWSTATE GENMASK_ULL(56, 54)
507 #define IRDMA_AEQE_TCPSTATE GENMASK_ULL(60, 57)
508 #define IRDMA_AEQE_Q2DATA GENMASK_ULL(62, 61)
511 #define IRDMA_UDA_QPSQ_NEXT_HDR GENMASK_ULL(23, 16)
512 #define IRDMA_UDA_QPSQ_OPCODE GENMASK_ULL(37, 32)
513 #define IRDMA_UDA_QPSQ_L4LEN GENMASK_ULL(45, 42)
514 #define IRDMA_GEN1_UDA_QPSQ_L4LEN GENMASK_ULL(27, 24)
515 #define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0)
518 #define IRDMA_UDA_QPSQ_MACLEN GENMASK_ULL(62, 56)
519 #define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48)
520 #define IRDMA_UDA_QPSQ_L4T GENMASK_ULL(31, 30)
521 #define IRDMA_UDA_QPSQ_IIPT GENMASK_ULL(29, 28)
522 #define IRDMA_UDA_PAYLOADLEN GENMASK_ULL(13, 0)
523 #define IRDMA_UDA_HDRLEN GENMASK_ULL(24, 16)
525 #define IRDMA_UDA_L3PROTO GENMASK_ULL(1, 0)
526 #define IRDMA_UDA_L4PROTO GENMASK_ULL(17, 16)
528 #define IRDMA_CQPSQ_BUFSIZE GENMASK_ULL(31, 0)
529 #define IRDMA_CQPSQ_OPCODE GENMASK_ULL(37, 32)
531 #define IRDMA_CQPSQ_TPHVAL GENMASK_ULL(7, 0)
533 #define IRDMA_CQPSQ_VSIIDX GENMASK_ULL(17, 8)
540 #define IRDMA_CQPSQ_QP_NEWMSS GENMASK_ULL(45, 32)
541 #define IRDMA_CQPSQ_QP_TERMLEN GENMASK_ULL(51, 48)
556 #define IRDMA_CQPSQ_QP_QPTYPE GENMASK_ULL(50, 48)
562 #define IRDMA_CQPSQ_QP_TERMACT GENMASK_ULL(57, 56)
565 #define IRDMA_CQPSQ_QP_NEXTIWSTATE GENMASK_ULL(62, 60)
569 #define IRDMA_CQPSQ_CQ_CQSIZE GENMASK_ULL(20, 0)
570 #define IRDMA_CQPSQ_CQ_CQCTX GENMASK_ULL(62, 0)
573 #define IRDMA_CQPSQ_CQ_OP GENMASK_ULL(37, 32)
575 #define IRDMA_CQPSQ_CQ_LPBLSIZE GENMASK_ULL(45, 44)
581 #define IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
585 #define IRDMA_CQPSQ_STAG_STAGLEN GENMASK_ULL(45, 0)
586 #define IRDMA_CQPSQ_STAG_KEY GENMASK_ULL(7, 0)
587 #define IRDMA_CQPSQ_STAG_IDX GENMASK_ULL(31, 8)
589 #define IRDMA_CQPSQ_STAG_PARENTSTAGIDX GENMASK_ULL(55, 32)
595 #define IRDMA_CQPSQ_STAG_HPAGESIZE GENMASK_ULL(47, 46)
596 #define IRDMA_CQPSQ_STAG_ARIGHTS GENMASK_ULL(52, 48)
603 #define IRDMA_CQPSQ_STAG_HMCFNIDX GENMASK_ULL(5, 0)
605 #define IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
607 #define IRDMA_CQPSQ_MLM_TABLEIDX GENMASK_ULL(5, 0)
610 #define IRDMA_CQPSQ_MLM_MAC0 GENMASK_ULL(7, 0)
611 #define IRDMA_CQPSQ_MLM_MAC1 GENMASK_ULL(15, 8)
612 #define IRDMA_CQPSQ_MLM_MAC2 GENMASK_ULL(23, 16)
613 #define IRDMA_CQPSQ_MLM_MAC3 GENMASK_ULL(31, 24)
614 #define IRDMA_CQPSQ_MLM_MAC4 GENMASK_ULL(39, 32)
615 #define IRDMA_CQPSQ_MLM_MAC5 GENMASK_ULL(47, 40)
616 #define IRDMA_CQPSQ_MAT_REACHMAX GENMASK_ULL(31, 0)
617 #define IRDMA_CQPSQ_MAT_MACADDR GENMASK_ULL(47, 0)
618 #define IRDMA_CQPSQ_MAT_ARPENTRYIDX GENMASK_ULL(11, 0)
622 #define IRDMA_CQPSQ_MVPBP_PD_ENTRY_CNT GENMASK_ULL(9, 0)
623 #define IRDMA_CQPSQ_MVPBP_FIRST_PD_INX GENMASK_ULL(24, 16)
624 #define IRDMA_CQPSQ_MVPBP_SD_INX GENMASK_ULL(43, 32)
626 #define IRDMA_CQPSQ_MVPBP_PD_PLPBA GENMASK_ULL(63, 3)
632 #define IRDMA_CQPSQ_MPP_QS_HANDLE GENMASK_ULL(9, 0)
633 #define IRDMA_CQPSQ_MPP_PPIDX GENMASK_ULL(9, 0)
634 #define IRDMA_CQPSQ_MPP_PPTYPE GENMASK_ULL(61, 60)
640 #define IRDMA_CQPSQ_UCTX_QPID GENMASK_ULL(23, 0)
641 #define IRDMA_CQPSQ_UCTX_QPTYPE GENMASK_ULL(51, 48)
646 #define IRDMA_CQPSQ_MHMC_VFIDX GENMASK_ULL(15, 0)
649 #define IRDMA_CQPSQ_SHMCRP_HMC_PROFILE GENMASK_ULL(2, 0)
650 #define IRDMA_CQPSQ_SHMCRP_VFNUM GENMASK_ULL(37, 32)
651 #define IRDMA_CQPSQ_CEQ_CEQSIZE GENMASK_ULL(21, 0)
652 #define IRDMA_CQPSQ_CEQ_CEQID GENMASK_ULL(9, 0)
657 #define IRDMA_CQPSQ_CEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
658 #define IRDMA_CQPSQ_AEQ_AEQECNT GENMASK_ULL(18, 0)
661 #define IRDMA_CQPSQ_AEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
663 #define IRDMA_COMMIT_FPM_QPCNT GENMASK_ULL(18, 0)
666 #define IRDMA_CQPSQ_CFPM_HMCFNID GENMASK_ULL(5, 0)
667 #define IRDMA_CQPSQ_FWQE_AECODE GENMASK_ULL(15, 0)
668 #define IRDMA_CQPSQ_FWQE_AESOURCE GENMASK_ULL(19, 16)
669 #define IRDMA_CQPSQ_FWQE_RQMNERR GENMASK_ULL(15, 0)
670 #define IRDMA_CQPSQ_FWQE_RQMJERR GENMASK_ULL(31, 16)
671 #define IRDMA_CQPSQ_FWQE_SQMNERR GENMASK_ULL(47, 32)
672 #define IRDMA_CQPSQ_FWQE_SQMJERR GENMASK_ULL(63, 48)
673 #define IRDMA_CQPSQ_FWQE_QPID GENMASK_ULL(23, 0)
678 #define IRDMA_CQPSQ_MAPT_PORT GENMASK_ULL(15, 0)
680 #define IRDMA_CQPSQ_UPESD_SDCMD GENMASK_ULL(31, 0)
681 #define IRDMA_CQPSQ_UPESD_SDDATALOW GENMASK_ULL(31, 0)
682 #define IRDMA_CQPSQ_UPESD_SDDATAHI GENMASK_ULL(63, 32)
683 #define IRDMA_CQPSQ_UPESD_HMCFNID GENMASK_ULL(5, 0)
690 #define IRDMA_CQPSQ_UPESD_BM GENMASK_ULL(34, 32)
691 #define IRDMA_CQPSQ_UPESD_ENTRY_COUNT GENMASK_ULL(3, 0)
693 #define IRDMA_CQPSQ_SUSPENDQP_QPID GENMASK_ULL(23, 0)
694 #define IRDMA_CQPSQ_RESUMEQP_QSHANDLE GENMASK_ULL(31, 0)
704 #define IRDMAQPC_DDP_VER GENMASK_ULL(1, 0)
711 #define IRDMAQPC_RQWQESIZE GENMASK_ULL(9, 8)
713 #define IRDMAQPC_LIMIT GENMASK_ULL(13, 12)
717 #define IRDMAQPC_DUPACK_THRESH GENMASK_ULL(18, 16)
719 #define IRDMAQPC_DIS_VLAN_CHECKS GENMASK_ULL(21, 19)
725 #define IRDMAQPC_PPIDX GENMASK_ULL(41, 32)
727 #define IRDMAQPC_RDMAP_VER GENMASK_ULL(63, 62)
728 #define IRDMAQPC_ROCE_TVER GENMASK_ULL(63, 60)
732 #define IRDMAQPC_TTL GENMASK_ULL(7, 0)
733 #define IRDMAQPC_RQSIZE GENMASK_ULL(11, 8)
734 #define IRDMAQPC_SQSIZE GENMASK_ULL(15, 12)
737 #define IRDMAQPC_TOS GENMASK_ULL(31, 24)
738 #define IRDMAQPC_SRCPORTNUM GENMASK_ULL(47, 32)
739 #define IRDMAQPC_DESTPORTNUM GENMASK_ULL(63, 48)
740 #define IRDMAQPC_DESTIPADDR0 GENMASK_ULL(63, 32)
741 #define IRDMAQPC_DESTIPADDR1 GENMASK_ULL(31, 0)
742 #define IRDMAQPC_DESTIPADDR2 GENMASK_ULL(63, 32)
743 #define IRDMAQPC_DESTIPADDR3 GENMASK_ULL(31, 0)
744 #define IRDMAQPC_SNDMSS GENMASK_ULL(29, 16)
745 #define IRDMAQPC_SYN_RST_HANDLING GENMASK_ULL(31, 30)
746 #define IRDMAQPC_VLANTAG GENMASK_ULL(47, 32)
747 #define IRDMAQPC_ARPIDX GENMASK_ULL(63, 48)
748 #define IRDMAQPC_FLOWLABEL GENMASK_ULL(19, 0)
753 #define IRDMAQPC_TCPSTATE GENMASK_ULL(31, 28)
754 #define IRDMAQPC_RCVSCALE GENMASK_ULL(35, 32)
755 #define IRDMAQPC_SNDSCALE GENMASK_ULL(43, 40)
756 #define IRDMAQPC_PDIDX GENMASK_ULL(63, 48)
757 #define IRDMAQPC_PDIDXHI GENMASK_ULL(21, 20)
758 #define IRDMAQPC_PKEY GENMASK_ULL(47, 32)
759 #define IRDMAQPC_ACKCREDITS GENMASK_ULL(24, 20)
760 #define IRDMAQPC_QKEY GENMASK_ULL(63, 32)
761 #define IRDMAQPC_DESTQP GENMASK_ULL(23, 0)
762 #define IRDMAQPC_KALIVE_TIMER_MAX_PROBES GENMASK_ULL(23, 16)
763 #define IRDMAQPC_KEEPALIVE_INTERVAL GENMASK_ULL(31, 24)
764 #define IRDMAQPC_TIMESTAMP_RECENT GENMASK_ULL(31, 0)
765 #define IRDMAQPC_TIMESTAMP_AGE GENMASK_ULL(63, 32)
766 #define IRDMAQPC_SNDNXT GENMASK_ULL(31, 0)
767 #define IRDMAQPC_ISN GENMASK_ULL(55, 32)
768 #define IRDMAQPC_PSNNXT GENMASK_ULL(23, 0)
769 #define IRDMAQPC_LSN GENMASK_ULL(55, 32)
770 #define IRDMAQPC_SNDWND GENMASK_ULL(63, 32)
771 #define IRDMAQPC_RCVNXT GENMASK_ULL(31, 0)
772 #define IRDMAQPC_EPSN GENMASK_ULL(23, 0)
773 #define IRDMAQPC_RCVWND GENMASK_ULL(63, 32)
774 #define IRDMAQPC_SNDMAX GENMASK_ULL(31, 0)
775 #define IRDMAQPC_SNDUNA GENMASK_ULL(63, 32)
776 #define IRDMAQPC_PSNMAX GENMASK_ULL(23, 0)
777 #define IRDMAQPC_PSNUNA GENMASK_ULL(55, 32)
778 #define IRDMAQPC_SRTT GENMASK_ULL(31, 0)
779 #define IRDMAQPC_RTTVAR GENMASK_ULL(63, 32)
780 #define IRDMAQPC_SSTHRESH GENMASK_ULL(31, 0)
781 #define IRDMAQPC_CWND GENMASK_ULL(63, 32)
782 #define IRDMAQPC_CWNDROCE GENMASK_ULL(55, 32)
783 #define IRDMAQPC_SNDWL1 GENMASK_ULL(31, 0)
784 #define IRDMAQPC_SNDWL2 GENMASK_ULL(63, 32)
785 #define IRDMAQPC_ERR_RQ_IDX GENMASK_ULL(45, 32)
786 #define IRDMAQPC_RTOMIN GENMASK_ULL(63, 57)
787 #define IRDMAQPC_MAXSNDWND GENMASK_ULL(31, 0)
788 #define IRDMAQPC_REXMIT_THRESH GENMASK_ULL(53, 48)
789 #define IRDMAQPC_RNRNAK_THRESH GENMASK_ULL(56, 54)
790 #define IRDMAQPC_TXCQNUM GENMASK_ULL(18, 0)
791 #define IRDMAQPC_RXCQNUM GENMASK_ULL(50, 32)
792 #define IRDMAQPC_STAT_INDEX GENMASK_ULL(6, 0)
793 #define IRDMAQPC_Q2ADDR GENMASK_ULL(63, 8)
794 #define IRDMAQPC_LASTBYTESENT GENMASK_ULL(7, 0)
795 #define IRDMAQPC_MACADDRESS GENMASK_ULL(63, 16)
796 #define IRDMAQPC_ORDSIZE GENMASK_ULL(7, 0)
798 #define IRDMAQPC_IRDSIZE GENMASK_ULL(18, 16)
811 #define IRDMAQPC_THIGH GENMASK_ULL(63, 52)
812 #define IRDMAQPC_TLOW GENMASK_ULL(39, 32)
813 #define IRDMAQPC_REMENDPOINTIDX GENMASK_ULL(16, 0)
819 #define IRDMAQPC_RCVMARKOFFSET GENMASK_ULL(40, 32)
820 #define IRDMAQPC_SNDMARKOFFSET GENMASK_ULL(56, 48)
823 #define IRDMAQPC_SQTPHVAL GENMASK_ULL(7, 0)
824 #define IRDMAQPC_RQTPHVAL GENMASK_ULL(15, 8)
825 #define IRDMAQPC_QSHANDLE GENMASK_ULL(25, 16)
826 #define IRDMAQPC_EXCEPTION_LAN_QUEUE GENMASK_ULL(43, 32)
827 #define IRDMAQPC_LOCAL_IPADDR3 GENMASK_ULL(31, 0)
828 #define IRDMAQPC_LOCAL_IPADDR2 GENMASK_ULL(63, 32)
829 #define IRDMAQPC_LOCAL_IPADDR1 GENMASK_ULL(31, 0)
830 #define IRDMAQPC_LOCAL_IPADDR0 GENMASK_ULL(63, 32)
831 #define IRDMA_FW_VER_MINOR GENMASK_ULL(15, 0)
832 #define IRDMA_FW_VER_MAJOR GENMASK_ULL(31, 16)
833 #define IRDMA_FEATURE_INFO GENMASK_ULL(47, 0)
834 #define IRDMA_FEATURE_CNT GENMASK_ULL(47, 32)
835 #define IRDMA_FEATURE_TYPE GENMASK_ULL(63, 48)
837 #define IRDMAQPSQ_OPCODE GENMASK_ULL(37, 32)
839 #define IRDMAQPSQ_ADDFRAGCNT GENMASK_ULL(41, 38)
846 #define IRDMAQPSQ_L4LEN GENMASK_ULL(45, 42)
852 #define IRDMAQPSQ_FRAG_LEN GENMASK_ULL(62, 32)
853 #define IRDMAQPSQ_FRAG_STAG GENMASK_ULL(31, 0)
854 #define IRDMAQPSQ_GEN1_FRAG_LEN GENMASK_ULL(31, 0)
855 #define IRDMAQPSQ_GEN1_FRAG_STAG GENMASK_ULL(63, 32)
856 #define IRDMAQPSQ_REMSTAGINV GENMASK_ULL(31, 0)
857 #define IRDMAQPSQ_DESTQKEY GENMASK_ULL(31, 0)
858 #define IRDMAQPSQ_DESTQPN GENMASK_ULL(55, 32)
859 #define IRDMAQPSQ_AHID GENMASK_ULL(16, 0)
863 #define IRDMAQPSQ_INLINEDATALEN GENMASK_ULL(55, 48)
867 #define IRDMAQPSQ_IMMDATA GENMASK_ULL(63, 0)
868 #define IRDMAQPSQ_REMSTAG GENMASK_ULL(31, 0)
872 #define IRDMAQPSQ_STAGRIGHTS GENMASK_ULL(52, 48)
877 #define IRDMAQPSQ_PARENTMRSTAG GENMASK_ULL(63, 32)
878 #define IRDMAQPSQ_MWSTAG GENMASK_ULL(31, 0)
882 #define IRDMAQPSQ_LOCSTAG GENMASK_ULL(31, 0)
884 #define IRDMAQPSQ_STAGKEY GENMASK_ULL(7, 0)
885 #define IRDMAQPSQ_STAGINDEX GENMASK_ULL(31, 8)
887 #define IRDMAQPSQ_LPBLSIZE GENMASK_ULL(45, 44)
888 #define IRDMAQPSQ_HPAGESIZE GENMASK_ULL(47, 46)
889 #define IRDMAQPSQ_STAGLEN GENMASK_ULL(40, 0)
890 #define IRDMAQPSQ_FIRSTPMPBLIDXLO GENMASK_ULL(63, 48)
891 #define IRDMAQPSQ_FIRSTPMPBLIDXHI GENMASK_ULL(11, 0)
892 #define IRDMAQPSQ_PBLADDR GENMASK_ULL(63, 12)
906 #define IRDMA_QUERY_FPM_MAX_QPS GENMASK_ULL(18, 0)
907 #define IRDMA_QUERY_FPM_MAX_CQS GENMASK_ULL(19, 0)
908 #define IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX GENMASK_ULL(13, 0)
909 #define IRDMA_QUERY_FPM_MAX_PE_SDS GENMASK_ULL(45, 32)
910 #define IRDMA_QUERY_FPM_MAX_CEQS GENMASK_ULL(9, 0)
911 #define IRDMA_QUERY_FPM_XFBLOCKSIZE GENMASK_ULL(63, 32)
912 #define IRDMA_QUERY_FPM_Q1BLOCKSIZE GENMASK_ULL(63, 32)
913 #define IRDMA_QUERY_FPM_HTMULTIPLIER GENMASK_ULL(19, 16)
914 #define IRDMA_QUERY_FPM_TIMERBUCKET GENMASK_ULL(47, 32)
915 #define IRDMA_QUERY_FPM_RRFBLOCKSIZE GENMASK_ULL(63, 32)
916 #define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE GENMASK_ULL(63, 32)
917 #define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE GENMASK_ULL(63, 32)
918 #define IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID GENMASK_ULL(5, 0)