Lines Matching refs:GENMASK_ULL

90 #define ERDMA_CQDB_IDX_MASK GENMASK_ULL(63, 56)
91 #define ERDMA_CQDB_CQN_MASK GENMASK_ULL(55, 32)
94 #define ERDMA_CQDB_CMDSN_MASK GENMASK_ULL(29, 28)
95 #define ERDMA_CQDB_CI_MASK GENMASK_ULL(23, 0)
98 #define ERDMA_EQDB_CI_MASK GENMASK_ULL(23, 0)
155 #define ERDMA_CMD_HDR_WQEBB_CNT_MASK GENMASK_ULL(54, 52)
156 #define ERDMA_CMD_HDR_CONTEXT_COOKIE_MASK GENMASK_ULL(47, 32)
157 #define ERDMA_CMD_HDR_SUB_MOD_MASK GENMASK_ULL(25, 24)
158 #define ERDMA_CMD_HDR_OPCODE_MASK GENMASK_ULL(23, 16)
159 #define ERDMA_CMD_HDR_WQEBB_INDEX_MASK GENMASK_ULL(15, 0)
220 #define ERDMA_CMD_ALLOC_DB_RESP_RDB_MASK GENMASK_ULL(63, 48)
221 #define ERDMA_CMD_ALLOC_DB_RESP_CDB_MASK GENMASK_ULL(47, 32)
222 #define ERDMA_CMD_ALLOC_DB_RESP_SDB_MASK GENMASK_ULL(15, 0)
327 #define ERDMA_CMDQ_CREATE_QP_RESP_COOKIE_MASK GENMASK_ULL(31, 0)
361 #define ERDMA_CMD_DEV_CAP_MAX_CQE_MASK GENMASK_ULL(47, 40)
362 #define ERDMA_CMD_DEV_CAP_FLAGS_MASK GENMASK_ULL(31, 24)
363 #define ERDMA_CMD_DEV_CAP_MAX_RECV_WR_MASK GENMASK_ULL(23, 16)
364 #define ERDMA_CMD_DEV_CAP_MAX_MR_SIZE_MASK GENMASK_ULL(7, 0)
367 #define ERDMA_CMD_DEV_CAP_DMA_LOCAL_KEY_MASK GENMASK_ULL(63, 32)
368 #define ERDMA_CMD_DEV_CAP_DEFAULT_CC_MASK GENMASK_ULL(31, 28)
369 #define ERDMA_CMD_DEV_CAP_QBLOCK_MASK GENMASK_ULL(27, 16)
370 #define ERDMA_CMD_DEV_CAP_MAX_MW_MASK GENMASK_ULL(7, 0)
380 #define ERDMA_CMD_INFO0_FW_VER_MASK GENMASK_ULL(31, 0)
423 #define ERDMA_SQE_HDR_SGL_LEN_MASK GENMASK_ULL(63, 56)
424 #define ERDMA_SQE_HDR_WQEBB_CNT_MASK GENMASK_ULL(54, 52)
425 #define ERDMA_SQE_HDR_QPN_MASK GENMASK_ULL(51, 32)
426 #define ERDMA_SQE_HDR_OPCODE_MASK GENMASK_ULL(31, 27)
432 #define ERDMA_SQE_HDR_WQEBB_INDEX_MASK GENMASK_ULL(15, 0)
498 #define ERDMA_CEQE_HDR_PI_MASK GENMASK_ULL(55, 32)
500 #define ERDMA_CEQE_HDR_CQN_MASK GENMASK_ULL(19, 0)