Lines Matching refs:st
389 static int ad4130_get_reg_size(struct ad4130_state *st, unsigned int reg, in ad4130_get_reg_size() argument
400 static unsigned int ad4130_data_reg_size(struct ad4130_state *st) in ad4130_data_reg_size() argument
405 ret = ad4130_get_reg_size(st, AD4130_DATA_REG, &data_reg_size); in ad4130_data_reg_size()
412 static unsigned int ad4130_resolution(struct ad4130_state *st) in ad4130_resolution() argument
414 return ad4130_data_reg_size(st) * BITS_PER_BYTE; in ad4130_resolution()
419 struct ad4130_state *st = context; in ad4130_reg_write() local
423 ret = ad4130_get_reg_size(st, reg, &size); in ad4130_reg_write()
427 st->reg_write_tx_buf[0] = reg; in ad4130_reg_write()
431 put_unaligned_be24(val, &st->reg_write_tx_buf[1]); in ad4130_reg_write()
434 put_unaligned_be16(val, &st->reg_write_tx_buf[1]); in ad4130_reg_write()
437 st->reg_write_tx_buf[1] = val; in ad4130_reg_write()
443 return spi_write(st->spi, st->reg_write_tx_buf, size + 1); in ad4130_reg_write()
448 struct ad4130_state *st = context; in ad4130_reg_read() local
451 .tx_buf = st->reg_read_tx_buf, in ad4130_reg_read()
452 .len = sizeof(st->reg_read_tx_buf), in ad4130_reg_read()
455 .rx_buf = st->reg_read_rx_buf, in ad4130_reg_read()
461 ret = ad4130_get_reg_size(st, reg, &size); in ad4130_reg_read()
465 st->reg_read_tx_buf[0] = AD4130_COMMS_READ_MASK | reg; in ad4130_reg_read()
468 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t)); in ad4130_reg_read()
474 *val = get_unaligned_be24(st->reg_read_rx_buf); in ad4130_reg_read()
477 *val = get_unaligned_be16(st->reg_read_rx_buf); in ad4130_reg_read()
480 *val = st->reg_read_rx_buf[0]; in ad4130_reg_read()
498 struct ad4130_state *st = gpiochip_get_data(gc); in ad4130_gpio_init_valid_mask() local
507 bool valid = st->pins_fn[pin] == AD4130_PIN_FN_NONE; in ad4130_gpio_init_valid_mask()
523 struct ad4130_state *st = gpiochip_get_data(gc); in ad4130_gpio_set() local
527 regmap_update_bits(st->regmap, AD4130_IO_CONTROL_REG, mask, in ad4130_gpio_set()
531 static int ad4130_set_mode(struct ad4130_state *st, enum ad4130_mode mode) in ad4130_set_mode() argument
533 return regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG, in ad4130_set_mode()
538 static int ad4130_set_watermark_interrupt_en(struct ad4130_state *st, bool en) in ad4130_set_watermark_interrupt_en() argument
540 return regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG, in ad4130_set_watermark_interrupt_en()
553 static int ad4130_set_fifo_mode(struct ad4130_state *st, in ad4130_set_fifo_mode() argument
556 return regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG, in ad4130_set_fifo_mode()
563 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_push_fifo_data() local
564 unsigned int data_reg_size = ad4130_data_reg_size(st); in ad4130_push_fifo_data()
565 unsigned int transfer_len = st->effective_watermark * data_reg_size; in ad4130_push_fifo_data()
566 unsigned int set_size = st->num_enabled_channels * data_reg_size; in ad4130_push_fifo_data()
570 st->fifo_tx_buf[1] = ad4130_watermark_reg_val(st->effective_watermark); in ad4130_push_fifo_data()
571 st->fifo_xfer[1].len = transfer_len; in ad4130_push_fifo_data()
573 ret = spi_sync(st->spi, &st->fifo_msg); in ad4130_push_fifo_data()
578 iio_push_to_buffers(indio_dev, &st->fifo_rx_buf[i]); in ad4130_push_fifo_data()
584 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_irq_handler() local
589 complete(&st->completion); in ad4130_irq_handler()
594 static int ad4130_find_slot(struct ad4130_state *st, in ad4130_find_slot() argument
604 struct ad4130_slot_info *slot_info = &st->slots_info[i]; in ad4130_find_slot()
619 slot_info->channels < st->slots_info[*slot].channels) in ad4130_find_slot()
631 static void ad4130_unlink_channel(struct ad4130_state *st, unsigned int channel) in ad4130_unlink_channel() argument
633 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_unlink_channel()
634 struct ad4130_slot_info *slot_info = &st->slots_info[chan_info->slot]; in ad4130_unlink_channel()
640 static int ad4130_unlink_slot(struct ad4130_state *st, unsigned int slot) in ad4130_unlink_slot() argument
645 struct ad4130_chan_info *chan_info = &st->chans_info[i]; in ad4130_unlink_slot()
650 ad4130_unlink_channel(st, i); in ad4130_unlink_slot()
656 static int ad4130_link_channel_slot(struct ad4130_state *st, in ad4130_link_channel_slot() argument
659 struct ad4130_slot_info *slot_info = &st->slots_info[slot]; in ad4130_link_channel_slot()
660 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_link_channel_slot()
663 ret = regmap_update_bits(st->regmap, AD4130_CHANNEL_X_REG(channel), in ad4130_link_channel_slot()
675 static int ad4130_write_slot_setup(struct ad4130_state *st, in ad4130_write_slot_setup() argument
690 ret = regmap_write(st->regmap, AD4130_CONFIG_X_REG(slot), val); in ad4130_write_slot_setup()
697 ret = regmap_write(st->regmap, AD4130_FILTER_X_REG(slot), val); in ad4130_write_slot_setup()
701 memcpy(&st->slots_info[slot].setup, setup_info, sizeof(*setup_info)); in ad4130_write_slot_setup()
706 static int ad4130_write_channel_setup(struct ad4130_state *st, in ad4130_write_channel_setup() argument
709 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_write_channel_setup()
746 ad4130_unlink_channel(st, channel); in ad4130_write_channel_setup()
753 ret = ad4130_find_slot(st, setup_info, &slot, &overwrite); in ad4130_write_channel_setup()
759 ad4130_unlink_channel(st, channel); in ad4130_write_channel_setup()
762 ret = ad4130_unlink_slot(st, slot); in ad4130_write_channel_setup()
766 ret = ad4130_write_slot_setup(st, slot, setup_info); in ad4130_write_channel_setup()
771 return ad4130_link_channel_slot(st, channel, slot); in ad4130_write_channel_setup()
774 static int ad4130_set_channel_enable(struct ad4130_state *st, in ad4130_set_channel_enable() argument
777 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_set_channel_enable()
785 ret = ad4130_write_channel_setup(st, channel, true); in ad4130_set_channel_enable()
790 slot_info = &st->slots_info[chan_info->slot]; in ad4130_set_channel_enable()
792 ret = regmap_update_bits(st->regmap, AD4130_CHANNEL_X_REG(channel), in ad4130_set_channel_enable()
881 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_set_filter_mode() local
883 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_set_filter_mode()
890 mutex_lock(&st->lock); in ad4130_set_filter_mode()
910 ret = ad4130_write_channel_setup(st, channel, false); in ad4130_set_filter_mode()
917 mutex_unlock(&st->lock); in ad4130_set_filter_mode()
925 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_get_filter_mode() local
927 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup; in ad4130_get_filter_mode()
930 mutex_lock(&st->lock); in ad4130_get_filter_mode()
932 mutex_unlock(&st->lock); in ad4130_get_filter_mode()
968 static int ad4130_set_channel_pga(struct ad4130_state *st, unsigned int channel, in ad4130_set_channel_pga() argument
971 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_set_channel_pga()
977 if (val == st->scale_tbls[setup_info->ref_sel][pga][0] && in ad4130_set_channel_pga()
978 val2 == st->scale_tbls[setup_info->ref_sel][pga][1]) in ad4130_set_channel_pga()
984 mutex_lock(&st->lock); in ad4130_set_channel_pga()
991 ret = ad4130_write_channel_setup(st, channel, false); in ad4130_set_channel_pga()
996 mutex_unlock(&st->lock); in ad4130_set_channel_pga()
1001 static int ad4130_set_channel_freq(struct ad4130_state *st, in ad4130_set_channel_freq() argument
1004 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_set_channel_freq()
1009 mutex_lock(&st->lock); in ad4130_set_channel_freq()
1019 ret = ad4130_write_channel_setup(st, channel, false); in ad4130_set_channel_freq()
1024 mutex_unlock(&st->lock); in ad4130_set_channel_freq()
1032 struct ad4130_state *st = iio_priv(indio_dev); in _ad4130_read_sample() local
1035 ret = ad4130_set_channel_enable(st, channel, true); in _ad4130_read_sample()
1039 reinit_completion(&st->completion); in _ad4130_read_sample()
1041 ret = ad4130_set_mode(st, AD4130_MODE_CONTINUOUS); in _ad4130_read_sample()
1045 ret = wait_for_completion_timeout(&st->completion, in _ad4130_read_sample()
1050 ret = ad4130_set_mode(st, AD4130_MODE_IDLE); in _ad4130_read_sample()
1054 ret = regmap_read(st->regmap, AD4130_DATA_REG, val); in _ad4130_read_sample()
1058 ret = ad4130_set_channel_enable(st, channel, false); in _ad4130_read_sample()
1068 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_read_sample() local
1075 mutex_lock(&st->lock); in ad4130_read_sample()
1077 mutex_unlock(&st->lock); in ad4130_read_sample()
1088 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_read_raw() local
1090 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup; in ad4130_read_raw()
1096 mutex_lock(&st->lock); in ad4130_read_raw()
1097 *val = st->scale_tbls[setup_info->ref_sel][setup_info->pga][0]; in ad4130_read_raw()
1098 *val2 = st->scale_tbls[setup_info->ref_sel][setup_info->pga][1]; in ad4130_read_raw()
1099 mutex_unlock(&st->lock); in ad4130_read_raw()
1103 *val = st->bipolar ? -BIT(chan->scan_type.realbits - 1) : 0; in ad4130_read_raw()
1107 mutex_lock(&st->lock); in ad4130_read_raw()
1110 mutex_unlock(&st->lock); in ad4130_read_raw()
1123 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_read_avail() local
1125 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup; in ad4130_read_avail()
1130 *vals = (int *)st->scale_tbls[setup_info->ref_sel]; in ad4130_read_avail()
1131 *length = ARRAY_SIZE(st->scale_tbls[setup_info->ref_sel]) * 2; in ad4130_read_avail()
1137 mutex_lock(&st->lock); in ad4130_read_avail()
1139 mutex_unlock(&st->lock); in ad4130_read_avail()
1168 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_write_raw() local
1173 return ad4130_set_channel_pga(st, channel, val, val2); in ad4130_write_raw()
1175 return ad4130_set_channel_freq(st, channel, val, val2); in ad4130_write_raw()
1184 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_reg_access() local
1187 return regmap_read(st->regmap, reg, readval); in ad4130_reg_access()
1189 return regmap_write(st->regmap, reg, writeval); in ad4130_reg_access()
1195 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_update_scan_mode() local
1200 mutex_lock(&st->lock); in ad4130_update_scan_mode()
1203 ret = ad4130_set_channel_enable(st, channel, true); in ad4130_update_scan_mode()
1210 st->num_enabled_channels = val; in ad4130_update_scan_mode()
1213 mutex_unlock(&st->lock); in ad4130_update_scan_mode()
1220 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_set_fifo_watermark() local
1227 eff = val * st->num_enabled_channels; in ad4130_set_fifo_watermark()
1233 eff = rounddown(AD4130_FIFO_SIZE, st->num_enabled_channels); in ad4130_set_fifo_watermark()
1235 mutex_lock(&st->lock); in ad4130_set_fifo_watermark()
1237 ret = regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG, in ad4130_set_fifo_watermark()
1244 st->effective_watermark = eff; in ad4130_set_fifo_watermark()
1245 st->watermark = val; in ad4130_set_fifo_watermark()
1248 mutex_unlock(&st->lock); in ad4130_set_fifo_watermark()
1265 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_buffer_postenable() local
1268 mutex_lock(&st->lock); in ad4130_buffer_postenable()
1270 ret = ad4130_set_watermark_interrupt_en(st, true); in ad4130_buffer_postenable()
1274 ret = irq_set_irq_type(st->spi->irq, st->inv_irq_trigger); in ad4130_buffer_postenable()
1278 ret = ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_WM); in ad4130_buffer_postenable()
1282 ret = ad4130_set_mode(st, AD4130_MODE_CONTINUOUS); in ad4130_buffer_postenable()
1285 mutex_unlock(&st->lock); in ad4130_buffer_postenable()
1292 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_buffer_predisable() local
1296 mutex_lock(&st->lock); in ad4130_buffer_predisable()
1298 ret = ad4130_set_mode(st, AD4130_MODE_IDLE); in ad4130_buffer_predisable()
1302 ret = irq_set_irq_type(st->spi->irq, st->irq_trigger); in ad4130_buffer_predisable()
1306 ret = ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_DISABLED); in ad4130_buffer_predisable()
1310 ret = ad4130_set_watermark_interrupt_en(st, false); in ad4130_buffer_predisable()
1319 ret = ad4130_set_channel_enable(st, i, false); in ad4130_buffer_predisable()
1325 mutex_unlock(&st->lock); in ad4130_buffer_predisable()
1338 struct ad4130_state *st = iio_priv(dev_to_iio_dev(dev)); in hwfifo_watermark_show() local
1341 mutex_lock(&st->lock); in hwfifo_watermark_show()
1342 val = st->watermark; in hwfifo_watermark_show()
1343 mutex_unlock(&st->lock); in hwfifo_watermark_show()
1351 struct ad4130_state *st = iio_priv(dev_to_iio_dev(dev)); in hwfifo_enabled_show() local
1355 ret = regmap_read(st->regmap, AD4130_FIFO_CONTROL_REG, &val); in hwfifo_enabled_show()
1406 static int ad4130_get_ref_voltage(struct ad4130_state *st, in ad4130_get_ref_voltage() argument
1411 return regulator_get_voltage(st->regulators[2].consumer); in ad4130_get_ref_voltage()
1413 return regulator_get_voltage(st->regulators[3].consumer); in ad4130_get_ref_voltage()
1415 return regulator_get_voltage(st->regulators[0].consumer); in ad4130_get_ref_voltage()
1417 return st->int_ref_uv; in ad4130_get_ref_voltage()
1423 static int ad4130_parse_fw_setup(struct ad4130_state *st, in ad4130_parse_fw_setup() argument
1427 struct device *dev = &st->spi->dev; in ad4130_parse_fw_setup()
1467 st->int_ref_en = true; in ad4130_parse_fw_setup()
1469 ret = ad4130_get_ref_voltage(st, setup_info->ref_sel); in ad4130_parse_fw_setup()
1477 static int ad4130_validate_diff_channel(struct ad4130_state *st, u32 pin) in ad4130_validate_diff_channel() argument
1479 struct device *dev = &st->spi->dev; in ad4130_validate_diff_channel()
1488 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL) in ad4130_validate_diff_channel()
1491 st->pins_fn[pin]); in ad4130_validate_diff_channel()
1493 st->pins_fn[pin] |= AD4130_PIN_FN_DIFF; in ad4130_validate_diff_channel()
1498 static int ad4130_validate_diff_channels(struct ad4130_state *st, in ad4130_validate_diff_channels() argument
1505 ret = ad4130_validate_diff_channel(st, pins[i]); in ad4130_validate_diff_channels()
1513 static int ad4130_validate_excitation_pin(struct ad4130_state *st, u32 pin) in ad4130_validate_excitation_pin() argument
1515 struct device *dev = &st->spi->dev; in ad4130_validate_excitation_pin()
1521 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL) in ad4130_validate_excitation_pin()
1524 st->pins_fn[pin]); in ad4130_validate_excitation_pin()
1526 st->pins_fn[pin] |= AD4130_PIN_FN_EXCITATION; in ad4130_validate_excitation_pin()
1531 static int ad4130_validate_vbias_pin(struct ad4130_state *st, u32 pin) in ad4130_validate_vbias_pin() argument
1533 struct device *dev = &st->spi->dev; in ad4130_validate_vbias_pin()
1539 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL) in ad4130_validate_vbias_pin()
1542 st->pins_fn[pin]); in ad4130_validate_vbias_pin()
1544 st->pins_fn[pin] |= AD4130_PIN_FN_VBIAS; in ad4130_validate_vbias_pin()
1549 static int ad4130_validate_vbias_pins(struct ad4130_state *st, in ad4130_validate_vbias_pins() argument
1555 for (i = 0; i < st->num_vbias_pins; i++) { in ad4130_validate_vbias_pins()
1556 ret = ad4130_validate_vbias_pin(st, pins[i]); in ad4130_validate_vbias_pins()
1567 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_parse_fw_channel() local
1568 unsigned int resolution = ad4130_resolution(st); in ad4130_parse_fw_channel()
1570 struct device *dev = &st->spi->dev; in ad4130_parse_fw_channel()
1579 chan = &st->chans[index]; in ad4130_parse_fw_channel()
1580 chan_info = &st->chans_info[index]; in ad4130_parse_fw_channel()
1596 ret = ad4130_validate_diff_channels(st, pins, ARRAY_SIZE(pins)); in ad4130_parse_fw_channel()
1603 ret = ad4130_parse_fw_setup(st, child, &chan_info->setup); in ad4130_parse_fw_channel()
1610 ret = ad4130_validate_excitation_pin(st, chan_info->iout0); in ad4130_parse_fw_channel()
1618 ret = ad4130_validate_excitation_pin(st, chan_info->iout1); in ad4130_parse_fw_channel()
1628 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_parse_fw_children() local
1629 struct device *dev = &st->spi->dev; in ad4130_parse_fw_children()
1633 indio_dev->channels = st->chans; in ad4130_parse_fw_children()
1648 struct ad4130_state *st = iio_priv(indio_dev); in ad4310_parse_fw() local
1649 struct device *dev = &st->spi->dev; in ad4310_parse_fw()
1656 st->mclk = devm_clk_get_optional(dev, "mclk"); in ad4310_parse_fw()
1657 if (IS_ERR(st->mclk)) in ad4310_parse_fw()
1658 return dev_err_probe(dev, PTR_ERR(st->mclk), in ad4310_parse_fw()
1661 st->int_pin_sel = AD4130_INT_PIN_INT; in ad4310_parse_fw()
1667 st->int_pin_sel = i; in ad4310_parse_fw()
1672 if (st->int_pin_sel == AD4130_INT_PIN_DOUT) in ad4310_parse_fw()
1676 if (st->int_pin_sel == AD4130_INT_PIN_P2) in ad4310_parse_fw()
1677 st->pins_fn[AD4130_AIN3_P2] = AD4130_PIN_FN_SPECIAL; in ad4310_parse_fw()
1686 if (st->mclk && ext_clk_freq == AD4130_MCLK_FREQ_153_6KHZ) in ad4310_parse_fw()
1687 st->mclk_sel = AD4130_MCLK_153_6KHZ_EXT; in ad4310_parse_fw()
1688 else if (st->mclk) in ad4310_parse_fw()
1689 st->mclk_sel = AD4130_MCLK_76_8KHZ_EXT; in ad4310_parse_fw()
1691 st->mclk_sel = AD4130_MCLK_76_8KHZ; in ad4310_parse_fw()
1693 if (st->int_pin_sel == AD4130_INT_PIN_CLK && in ad4310_parse_fw()
1694 st->mclk_sel != AD4130_MCLK_76_8KHZ) in ad4310_parse_fw()
1697 st->mclk_sel, st->int_pin_sel); in ad4310_parse_fw()
1699 st->int_ref_uv = AD4130_INT_REF_2_5V; in ad4310_parse_fw()
1706 avdd_uv = regulator_get_voltage(st->regulators[0].consumer); in ad4310_parse_fw()
1708 st->int_ref_uv = AD4130_INT_REF_1_25V; in ad4310_parse_fw()
1710 st->bipolar = device_property_read_bool(dev, "adi,bipolar"); in ad4310_parse_fw()
1718 st->num_vbias_pins = ret; in ad4310_parse_fw()
1721 st->vbias_pins, in ad4310_parse_fw()
1722 st->num_vbias_pins); in ad4310_parse_fw()
1727 ret = ad4130_validate_vbias_pins(st, st->vbias_pins, in ad4310_parse_fw()
1728 st->num_vbias_pins); in ad4310_parse_fw()
1740 static void ad4130_fill_scale_tbls(struct ad4130_state *st) in ad4130_fill_scale_tbls() argument
1742 unsigned int pow = ad4130_resolution(st) - st->bipolar; in ad4130_fill_scale_tbls()
1749 ret = ad4130_get_ref_voltage(st, i); in ad4130_fill_scale_tbls()
1756 st->scale_tbls[i][j][1] = div_u64(nv >> (pow + j), MILLI); in ad4130_fill_scale_tbls()
1765 static int ad4130_set_mclk_sel(struct ad4130_state *st, in ad4130_set_mclk_sel() argument
1768 return regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG, in ad4130_set_mclk_sel()
1782 struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw); in ad4130_int_clk_is_enabled() local
1784 return st->mclk_sel == AD4130_MCLK_76_8KHZ_OUT; in ad4130_int_clk_is_enabled()
1789 struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw); in ad4130_int_clk_prepare() local
1792 ret = ad4130_set_mclk_sel(st, AD4130_MCLK_76_8KHZ_OUT); in ad4130_int_clk_prepare()
1796 st->mclk_sel = AD4130_MCLK_76_8KHZ_OUT; in ad4130_int_clk_prepare()
1803 struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw); in ad4130_int_clk_unprepare() local
1806 ret = ad4130_set_mclk_sel(st, AD4130_MCLK_76_8KHZ); in ad4130_int_clk_unprepare()
1810 st->mclk_sel = AD4130_MCLK_76_8KHZ; in ad4130_int_clk_unprepare()
1825 static int ad4130_setup_int_clk(struct ad4130_state *st) in ad4130_setup_int_clk() argument
1827 struct device *dev = &st->spi->dev; in ad4130_setup_int_clk()
1834 if (st->int_pin_sel == AD4130_INT_PIN_CLK || in ad4130_setup_int_clk()
1835 st->mclk_sel != AD4130_MCLK_76_8KHZ) in ad4130_setup_int_clk()
1847 st->int_clk_hw.init = &init; in ad4130_setup_int_clk()
1848 clk = devm_clk_register(dev, &st->int_clk_hw); in ad4130_setup_int_clk()
1861 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_setup() local
1862 struct device *dev = &st->spi->dev; in ad4130_setup()
1869 if (st->mclk_sel == AD4130_MCLK_153_6KHZ_EXT) in ad4130_setup()
1872 ret = clk_set_rate(st->mclk, rate); in ad4130_setup()
1876 ret = clk_prepare_enable(st->mclk); in ad4130_setup()
1881 st->mclk); in ad4130_setup()
1885 if (st->int_ref_uv == AD4130_INT_REF_2_5V) in ad4130_setup()
1892 val |= FIELD_PREP(AD4130_ADC_CONTROL_BIPOLAR_MASK, st->bipolar); in ad4130_setup()
1893 val |= FIELD_PREP(AD4130_ADC_CONTROL_INT_REF_EN_MASK, st->int_ref_en); in ad4130_setup()
1895 val |= FIELD_PREP(AD4130_ADC_CONTROL_MCLK_SEL_MASK, st->mclk_sel); in ad4130_setup()
1898 ret = regmap_write(st->regmap, AD4130_ADC_CONTROL_REG, val); in ad4130_setup()
1908 if (st->pins_fn[i + AD4130_AIN2_P1] == AD4130_PIN_FN_NONE) in ad4130_setup()
1911 val |= FIELD_PREP(AD4130_IO_CONTROL_INT_PIN_SEL_MASK, st->int_pin_sel); in ad4130_setup()
1913 ret = regmap_write(st->regmap, AD4130_IO_CONTROL_REG, val); in ad4130_setup()
1918 for (i = 0; i < st->num_vbias_pins; i++) in ad4130_setup()
1919 val |= BIT(st->vbias_pins[i]); in ad4130_setup()
1921 ret = regmap_write(st->regmap, AD4130_VBIAS_REG, val); in ad4130_setup()
1925 ret = regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG, in ad4130_setup()
1931 ret = ad4130_set_watermark_interrupt_en(st, false); in ad4130_setup()
1937 struct ad4130_chan_info *chan_info = &st->chans_info[i]; in ad4130_setup()
1938 struct iio_chan_spec *chan = &st->chans[i]; in ad4130_setup()
1946 ret = regmap_write(st->regmap, AD4130_CHANNEL_X_REG(i), val); in ad4130_setup()
1954 static int ad4130_soft_reset(struct ad4130_state *st) in ad4130_soft_reset() argument
1958 ret = spi_write(st->spi, st->reset_buf, sizeof(st->reset_buf)); in ad4130_soft_reset()
1969 struct ad4130_state *st = data; in ad4130_disable_regulators() local
1971 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators); in ad4130_disable_regulators()
1978 struct ad4130_state *st; in ad4130_probe() local
1981 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); in ad4130_probe()
1985 st = iio_priv(indio_dev); in ad4130_probe()
1987 memset(st->reset_buf, 0xff, sizeof(st->reset_buf)); in ad4130_probe()
1988 init_completion(&st->completion); in ad4130_probe()
1989 mutex_init(&st->lock); in ad4130_probe()
1990 st->spi = spi; in ad4130_probe()
1997 st->fifo_tx_buf[0] = AD4130_COMMS_READ_MASK | AD4130_FIFO_DATA_REG; in ad4130_probe()
1998 st->fifo_xfer[0].tx_buf = st->fifo_tx_buf; in ad4130_probe()
1999 st->fifo_xfer[0].len = sizeof(st->fifo_tx_buf); in ad4130_probe()
2000 st->fifo_xfer[1].rx_buf = st->fifo_rx_buf; in ad4130_probe()
2001 spi_message_init_with_transfers(&st->fifo_msg, st->fifo_xfer, in ad4130_probe()
2002 ARRAY_SIZE(st->fifo_xfer)); in ad4130_probe()
2008 st->regmap = devm_regmap_init(dev, NULL, st, &ad4130_regmap_config); in ad4130_probe()
2009 if (IS_ERR(st->regmap)) in ad4130_probe()
2010 return PTR_ERR(st->regmap); in ad4130_probe()
2012 st->regulators[0].supply = "avdd"; in ad4130_probe()
2013 st->regulators[1].supply = "iovdd"; in ad4130_probe()
2014 st->regulators[2].supply = "refin1"; in ad4130_probe()
2015 st->regulators[3].supply = "refin2"; in ad4130_probe()
2017 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators), in ad4130_probe()
2018 st->regulators); in ad4130_probe()
2022 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators); in ad4130_probe()
2026 ret = devm_add_action_or_reset(dev, ad4130_disable_regulators, st); in ad4130_probe()
2031 ret = ad4130_soft_reset(st); in ad4130_probe()
2043 ret = ad4130_setup_int_clk(st); in ad4130_probe()
2047 ad4130_fill_scale_tbls(st); in ad4130_probe()
2049 st->gc.owner = THIS_MODULE; in ad4130_probe()
2050 st->gc.label = AD4130_NAME; in ad4130_probe()
2051 st->gc.base = -1; in ad4130_probe()
2052 st->gc.ngpio = AD4130_MAX_GPIOS; in ad4130_probe()
2053 st->gc.parent = dev; in ad4130_probe()
2054 st->gc.can_sleep = true; in ad4130_probe()
2055 st->gc.init_valid_mask = ad4130_gpio_init_valid_mask; in ad4130_probe()
2056 st->gc.get_direction = ad4130_gpio_get_direction; in ad4130_probe()
2057 st->gc.set = ad4130_gpio_set; in ad4130_probe()
2059 ret = devm_gpiochip_add_data(dev, &st->gc, st); in ad4130_probe()
2083 st->irq_trigger = irq_get_trigger_type(spi->irq); in ad4130_probe()
2084 if (st->irq_trigger & IRQF_TRIGGER_RISING) in ad4130_probe()
2085 st->inv_irq_trigger = IRQF_TRIGGER_FALLING; in ad4130_probe()
2086 else if (st->irq_trigger & IRQF_TRIGGER_FALLING) in ad4130_probe()
2087 st->inv_irq_trigger = IRQF_TRIGGER_RISING; in ad4130_probe()
2090 st->irq_trigger); in ad4130_probe()