Lines Matching refs:uint8_t
46 uint8_t DisplayPhy1Config;
47 uint8_t DisplayPhy2Config;
48 uint8_t DisplayPhy3Config;
49 uint8_t DisplayPhy4Config;
51 uint8_t DisplayPhy5Config;
52 uint8_t DisplayPhy6Config;
53 uint8_t DisplayPhy7Config;
54 uint8_t DisplayPhy8Config;
60 uint8_t SClkDpmEnabledLevels;
61 uint8_t MClkDpmEnabledLevels;
62 uint8_t LClkDpmEnabledLevels;
63 uint8_t PCIeDpmEnabledLevels;
65 uint8_t UVDDpmEnabledLevels;
66 uint8_t SAMUDpmEnabledLevels;
67 uint8_t ACPDpmEnabledLevels;
68 uint8_t VCEDpmEnabledLevels;
89 uint8_t Vid;
90 uint8_t VidOffset;
93 uint8_t PowerThrottle;
94 uint8_t GnbSlow;
95 uint8_t ForceNbPs1;
96 uint8_t SclkDid;
98 uint8_t DisplayWatermark;
99 uint8_t EnabledForActivity;
100 uint8_t EnabledForThrottle;
101 uint8_t UpH;
103 uint8_t DownH;
104 uint8_t VoltageDownH;
105 uint8_t DeepSleepDivId;
107 uint8_t ClkBypassCntl;
116 uint8_t EnabledForActivity;
117 uint8_t LclkDid;
118 uint8_t Vid;
119 uint8_t VoltageDownH;
124 uint8_t UpH;
125 uint8_t DownH;
129 uint8_t ActivityLevel;
130 uint8_t EnabledForThrottle;
132 uint8_t ClkBypassCntl;
134 uint8_t padding;
145 uint8_t VclkDivider;
146 uint8_t DclkDivider;
148 uint8_t VClkBypassCntl;
149 uint8_t DClkBypassCntl;
151 uint8_t padding[2];
162 uint8_t Divider;
163 uint8_t ClkBypassCntl;
174 uint8_t SclkDid;
175 uint8_t GnbSlow;
176 uint8_t ForceNbPs1;
177 uint8_t DisplayWatermark;
178 uint8_t DeepSleepDivId;
179 uint8_t padding[3];
186 uint8_t DpmXNbPsHi;
187 uint8_t DpmXNbPsLo;
188 uint8_t Dpm0PgNbPsHi;
189 uint8_t Dpm0PgNbPsLo;
190 uint8_t EnablePsi1;
191 uint8_t SkipDPM0;
192 uint8_t SkipPG;
193 uint8_t Hysteresis;
194 uint8_t EnableDpmPstatePoll;
195 uint8_t padding[3];
209 uint8_t DisplayWatermark;
210 uint8_t McArbIndex;
224 uint8_t GraphicsDpmLevelCount;
225 uint8_t GIOLevelCount;
226 uint8_t UvdLevelCount;
227 uint8_t VceLevelCount;
229 uint8_t AcpLevelCount;
230 uint8_t SamuLevelCount;
240 uint8_t UvdBootLevel;
241 uint8_t VceBootLevel;
242 uint8_t AcpBootLevel;
243 uint8_t SamuBootLevel;
244 uint8_t UVDInterval;
245 uint8_t VCEInterval;
246 uint8_t ACPInterval;
247 uint8_t SAMUInterval;
249 uint8_t GraphicsBootLevel;
250 uint8_t GraphicsInterval;
251 uint8_t GraphicsThermThrottleEnable;
252 uint8_t GraphicsVoltageChangeEnable;
254 uint8_t GraphicsClkSlowEnable;
255 uint8_t GraphicsClkSlowDivider;
278 uint8_t Enable;
279 uint8_t GIOVoltageChangeEnable;
280 uint8_t GIOBootLevel;
281 uint8_t padding;
282 uint8_t padding1[2];
283 uint8_t TargetState;
284 uint8_t CurrenttState;
285 uint8_t ThrottleOnHtc;
286 uint8_t ThermThrottleStatus;
287 uint8_t ThermThrottleTempSelect;
288 uint8_t ThermThrottleEnable;