Lines Matching refs:pi
153 struct kv_power_info *pi = rdev->pm.dpm.priv; in kv_get_pi() local
155 return pi; in kv_get_pi()
209 struct kv_power_info *pi = kv_get_pi(rdev); in kv_do_enable_didt() local
212 if (pi->caps_sq_ramping) { in kv_do_enable_didt()
221 if (pi->caps_db_ramping) { in kv_do_enable_didt()
230 if (pi->caps_td_ramping) { in kv_do_enable_didt()
239 if (pi->caps_tcp_ramping) { in kv_do_enable_didt()
251 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_didt() local
254 if (pi->caps_sq_ramping || in kv_enable_didt()
255 pi->caps_db_ramping || in kv_enable_didt()
256 pi->caps_td_ramping || in kv_enable_didt()
257 pi->caps_tcp_ramping) { in kv_enable_didt()
278 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_smc_cac() local
281 if (pi->caps_cac) { in kv_enable_smc_cac()
285 pi->cac_enabled = false; in kv_enable_smc_cac()
287 pi->cac_enabled = true; in kv_enable_smc_cac()
288 } else if (pi->cac_enabled) { in kv_enable_smc_cac()
290 pi->cac_enabled = false; in kv_enable_smc_cac()
299 struct kv_power_info *pi = kv_get_pi(rdev); in kv_process_firmware_header() local
305 &tmp, pi->sram_end); in kv_process_firmware_header()
308 pi->dpm_table_start = tmp; in kv_process_firmware_header()
312 &tmp, pi->sram_end); in kv_process_firmware_header()
315 pi->soft_regs_start = tmp; in kv_process_firmware_header()
322 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_dpm_voltage_scaling() local
325 pi->graphics_voltage_change_enable = 1; in kv_enable_dpm_voltage_scaling()
328 pi->dpm_table_start + in kv_enable_dpm_voltage_scaling()
330 &pi->graphics_voltage_change_enable, in kv_enable_dpm_voltage_scaling()
331 sizeof(u8), pi->sram_end); in kv_enable_dpm_voltage_scaling()
338 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_dpm_interval() local
341 pi->graphics_interval = 1; in kv_set_dpm_interval()
344 pi->dpm_table_start + in kv_set_dpm_interval()
346 &pi->graphics_interval, in kv_set_dpm_interval()
347 sizeof(u8), pi->sram_end); in kv_set_dpm_interval()
354 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_dpm_boot_state() local
358 pi->dpm_table_start + in kv_set_dpm_boot_state()
360 &pi->graphics_boot_level, in kv_set_dpm_boot_state()
361 sizeof(u8), pi->sram_end); in kv_set_dpm_boot_state()
379 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_divider_value() local
388 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value()
389 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); in kv_set_divider_value()
449 struct kv_power_info *pi = kv_get_pi(rdev); in kv_convert_2bit_index_to_voltage() local
451 &pi->sys_info.vid_mapping_table, in kv_convert_2bit_index_to_voltage()
460 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_vid() local
462 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t; in kv_set_vid()
463 pi->graphics_level[index].MinVddNb = in kv_set_vid()
471 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_at() local
473 pi->graphics_level[index].AT = cpu_to_be16((u16)at); in kv_set_at()
481 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_power_level_enable() local
483 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0; in kv_dpm_power_level_enable()
541 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_sclk_t() local
545 if (pi->caps_sclk_throttle_low_notification) { in kv_update_sclk_t()
546 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); in kv_update_sclk_t()
549 pi->dpm_table_start + in kv_update_sclk_t()
552 sizeof(u32), pi->sram_end); in kv_update_sclk_t()
559 struct kv_power_info *pi = kv_get_pi(rdev); in kv_program_bootup_state() local
565 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_program_bootup_state()
566 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state()
570 pi->graphics_boot_level = (u8)i; in kv_program_bootup_state()
574 &pi->sys_info.sclk_voltage_mapping_table; in kv_program_bootup_state()
579 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_program_bootup_state()
580 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state()
584 pi->graphics_boot_level = (u8)i; in kv_program_bootup_state()
592 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_auto_thermal_throttling() local
595 pi->graphics_therm_throttle_enable = 1; in kv_enable_auto_thermal_throttling()
598 pi->dpm_table_start + in kv_enable_auto_thermal_throttling()
600 &pi->graphics_therm_throttle_enable, in kv_enable_auto_thermal_throttling()
601 sizeof(u8), pi->sram_end); in kv_enable_auto_thermal_throttling()
608 struct kv_power_info *pi = kv_get_pi(rdev); in kv_upload_dpm_settings() local
612 pi->dpm_table_start + in kv_upload_dpm_settings()
614 (u8 *)&pi->graphics_level, in kv_upload_dpm_settings()
616 pi->sram_end); in kv_upload_dpm_settings()
622 pi->dpm_table_start + in kv_upload_dpm_settings()
624 &pi->graphics_dpm_level_count, in kv_upload_dpm_settings()
625 sizeof(u8), pi->sram_end); in kv_upload_dpm_settings()
637 struct kv_power_info *pi = kv_get_pi(rdev); in kv_get_clk_bypass() local
640 if (pi->caps_enable_dfs_bypass) { in kv_get_clk_bypass()
662 struct kv_power_info *pi = kv_get_pi(rdev); in kv_populate_uvd_table() local
672 pi->uvd_level_count = 0; in kv_populate_uvd_table()
674 if (pi->high_voltage_t && in kv_populate_uvd_table()
675 (pi->high_voltage_t < table->entries[i].v)) in kv_populate_uvd_table()
678 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); in kv_populate_uvd_table()
679 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk); in kv_populate_uvd_table()
680 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v); in kv_populate_uvd_table()
682 pi->uvd_level[i].VClkBypassCntl = in kv_populate_uvd_table()
684 pi->uvd_level[i].DClkBypassCntl = in kv_populate_uvd_table()
691 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
697 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
699 pi->uvd_level_count++; in kv_populate_uvd_table()
703 pi->dpm_table_start + in kv_populate_uvd_table()
705 (u8 *)&pi->uvd_level_count, in kv_populate_uvd_table()
706 sizeof(u8), pi->sram_end); in kv_populate_uvd_table()
710 pi->uvd_interval = 1; in kv_populate_uvd_table()
713 pi->dpm_table_start + in kv_populate_uvd_table()
715 &pi->uvd_interval, in kv_populate_uvd_table()
716 sizeof(u8), pi->sram_end); in kv_populate_uvd_table()
721 pi->dpm_table_start + in kv_populate_uvd_table()
723 (u8 *)&pi->uvd_level, in kv_populate_uvd_table()
725 pi->sram_end); in kv_populate_uvd_table()
733 struct kv_power_info *pi = kv_get_pi(rdev); in kv_populate_vce_table() local
743 pi->vce_level_count = 0; in kv_populate_vce_table()
745 if (pi->high_voltage_t && in kv_populate_vce_table()
746 pi->high_voltage_t < table->entries[i].v) in kv_populate_vce_table()
749 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); in kv_populate_vce_table()
750 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_vce_table()
752 pi->vce_level[i].ClkBypassCntl = in kv_populate_vce_table()
759 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()
761 pi->vce_level_count++; in kv_populate_vce_table()
765 pi->dpm_table_start + in kv_populate_vce_table()
767 (u8 *)&pi->vce_level_count, in kv_populate_vce_table()
769 pi->sram_end); in kv_populate_vce_table()
773 pi->vce_interval = 1; in kv_populate_vce_table()
776 pi->dpm_table_start + in kv_populate_vce_table()
778 (u8 *)&pi->vce_interval, in kv_populate_vce_table()
780 pi->sram_end); in kv_populate_vce_table()
785 pi->dpm_table_start + in kv_populate_vce_table()
787 (u8 *)&pi->vce_level, in kv_populate_vce_table()
789 pi->sram_end); in kv_populate_vce_table()
796 struct kv_power_info *pi = kv_get_pi(rdev); in kv_populate_samu_table() local
806 pi->samu_level_count = 0; in kv_populate_samu_table()
808 if (pi->high_voltage_t && in kv_populate_samu_table()
809 pi->high_voltage_t < table->entries[i].v) in kv_populate_samu_table()
812 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk); in kv_populate_samu_table()
813 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_samu_table()
815 pi->samu_level[i].ClkBypassCntl = in kv_populate_samu_table()
822 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table()
824 pi->samu_level_count++; in kv_populate_samu_table()
828 pi->dpm_table_start + in kv_populate_samu_table()
830 (u8 *)&pi->samu_level_count, in kv_populate_samu_table()
832 pi->sram_end); in kv_populate_samu_table()
836 pi->samu_interval = 1; in kv_populate_samu_table()
839 pi->dpm_table_start + in kv_populate_samu_table()
841 (u8 *)&pi->samu_interval, in kv_populate_samu_table()
843 pi->sram_end); in kv_populate_samu_table()
848 pi->dpm_table_start + in kv_populate_samu_table()
850 (u8 *)&pi->samu_level, in kv_populate_samu_table()
852 pi->sram_end); in kv_populate_samu_table()
862 struct kv_power_info *pi = kv_get_pi(rdev); in kv_populate_acp_table() local
872 pi->acp_level_count = 0; in kv_populate_acp_table()
874 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk); in kv_populate_acp_table()
875 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_acp_table()
881 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
883 pi->acp_level_count++; in kv_populate_acp_table()
887 pi->dpm_table_start + in kv_populate_acp_table()
889 (u8 *)&pi->acp_level_count, in kv_populate_acp_table()
891 pi->sram_end); in kv_populate_acp_table()
895 pi->acp_interval = 1; in kv_populate_acp_table()
898 pi->dpm_table_start + in kv_populate_acp_table()
900 (u8 *)&pi->acp_interval, in kv_populate_acp_table()
902 pi->sram_end); in kv_populate_acp_table()
907 pi->dpm_table_start + in kv_populate_acp_table()
909 (u8 *)&pi->acp_level, in kv_populate_acp_table()
911 pi->sram_end); in kv_populate_acp_table()
920 struct kv_power_info *pi = kv_get_pi(rdev); in kv_calculate_dfs_bypass_settings() local
926 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_calculate_dfs_bypass_settings()
927 if (pi->caps_enable_dfs_bypass) { in kv_calculate_dfs_bypass_settings()
929 pi->graphics_level[i].ClkBypassCntl = 3; in kv_calculate_dfs_bypass_settings()
931 pi->graphics_level[i].ClkBypassCntl = 2; in kv_calculate_dfs_bypass_settings()
933 pi->graphics_level[i].ClkBypassCntl = 7; in kv_calculate_dfs_bypass_settings()
935 pi->graphics_level[i].ClkBypassCntl = 6; in kv_calculate_dfs_bypass_settings()
937 pi->graphics_level[i].ClkBypassCntl = 8; in kv_calculate_dfs_bypass_settings()
939 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
941 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
946 &pi->sys_info.sclk_voltage_mapping_table; in kv_calculate_dfs_bypass_settings()
947 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_calculate_dfs_bypass_settings()
948 if (pi->caps_enable_dfs_bypass) { in kv_calculate_dfs_bypass_settings()
950 pi->graphics_level[i].ClkBypassCntl = 3; in kv_calculate_dfs_bypass_settings()
952 pi->graphics_level[i].ClkBypassCntl = 2; in kv_calculate_dfs_bypass_settings()
954 pi->graphics_level[i].ClkBypassCntl = 7; in kv_calculate_dfs_bypass_settings()
956 pi->graphics_level[i].ClkBypassCntl = 6; in kv_calculate_dfs_bypass_settings()
958 pi->graphics_level[i].ClkBypassCntl = 8; in kv_calculate_dfs_bypass_settings()
960 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
962 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
976 struct kv_power_info *pi = kv_get_pi(rdev); in kv_reset_acp_boot_level() local
978 pi->acp_boot_level = 0xff; in kv_reset_acp_boot_level()
985 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_current_ps() local
987 pi->current_rps = *rps; in kv_update_current_ps()
988 pi->current_ps = *new_ps; in kv_update_current_ps()
989 pi->current_rps.ps_priv = &pi->current_ps; in kv_update_current_ps()
996 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_requested_ps() local
998 pi->requested_rps = *rps; in kv_update_requested_ps()
999 pi->requested_ps = *new_ps; in kv_update_requested_ps()
1000 pi->requested_rps.ps_priv = &pi->requested_ps; in kv_update_requested_ps()
1005 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_enable_bapm() local
1008 if (pi->bapm_enable) { in kv_dpm_enable_bapm()
1030 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_enable() local
1074 if (pi->enable_auto_thermal_throttling) { in kv_dpm_enable()
1175 struct kv_power_info *pi = kv_get_pi(rdev); in kv_init_sclk_t() local
1177 pi->low_sclk_interrupt_t = 0; in kv_init_sclk_t()
1182 struct kv_power_info *pi = kv_get_pi(rdev); in kv_init_fps_limits() local
1185 if (pi->caps_fps) { in kv_init_fps_limits()
1189 pi->fps_high_t = cpu_to_be16(tmp); in kv_init_fps_limits()
1191 pi->dpm_table_start + in kv_init_fps_limits()
1193 (u8 *)&pi->fps_high_t, in kv_init_fps_limits()
1194 sizeof(u16), pi->sram_end); in kv_init_fps_limits()
1197 pi->fps_low_t = cpu_to_be16(tmp); in kv_init_fps_limits()
1200 pi->dpm_table_start + in kv_init_fps_limits()
1202 (u8 *)&pi->fps_low_t, in kv_init_fps_limits()
1203 sizeof(u16), pi->sram_end); in kv_init_fps_limits()
1211 struct kv_power_info *pi = kv_get_pi(rdev); in kv_init_powergate_state() local
1213 pi->uvd_power_gated = false; in kv_init_powergate_state()
1214 pi->vce_power_gated = false; in kv_init_powergate_state()
1215 pi->samu_power_gated = false; in kv_init_powergate_state()
1216 pi->acp_power_gated = false; in kv_init_powergate_state()
1246 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_uvd_dpm() local
1254 pi->uvd_boot_level = table->count - 1; in kv_update_uvd_dpm()
1256 pi->uvd_boot_level = 0; in kv_update_uvd_dpm()
1258 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) { in kv_update_uvd_dpm()
1259 mask = 1 << pi->uvd_boot_level; in kv_update_uvd_dpm()
1265 pi->dpm_table_start + in kv_update_uvd_dpm()
1267 (uint8_t *)&pi->uvd_boot_level, in kv_update_uvd_dpm()
1268 sizeof(u8), pi->sram_end); in kv_update_uvd_dpm()
1298 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_vce_dpm() local
1307 if (pi->caps_stable_p_state) in kv_update_vce_dpm()
1308 pi->vce_boot_level = table->count - 1; in kv_update_vce_dpm()
1310 pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk); in kv_update_vce_dpm()
1313 pi->dpm_table_start + in kv_update_vce_dpm()
1315 (u8 *)&pi->vce_boot_level, in kv_update_vce_dpm()
1317 pi->sram_end); in kv_update_vce_dpm()
1321 if (pi->caps_stable_p_state) in kv_update_vce_dpm()
1324 (1 << pi->vce_boot_level)); in kv_update_vce_dpm()
1339 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_samu_dpm() local
1345 if (pi->caps_stable_p_state) in kv_update_samu_dpm()
1346 pi->samu_boot_level = table->count - 1; in kv_update_samu_dpm()
1348 pi->samu_boot_level = 0; in kv_update_samu_dpm()
1351 pi->dpm_table_start + in kv_update_samu_dpm()
1353 (u8 *)&pi->samu_boot_level, in kv_update_samu_dpm()
1355 pi->sram_end); in kv_update_samu_dpm()
1359 if (pi->caps_stable_p_state) in kv_update_samu_dpm()
1362 (1 << pi->samu_boot_level)); in kv_update_samu_dpm()
1387 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_acp_boot_level() local
1390 if (!pi->caps_stable_p_state) { in kv_update_acp_boot_level()
1392 if (acp_boot_level != pi->acp_boot_level) { in kv_update_acp_boot_level()
1393 pi->acp_boot_level = acp_boot_level; in kv_update_acp_boot_level()
1396 (1 << pi->acp_boot_level)); in kv_update_acp_boot_level()
1403 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_acp_dpm() local
1409 if (pi->caps_stable_p_state) in kv_update_acp_dpm()
1410 pi->acp_boot_level = table->count - 1; in kv_update_acp_dpm()
1412 pi->acp_boot_level = kv_get_acp_boot_level(rdev); in kv_update_acp_dpm()
1415 pi->dpm_table_start + in kv_update_acp_dpm()
1417 (u8 *)&pi->acp_boot_level, in kv_update_acp_dpm()
1419 pi->sram_end); in kv_update_acp_dpm()
1423 if (pi->caps_stable_p_state) in kv_update_acp_dpm()
1426 (1 << pi->acp_boot_level)); in kv_update_acp_dpm()
1434 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_powergate_uvd() local
1436 if (pi->uvd_power_gated == gate) in kv_dpm_powergate_uvd()
1439 pi->uvd_power_gated = gate; in kv_dpm_powergate_uvd()
1442 if (pi->caps_uvd_pg) { in kv_dpm_powergate_uvd()
1447 if (pi->caps_uvd_pg) in kv_dpm_powergate_uvd()
1450 if (pi->caps_uvd_pg) { in kv_dpm_powergate_uvd()
1462 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_powergate_vce() local
1464 if (pi->vce_power_gated == gate) in kv_dpm_powergate_vce()
1467 pi->vce_power_gated = gate; in kv_dpm_powergate_vce()
1470 if (pi->caps_vce_pg) { in kv_dpm_powergate_vce()
1475 if (pi->caps_vce_pg) { in kv_dpm_powergate_vce()
1485 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_powergate_samu() local
1487 if (pi->samu_power_gated == gate) in kv_dpm_powergate_samu()
1490 pi->samu_power_gated = gate; in kv_dpm_powergate_samu()
1494 if (pi->caps_samu_pg) in kv_dpm_powergate_samu()
1497 if (pi->caps_samu_pg) in kv_dpm_powergate_samu()
1505 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_powergate_acp() local
1507 if (pi->acp_power_gated == gate) in kv_dpm_powergate_acp()
1513 pi->acp_power_gated = gate; in kv_dpm_powergate_acp()
1517 if (pi->caps_acp_pg) in kv_dpm_powergate_acp()
1520 if (pi->caps_acp_pg) in kv_dpm_powergate_acp()
1530 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_valid_clock_range() local
1536 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_set_valid_clock_range()
1538 (i == (pi->graphics_dpm_level_count - 1))) { in kv_set_valid_clock_range()
1539 pi->lowest_valid = i; in kv_set_valid_clock_range()
1544 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_set_valid_clock_range()
1548 pi->highest_valid = i; in kv_set_valid_clock_range()
1550 if (pi->lowest_valid > pi->highest_valid) { in kv_set_valid_clock_range()
1551 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range()
1552 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1553 pi->highest_valid = pi->lowest_valid; in kv_set_valid_clock_range()
1555 pi->lowest_valid = pi->highest_valid; in kv_set_valid_clock_range()
1559 &pi->sys_info.sclk_voltage_mapping_table; in kv_set_valid_clock_range()
1561 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) { in kv_set_valid_clock_range()
1563 i == (int)(pi->graphics_dpm_level_count - 1)) { in kv_set_valid_clock_range()
1564 pi->lowest_valid = i; in kv_set_valid_clock_range()
1569 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_set_valid_clock_range()
1574 pi->highest_valid = i; in kv_set_valid_clock_range()
1576 if (pi->lowest_valid > pi->highest_valid) { in kv_set_valid_clock_range()
1578 table->entries[pi->highest_valid].sclk_frequency) > in kv_set_valid_clock_range()
1579 (table->entries[pi->lowest_valid].sclk_frequency - in kv_set_valid_clock_range()
1581 pi->highest_valid = pi->lowest_valid; in kv_set_valid_clock_range()
1583 pi->lowest_valid = pi->highest_valid; in kv_set_valid_clock_range()
1592 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_dfs_bypass_settings() local
1596 if (pi->caps_enable_dfs_bypass) { in kv_update_dfs_bypass_settings()
1598 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0; in kv_update_dfs_bypass_settings()
1600 (pi->dpm_table_start + in kv_update_dfs_bypass_settings()
1602 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) + in kv_update_dfs_bypass_settings()
1605 sizeof(u8), pi->sram_end); in kv_update_dfs_bypass_settings()
1614 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_nb_dpm() local
1618 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) { in kv_enable_nb_dpm()
1621 pi->nb_dpm_enabled = true; in kv_enable_nb_dpm()
1624 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) { in kv_enable_nb_dpm()
1627 pi->nb_dpm_enabled = false; in kv_enable_nb_dpm()
1660 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_pre_set_power_state() local
1667 &pi->requested_rps, in kv_dpm_pre_set_power_state()
1668 &pi->current_rps); in kv_dpm_pre_set_power_state()
1675 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_set_power_state() local
1676 struct radeon_ps *new_ps = &pi->requested_rps; in kv_dpm_set_power_state()
1677 struct radeon_ps *old_ps = &pi->current_rps; in kv_dpm_set_power_state()
1680 if (pi->bapm_enable) { in kv_dpm_set_power_state()
1689 if (pi->enable_dpm) { in kv_dpm_set_power_state()
1718 if (pi->enable_dpm) { in kv_dpm_set_power_state()
1749 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_post_set_power_state() local
1750 struct radeon_ps *new_ps = &pi->requested_rps; in kv_dpm_post_set_power_state()
1767 struct kv_power_info *pi = kv_get_pi(rdev); in kv_construct_max_power_limits_table() local
1769 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) { in kv_construct_max_power_limits_table()
1770 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1; in kv_construct_max_power_limits_table()
1772 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency; in kv_construct_max_power_limits_table()
1775 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit); in kv_construct_max_power_limits_table()
1778 table->mclk = pi->sys_info.nbp_memory_clock[0]; in kv_construct_max_power_limits_table()
1825 struct kv_power_info *pi = kv_get_pi(rdev); in kv_construct_boot_state() local
1827 pi->boot_pl.sclk = pi->sys_info.bootup_sclk; in kv_construct_boot_state()
1828 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; in kv_construct_boot_state()
1829 pi->boot_pl.ds_divider_index = 0; in kv_construct_boot_state()
1830 pi->boot_pl.ss_divider_index = 0; in kv_construct_boot_state()
1831 pi->boot_pl.allow_gnb_slow = 1; in kv_construct_boot_state()
1832 pi->boot_pl.force_nbp_state = 0; in kv_construct_boot_state()
1833 pi->boot_pl.display_wm = 0; in kv_construct_boot_state()
1834 pi->boot_pl.vce_wm = 0; in kv_construct_boot_state()
1880 struct kv_power_info *pi = kv_get_pi(rdev); in kv_get_sleep_divider_id_from_clock() local
1889 if (!pi->caps_sclk_ds) in kv_get_sleep_divider_id_from_clock()
1903 struct kv_power_info *pi = kv_get_pi(rdev); in kv_get_high_voltage_limit() local
1910 if (pi->high_voltage_t && in kv_get_high_voltage_limit()
1912 pi->high_voltage_t)) { in kv_get_high_voltage_limit()
1919 &pi->sys_info.sclk_voltage_mapping_table; in kv_get_high_voltage_limit()
1922 if (pi->high_voltage_t && in kv_get_high_voltage_limit()
1924 pi->high_voltage_t)) { in kv_get_high_voltage_limit()
1940 struct kv_power_info *pi = kv_get_pi(rdev); in kv_apply_state_adjust_rules() local
1962 if (pi->caps_stable_p_state) { in kv_apply_state_adjust_rules()
1992 if (pi->high_voltage_t && in kv_apply_state_adjust_rules()
1993 (pi->high_voltage_t < in kv_apply_state_adjust_rules()
2001 &pi->sys_info.sclk_voltage_mapping_table; in kv_apply_state_adjust_rules()
2004 if (pi->high_voltage_t && in kv_apply_state_adjust_rules()
2005 (pi->high_voltage_t < in kv_apply_state_adjust_rules()
2013 if (pi->caps_stable_p_state) { in kv_apply_state_adjust_rules()
2019 pi->video_start = new_rps->dclk || new_rps->vclk || in kv_apply_state_adjust_rules()
2024 pi->battery_state = true; in kv_apply_state_adjust_rules()
2026 pi->battery_state = false; in kv_apply_state_adjust_rules()
2039 if (pi->sys_info.nb_dpm_enable) { in kv_apply_state_adjust_rules()
2040 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) || in kv_apply_state_adjust_rules()
2041 pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) || in kv_apply_state_adjust_rules()
2042 pi->disable_nb_ps3_in_battery; in kv_apply_state_adjust_rules()
2054 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_power_level_enabled_for_throttle() local
2056 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0; in kv_dpm_power_level_enabled_for_throttle()
2061 struct kv_power_info *pi = kv_get_pi(rdev); in kv_calculate_ds_divider() local
2065 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_ds_divider()
2068 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_ds_divider()
2069 pi->graphics_level[i].DeepSleepDivId = in kv_calculate_ds_divider()
2071 be32_to_cpu(pi->graphics_level[i].SclkFrequency), in kv_calculate_ds_divider()
2079 struct kv_power_info *pi = kv_get_pi(rdev); in kv_calculate_nbps_level_settings() local
2086 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_nbps_level_settings()
2090 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_nbps_level_settings()
2091 pi->graphics_level[i].GnbSlow = 1; in kv_calculate_nbps_level_settings()
2092 pi->graphics_level[i].ForceNbPs1 = 0; in kv_calculate_nbps_level_settings()
2093 pi->graphics_level[i].UpH = 0; in kv_calculate_nbps_level_settings()
2096 if (!pi->sys_info.nb_dpm_enable) in kv_calculate_nbps_level_settings()
2099 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) || in kv_calculate_nbps_level_settings()
2100 (rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); in kv_calculate_nbps_level_settings()
2103 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_calculate_nbps_level_settings()
2104 pi->graphics_level[i].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2106 if (pi->battery_state) in kv_calculate_nbps_level_settings()
2107 pi->graphics_level[0].ForceNbPs1 = 1; in kv_calculate_nbps_level_settings()
2109 pi->graphics_level[1].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2110 pi->graphics_level[2].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2111 pi->graphics_level[3].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2112 pi->graphics_level[4].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2115 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_nbps_level_settings()
2116 pi->graphics_level[i].GnbSlow = 1; in kv_calculate_nbps_level_settings()
2117 pi->graphics_level[i].ForceNbPs1 = 0; in kv_calculate_nbps_level_settings()
2118 pi->graphics_level[i].UpH = 0; in kv_calculate_nbps_level_settings()
2121 if (pi->sys_info.nb_dpm_enable && pi->battery_state) { in kv_calculate_nbps_level_settings()
2122 pi->graphics_level[pi->lowest_valid].UpH = 0x28; in kv_calculate_nbps_level_settings()
2123 pi->graphics_level[pi->lowest_valid].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2124 if (pi->lowest_valid != pi->highest_valid) in kv_calculate_nbps_level_settings()
2125 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1; in kv_calculate_nbps_level_settings()
2133 struct kv_power_info *pi = kv_get_pi(rdev); in kv_calculate_dpm_settings() local
2136 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_dpm_settings()
2139 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_calculate_dpm_settings()
2140 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0; in kv_calculate_dpm_settings()
2147 struct kv_power_info *pi = kv_get_pi(rdev); in kv_init_graphics_levels() local
2155 pi->graphics_dpm_level_count = 0; in kv_init_graphics_levels()
2157 if (pi->high_voltage_t && in kv_init_graphics_levels()
2158 (pi->high_voltage_t < in kv_init_graphics_levels()
2164 &pi->sys_info.vid_mapping_table, in kv_init_graphics_levels()
2167 kv_set_at(rdev, i, pi->at[i]); in kv_init_graphics_levels()
2169 pi->graphics_dpm_level_count++; in kv_init_graphics_levels()
2173 &pi->sys_info.sclk_voltage_mapping_table; in kv_init_graphics_levels()
2175 pi->graphics_dpm_level_count = 0; in kv_init_graphics_levels()
2177 if (pi->high_voltage_t && in kv_init_graphics_levels()
2178 pi->high_voltage_t < in kv_init_graphics_levels()
2184 kv_set_at(rdev, i, pi->at[i]); in kv_init_graphics_levels()
2186 pi->graphics_dpm_level_count++; in kv_init_graphics_levels()
2196 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_new_levels() local
2200 if (i >= pi->lowest_valid && i <= pi->highest_valid) in kv_enable_new_levels()
2216 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_enabled_levels() local
2219 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_set_enabled_levels()
2231 struct kv_power_info *pi = kv_get_pi(rdev); in kv_program_nbps_index_settings() local
2237 if (pi->sys_info.nb_dpm_enable) { in kv_program_nbps_index_settings()
2288 struct kv_power_info *pi = kv_get_pi(rdev); in kv_parse_sys_info_table() local
2305 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock); in kv_parse_sys_info_table()
2306 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock); in kv_parse_sys_info_table()
2307 pi->sys_info.bootup_nb_voltage_index = in kv_parse_sys_info_table()
2310 pi->sys_info.htc_tmp_lmt = 203; in kv_parse_sys_info_table()
2312 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt; in kv_parse_sys_info_table()
2314 pi->sys_info.htc_hyst_lmt = 5; in kv_parse_sys_info_table()
2316 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt; in kv_parse_sys_info_table()
2317 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { in kv_parse_sys_info_table()
2322 pi->sys_info.nb_dpm_enable = true; in kv_parse_sys_info_table()
2324 pi->sys_info.nb_dpm_enable = false; in kv_parse_sys_info_table()
2327 pi->sys_info.nbp_memory_clock[i] = in kv_parse_sys_info_table()
2329 pi->sys_info.nbp_n_clock[i] = in kv_parse_sys_info_table()
2334 pi->caps_enable_dfs_bypass = true; in kv_parse_sys_info_table()
2337 &pi->sys_info.sclk_voltage_mapping_table, in kv_parse_sys_info_table()
2341 &pi->sys_info.vid_mapping_table, in kv_parse_sys_info_table()
2374 struct kv_power_info *pi = kv_get_pi(rdev); in kv_patch_boot_state() local
2377 ps->levels[0] = pi->boot_pl; in kv_patch_boot_state()
2411 struct kv_power_info *pi = kv_get_pi(rdev); in kv_parse_pplib_clock_info() local
2423 if (pi->caps_sclk_ds) { in kv_parse_pplib_clock_info()
2521 struct kv_power_info *pi; in kv_dpm_init() local
2524 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL); in kv_dpm_init()
2525 if (pi == NULL) in kv_dpm_init()
2527 rdev->pm.dpm.priv = pi; in kv_dpm_init()
2538 pi->at[i] = TRINITY_AT_DFLT; in kv_dpm_init()
2540 pi->sram_end = SMC_RAM_END; in kv_dpm_init()
2544 pi->enable_nb_dpm = false; in kv_dpm_init()
2546 pi->enable_nb_dpm = true; in kv_dpm_init()
2548 pi->caps_power_containment = true; in kv_dpm_init()
2549 pi->caps_cac = true; in kv_dpm_init()
2550 pi->enable_didt = false; in kv_dpm_init()
2551 if (pi->enable_didt) { in kv_dpm_init()
2552 pi->caps_sq_ramping = true; in kv_dpm_init()
2553 pi->caps_db_ramping = true; in kv_dpm_init()
2554 pi->caps_td_ramping = true; in kv_dpm_init()
2555 pi->caps_tcp_ramping = true; in kv_dpm_init()
2558 pi->caps_sclk_ds = true; in kv_dpm_init()
2559 pi->enable_auto_thermal_throttling = true; in kv_dpm_init()
2560 pi->disable_nb_ps3_in_battery = false; in kv_dpm_init()
2564 pi->bapm_enable = true; in kv_dpm_init()
2566 pi->bapm_enable = false; in kv_dpm_init()
2568 pi->bapm_enable = false; in kv_dpm_init()
2570 pi->bapm_enable = true; in kv_dpm_init()
2572 pi->voltage_drop_t = 0; in kv_dpm_init()
2573 pi->caps_sclk_throttle_low_notification = false; in kv_dpm_init()
2574 pi->caps_fps = false; /* true? */ in kv_dpm_init()
2575 pi->caps_uvd_pg = true; in kv_dpm_init()
2576 pi->caps_uvd_dpm = true; in kv_dpm_init()
2577 pi->caps_vce_pg = false; /* XXX true */ in kv_dpm_init()
2578 pi->caps_samu_pg = false; in kv_dpm_init()
2579 pi->caps_acp_pg = false; in kv_dpm_init()
2580 pi->caps_stable_p_state = false; in kv_dpm_init()
2593 pi->enable_dpm = true; in kv_dpm_init()
2601 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_debugfs_print_current_performance_level() local
2611 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); in kv_dpm_debugfs_print_current_performance_level()
2615 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en"); in kv_dpm_debugfs_print_current_performance_level()
2616 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en"); in kv_dpm_debugfs_print_current_performance_level()
2624 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_get_current_sclk() local
2633 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); in kv_dpm_get_current_sclk()
2640 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_get_current_mclk() local
2642 return pi->sys_info.bootup_uma_clk; in kv_dpm_get_current_mclk()
2682 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_get_sclk() local
2683 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps); in kv_dpm_get_sclk()
2693 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_get_mclk() local
2695 return pi->sys_info.bootup_uma_clk; in kv_dpm_get_mclk()