1145 	uint32_t fb_format, fb_pitch_pixels, tiling_flags;  in dce4_crtc_do_set_base()  local
1187 		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |  in dce4_crtc_do_set_base()
1192 		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |  in dce4_crtc_do_set_base()
1200 		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |  in dce4_crtc_do_set_base()
1208 		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |  in dce4_crtc_do_set_base()
1215 		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |  in dce4_crtc_do_set_base()
1223 		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |  in dce4_crtc_do_set_base()
1231 		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |  in dce4_crtc_do_set_base()
1241 		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |  in dce4_crtc_do_set_base()
1251 		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |  in dce4_crtc_do_set_base()
1308 			fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);  in dce4_crtc_do_set_base()
1318 				fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);  in dce4_crtc_do_set_base()
1322 				fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);  in dce4_crtc_do_set_base()
1325 				fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);  in dce4_crtc_do_set_base()
1330 		fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);  in dce4_crtc_do_set_base()
1331 		fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);  in dce4_crtc_do_set_base()
1332 		fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);  in dce4_crtc_do_set_base()
1333 		fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);  in dce4_crtc_do_set_base()
1334 		fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);  in dce4_crtc_do_set_base()
1337 			fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);  in dce4_crtc_do_set_base()
1340 		fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);  in dce4_crtc_do_set_base()
1348 		fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);  in dce4_crtc_do_set_base()
1351 		fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);  in dce4_crtc_do_set_base()
1355 		fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);  in dce4_crtc_do_set_base()
1393 	WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);  in dce4_crtc_do_set_base()
1466 	uint32_t fb_format, fb_pitch_pixels, tiling_flags;  in avivo_crtc_do_set_base()  local
1506 		fb_format =  in avivo_crtc_do_set_base()
1512 		fb_format =  in avivo_crtc_do_set_base()
1520 		fb_format =  in avivo_crtc_do_set_base()
1528 		fb_format =  in avivo_crtc_do_set_base()
1537 		fb_format =  in avivo_crtc_do_set_base()
1546 		fb_format =  in avivo_crtc_do_set_base()
1557 		fb_format =  in avivo_crtc_do_set_base()
1565 			fb_format |= AVIVO_D1GRPH_SWAP_RB;  in avivo_crtc_do_set_base()
1578 			fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;  in avivo_crtc_do_set_base()
1580 			fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;  in avivo_crtc_do_set_base()
1583 			fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;  in avivo_crtc_do_set_base()
1586 			fb_format |= AVIVO_D1GRPH_TILED;  in avivo_crtc_do_set_base()
1612 	WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);  in avivo_crtc_do_set_base()