185 	ram_mask(hwsq, mr[0], 0x100, 0x100);  in nvkm_sddr2_dll_reset()
186 	ram_mask(hwsq, mr[0], 0x100, 0x000);  in nvkm_sddr2_dll_reset()
212 		ram_mask(hwsq, gpio[reg], (0x3 << sh), ((val | 0x2) << sh));  in nv50_ram_gpio()
305 		ram_mask(hwsq, 0x100710, 0x00000200, 0x00000000);  in nv50_ram_calc()
308 	ram_mask(hwsq, 0x100200, 0x00000800, 0x00000000);  in nv50_ram_calc()
350 	ram_mask(hwsq, 0x00c040, 0xc000c000, 0x0000c000);  in nv50_ram_calc()
353 	ram_mask(hwsq, 0x004008, 0x00004200, 0x00000200 |  in nv50_ram_calc()
355 	ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1);  in nv50_ram_calc()
356 	ram_mask(hwsq, 0x004008, 0x91ff0000, r004008);  in nv50_ram_calc()
366 	ram_mask(hwsq, 0x004008, 0x00002200, 0x00002000);  in nv50_ram_calc()
377 		ram_mask(hwsq, mr[0], 0x000, 0x000);  in nv50_ram_calc()
389 	ram_mask(hwsq, timing[3], 0xffffffff, timing[3]);  in nv50_ram_calc()
390 	ram_mask(hwsq, timing[1], 0xffffffff, timing[1]);  in nv50_ram_calc()
391 	ram_mask(hwsq, timing[6], 0xffffffff, timing[6]);  in nv50_ram_calc()
392 	ram_mask(hwsq, timing[7], 0xffffffff, timing[7]);  in nv50_ram_calc()
393 	ram_mask(hwsq, timing[8], 0xffffffff, timing[8]);  in nv50_ram_calc()
394 	ram_mask(hwsq, timing[0], 0xffffffff, timing[0]);  in nv50_ram_calc()
395 	ram_mask(hwsq, timing[2], 0xffffffff, timing[2]);  in nv50_ram_calc()
396 	ram_mask(hwsq, timing[4], 0xffffffff, timing[4]);  in nv50_ram_calc()
397 	ram_mask(hwsq, timing[5], 0xffffffff, timing[5]);  in nv50_ram_calc()
400 		ram_mask(hwsq, 0x10021c, 0x00010000, 0x00000000);  in nv50_ram_calc()
401 	ram_mask(hwsq, 0x100200, 0x00001000, !next->bios.ramcfg_00_04_02 << 12);  in nv50_ram_calc()
436 	ram_mask(hwsq, 0x100714, 0xffffffff, unk714);  in nv50_ram_calc()
437 	ram_mask(hwsq, 0x10071c, 0xffffffff, unk71c);  in nv50_ram_calc()
438 	ram_mask(hwsq, 0x100718, 0xffffffff, unk718);  in nv50_ram_calc()
439 	ram_mask(hwsq, 0x100710, 0xffffffff, unk710);  in nv50_ram_calc()
449 		ram_mask(hwsq, 0x10053c, 0x00001000, 0x00000000);  in nv50_ram_calc()
451 		ram_mask(hwsq, 0x10053c, 0x00001000, 0x00001000);  in nv50_ram_calc()
453 	ram_mask(hwsq, mr[1], 0xffffffff, ram->base.mr[1]);  in nv50_ram_calc()
468 		ram_mask(hwsq, 0x100200, 0x00000800, 0x00000800);  in nv50_ram_calc()
470 		ram_mask(hwsq, 0x004008, 0x00004000, 0x00000000);  in nv50_ram_calc()
472 		ram_mask(hwsq, 0x10021c, 0x00010000, 0x00010000);  in nv50_ram_calc()
474 		ram_mask(hwsq, 0x100710, 0x00000200, 0x00000200);  in nv50_ram_calc()