Lines Matching refs:b32
23 ctx_dma_query: .b32 0
24 ctx_dma_src: .b32 0
25 ctx_dma_dst: .b32 0
27 ctx_query_address_high: .b32 0
28 ctx_query_address_low: .b32 0
29 ctx_query_counter: .b32 0
30 ctx_cond_address_high: .b32 0
31 ctx_cond_address_low: .b32 0
32 ctx_cond_off: .b32 0
33 ctx_src_address_high: .b32 0
34 ctx_src_address_low: .b32 0
35 ctx_dst_address_high: .b32 0
36 ctx_dst_address_low: .b32 0
37 ctx_mode: .b32 0
48 .b32 #ctx_query_address_high + 0x20000 ~0xff
49 .b32 #ctx_query_address_low + 0x20000 ~0xfffffff0
50 .b32 #ctx_query_counter + 0x20000 ~0xffffffff
51 .b32 #cmd_query_get + 0x00000 ~1
52 .b32 #ctx_cond_address_high + 0x20000 ~0xff
53 .b32 #ctx_cond_address_low + 0x20000 ~0xfffffff0
54 .b32 #cmd_cond_mode + 0x00000 ~7
55 .b32 #cmd_wrcache_flush + 0x00000 ~0
61 .b32 #ctx_key + 0x0 + 0x20000 ~0xffffffff
62 .b32 #ctx_key + 0x4 + 0x20000 ~0xffffffff
63 .b32 #ctx_key + 0x8 + 0x20000 ~0xffffffff
64 .b32 #ctx_key + 0xc + 0x20000 ~0xffffffff
65 .b32 #ctx_iv + 0x0 + 0x20000 ~0xffffffff
66 .b32 #ctx_iv + 0x4 + 0x20000 ~0xffffffff
67 .b32 #ctx_iv + 0x8 + 0x20000 ~0xffffffff
68 .b32 #ctx_iv + 0xc + 0x20000 ~0xffffffff
69 .b32 #ctx_src_address_high + 0x20000 ~0xff
70 .b32 #ctx_src_address_low + 0x20000 ~0xfffffff0
71 .b32 #ctx_dst_address_high + 0x20000 ~0xff
72 .b32 #ctx_dst_address_low + 0x20000 ~0xfffffff0
73 .b32 #sec_cmd_mode + 0x00000 ~0xf
74 .b32 #sec_cmd_length + 0x10000 ~0x0ffffff0
100 clear b32 $r0
139 cmpu b32 $r2 0
154 shl b32 $r5 $r4 1
155 cmps b32 $r5 0
173 shl b32 $r15 $r4 1
174 cmps b32 $r15 0
185 ld b32 $r7 D[$r5 + $r6 * 4]
186 add b32 $r8 $r6 0x180
187 shl b32 $r8 8
189 sub b32 $r6 1
199 cmpu b32 $r2 0
209 shl b32 $r2 0x10
213 cmpu b32 $r5 0
218 cmpu b32 $r4 0xc0
222 cmpu b32 $r4 0x80
224 cmpu b32 $r4 0x60
226 cmpu b32 $r4 0x50
231 clear b32 $r3
238 cmpu b32 $r4 0x60+#dma_count
240 shl b32 $r5 $r4 2
241 add b32 $r5 ((#ctx_dma - 0x60 * 4) & 0xffff)
243 st b32 D[$r5] $r3
244 add b32 $r4 0x180 - 0x60
245 shl b32 $r4 8
250 cmpu b32 $r4 $r6
252 shl b32 $r4 3
253 add b32 $r4 $r5
254 ld b32 $r5 D[$r4 + 4]
256 cmpu b32 $r5 0
260 cmpu b32 $r6 2
262 ld b32 $r7 D[$r0 + #ctx_cond_off]
264 cmpu b32 $r6 1
271 st b32 D[$r5] $r3
288 cmpu b32 $r4 0
314 cmpu b32 $r6 $r7
318 ld b32 $r4 D[$r0 + #ctx_query_counter]
319 st b32 D[$r0 + #swap + 0x0] $r4
320 st b32 D[$r0 + #swap + 0x4] $r0
321 st b32 D[$r0 + #swap + 0x8] $r5
322 st b32 D[$r0 + #swap + 0xc] $r6
327 ld b32 $r4 D[$r0 + #ctx_query_address_high]
328 shl b32 $r4 0x18
331 ld b32 $r4 D[$r0 + #ctx_query_address_low]
343 cmpu b32 $r3 5
350 cmpu b32 $r3 2
354 st b32 D[$r0 + #ctx_cond_off] $r3
360 ld b32 $r4 D[$r0 + #ctx_cond_address_high]
361 ld b32 $r5 D[$r0 + #ctx_cond_address_low]
363 shr b32 $r5 8
364 shl b32 $r4 0x18
375 cmpu b32 $r3 2
379 ld b32 $r4 D[$r0 + #swap + 4]
380 cmpu b32 $r4 0
382 st b32 D[$r0 + #ctx_cond_off] $r4
387 add b32 $r6 0x10
388 add b32 $r5 0x10
393 ld b32 $r5 D[$r0 + #swap + 0x00]
394 ld b32 $r6 D[$r0 + #swap + 0x10]
395 cmpu b32 $r5 $r6
399 ld b32 $r5 D[$r0 + #swap + 0x04]
400 ld b32 $r6 D[$r0 + #swap + 0x14]
401 cmpu b32 $r5 $r6
406 cmpu b32 $r3 3
409 st b32 D[$r0 + #ctx_cond_off] $r4
415 clear b32 $r3
424 cmpu b32 $r3 0xf
428 st b32 D[$r0 + #ctx_mode] $r3
435 cmpu b32 $r3 0
454 ld b32 $r4 D[$r0 + #ctx_src_address_high]
455 ld b32 $r5 D[$r0 + #ctx_src_address_low]
456 shr b32 $r8 $r5 8
457 shl b32 $r4 0x18
462 ld b32 $r6 D[$r0 + #ctx_dst_address_high]
463 ld b32 $r7 D[$r0 + #ctx_dst_address_low]
464 shr b32 $r8 $r7 8
465 shl b32 $r6 0x18
470 ld b32 $r8 D[$r0 + #ctx_mode]
471 shl b32 $r8 2
487 shr b32 $r8 $r4 0x18
488 shl b32 $r9 $r4 8
489 add b32 $r9 $r5
490 adc b32 $r8 0
491 st b32 D[$r0 + #ctx_src_address_high] $r8
492 st b32 D[$r0 + #ctx_src_address_low] $r9
495 shr b32 $r8 $r6 0x18
496 shl b32 $r9 $r6 8
497 add b32 $r9 $r7
498 adc b32 $r8 0
499 st b32 D[$r0 + #ctx_dst_address_high] $r8
500 st b32 D[$r0 + #ctx_dst_address_low] $r9
640 add b32 $r3 $r5
651 add b32 $r5 0x10
652 cmpu b32 $r5 $r3
659 add b32 $r3 $r7
670 add b32 $r7 0x10
671 cmpu b32 $r7 $r3
676 add b32 $r3 $r5
692 add b32 $r5 0x10
693 add b32 $r7 0x10
694 cmpu b32 $r5 $r3